DETAILED ACTION
This Notice is responsive to communication filed on 11/04/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
An amendment filed on 11/11/2025 has been acknowledged and entered into the record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30 - 32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites the limitation "the first interconnection portion and the second interconnection portion of the third interconnection layer" dependent on claim 26 in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 31 recites the limitation "the first interconnection portion and the second interconnection portion of the first interconnection layer" dependent on claim 21 in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 32 recites the limitation "the first interconnection portion and the second interconnection portion of the second interconnection layer" dependent on claim 22 in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 21-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (US 20160005718), and further in view of Gamini (US 20160379967).
Regarding claim 1, Cheah teaches a semiconductor device, comprising:
a body Fig. 1A: 120 having;
a first lateral surface (bottom surface of Fig. 1C: 120),
a second lateral surface (left surface of surface of Fig. 1C: 120) angled relative to the first lateral surface (bottom surface of Fig. 1C: 120); and
a third lateral surface (top surface of Fig. 1C: 120) opposite to the first lateral surface (bottom surface of Fig. 1C: 120) and angled relative to the second lateral surface (left surface of Fig. 1C: 120);
wherein the body Fig. 1A: 120 comprises:
a first circuit layer Fig 1A: 122+124 comprising:
a first surface (Fig. 1A/1C bottom surface corresponding to first circuit layer) configured to form a part of the first lateral surface (bottom surface of Fig. 1C: 120) of the body Fig. 1A: 120;
a second surface (Fig. 1A/1C left surface corresponding to second circuit layer) configured to form a part of the second lateral surface (left surface of Fig. 1C: 120) of the body Fig. 1A: 120;
a first electrical contact Fig. 1A/1C: 104 disposed on the first surface;
a second electrical contact Fig. 1/A1C: 104 disposed on the second surface; and
a first interconnection structure Fig. 1A: 123+125+136+144 connecting the first electrical contact Fig. 1A/1C: 104 and the second electrical contact Fig. 1A/1C: 104 (para. 0021); and
a second circuit layer Fig. 1A: 126+128 comprising:
a third surface (Fig. 1A/1C bottom surface corresponding to second circuit layer) configured to form a part of the first lateral surface (bottom surface of Fig. 1C: 120) of the body Fig. 1A: 120;
a fourth surface (Fig. 1A/1C top surface corresponding to second circuit layer) configured to form a part of the third lateral surface (top surface of Fig. 1C: 120) of the body Fig. 1A: 120;
a third electrical contact Fig. 1A/1C: 104 disposed on the third surface;
a fourth electrical contact Fig. 1A/1C: 104 disposed on the fourth surface; and
a second interconnection structure Fig. 1A: 127+129+136+144 connecting the third electrical contact Fig. 1A/1C: 104 and the fourth contact Fig. 1A/1C: 104 (para. 0021),
wherein an angle between the first surface of the first circuit layer Fig 1A: 122+124 and the second surface of the first circuit layer Fig 1A: 122+124 is 90 degrees, and
wherein an angle between the third surface of the second circuit layer Fig. 1A: 126+128 and the fourth surface of the second circuit layer Fig. 1A: 126+128 is 90 degrees.
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But Cheah fails to explicitly teach wherein the first interconnection structure comprises a first interconnection layer extended between the first surface of the first circuit layer and the second surface of the first circuit layer to electrically connect the first electrical contact and the second electrical contact with each other; and wherein the second interconnection structure comprises a second interconnection layer extended between the third surface of the second circuit layer and the fourth surface of the second circuit layer to electrically connect the third electrical contact and the fourth electrical contact with each other.
However, Gamini teaches wherein the first interconnection structure comprises a first interconnection layer Fig. 2: 104 (corresponding to annotated first circuit layer) extended between the first surface Fig. 2: 106 of the first circuit layer (annotated below) and the second surface Fig. 2: 108 of the first circuit layer to electrically connect the first electrical contact Fig. 2: 202 (corresponding to surface 106) and the second electrical contact Fig. 2: 202 (corresponding to surface 108) with each other (para. 0047); and wherein the second interconnection structure comprises a second interconnection layer Fig. 2: 104 (corresponding to second circuit layer annotated below) extended between the third surface Fig. 2: 106 of the second circuit layer (annotated below) and the fourth surface Fig. 2: 108 of the second circuit layer to electrically connect the third electrical contact Fig. 2: 202 (corresponding to surface 106) and the fourth electrical contact Fig. 2: 202 (corresponding to surface 108) with each other (para. 0047).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine these teachings for the purpose of avoiding drilling vias through a substrate which can be susceptible to voids and gaps within the body of the interposer (para. 0036).
Cheah also fails to explicitly teach wherein the first interconnection layer is detoured 90 degrees to electrically connect the first electrical contact and the second electrical contact; and the second interconnection layer is detoured 90 degrees to electrically connect the third electrical contact and the fourth electrical contact.
However, Gamini teaches wherein the first interconnection layer Fig. 2: 104 is detoured 90 degrees to electrically connect the first electrical contact Fig. 2: 202 and the second electrical contact Fig. 2: 202 (see annotated below); and wherein the second interconnection layer Fig. 2: 104 is detoured 90 degrees to electrically connect the third electrical contact Fig. 2: 202 and the fourth electrical contact Fig. 2: 202 (see annotated below).
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Cheah, Guevara, and Gamini as an obvious matter of design choice (See MPEP 2144.04 (VI)(C) In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) and MPEP 2144.04 (IV)(B) In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). The specific limitation of the interconnection layer being detoured 90 degrees to electrically connect the electrical contacts is a matter of design and not a functional characteristic. Therefore, per In re Kuhle as cited above, this is held to be an obvious matter of design choice, and per In re Dailey, since this is a matter of choice and persuasive evidence of the claimed detour of the interconnection layer is absent, a person of ordinary skill in the art would have found the configuration of having the layer detoured at a 90° in order to connect contacts at connecting surfaces of the circuit layer to be obvious.
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Gamini’s Fig. 2 embodiment shows each circuit layer (wafers 110) includes contacts (conductive ends 202) on the side surfaces and interconnection layers (conductive traces 104) connecting the contacts (conductive ends 202) (see para. 0047).
Regarding claim 21, Cheah teaches the semiconductor device of claim 1, wherein the first interconnection structure Fig. 1A: 123+125+136+144 is covered by a first dielectric layer Fig. 1A/1B: 142 of the first circuit layer Fig 1A: 122+124. But Cheah fails to explicitly teach wherein the first electrical contact has an embedded portion embedded in the first surface of the first circuit layer and an exposed portion exposed out of the first surface of the first circuit layer, wherein the second electrical contact has an embedded portion embedded in the second surface of the first circuit layer and an exposed portion exposed out of the second surface of the first circuit layer, and wherein the first interconnection layer is integrally extended between the embedded portion of the first electrical contact and the embedded portion of the second electrical contact. However, Gamini teaches wherein the first electrical contact Fig. 2: 202 (corresponding to the first circuit layer) has an embedded portion embedded in the first surface Fig. 2: 106 of the first circuit layer (annotated first circuit layer above) and an exposed portion exposed out of the first surface of the first circuit layer, wherein the second electrical contact Fig. 2: 202 (corresponding to the first circuit layer) has an embedded portion embedded in the second surface Fig. 2: 108 of the first circuit layer and an exposed portion exposed out of the second surface of the first circuit layer, and wherein the first interconnection layer Fig. 2: 104 is integrally extended between the embedded portion of the first electrical contact Fig. 2: 202 and the embedded portion of the second electrical contact Fig. 2: 202. Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine these teachings for the purpose of enabling connection to active/passive devices, to additional interposers or packages (para. 0038/0068).
Regarding claim 22, Cheah teaches the semiconductor device of claim 1, wherein the second interconnection structure Fig. 1A: 127+129+136+144 is covered by a second dielectric layer Fig. 1A/1B: 142 of the second circuit layer Fig. 1A: 126+128. But Cheah fails to explicitly teach wherein the third electrical contact has an embedded portion embedded in the third surface of the second circuit layer and an exposed portion exposed out of the third surface of the second circuit layer, wherein the fourth electrical contact has an embedded portion embedded in the fourth surface of the second circuit layer and an exposed portion exposed out of the fourth surface of the second circuit layer, and wherein the second interconnection layer is integrally extended between the embedded portion of the third electrical contact and the embedded portion of the fourth electrical contact. However, Gamini teaches wherein the third electrical contact Fig. 2: 202 (corresponding to the second circuit layer) has an embedded portion embedded in the third surface Fig. 2: 106 of the second circuit layer (annotated second circuit layer above) and an exposed portion exposed out of the third surface of the second circuit layer, wherein the fourth electrical contact Fig. 2: 202 (corresponding to the second circuit layer) has an embedded portion embedded in the fourth surface Fig. 2: 108 of the second circuit layer and an exposed portion exposed out of the fourth surface of the second circuit layer, and wherein the second interconnection layer Fig. 2: 104 (corresponding to the second circuit layer) is integrally extended between the embedded portion of the third electrical contact Fig. 2: 202 and the embedded portion of the fourth electrical contact Fig. 2: 202. Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine these teachings for the purpose of enabling connection to active/passive devices, to additional interposers or packages (para. 0038/0068).
Regarding claim 23, Cheah teaches the semiconductor device of claim 1, wherein the first circuit layer Fig 1A: 122+124 is attached to the second circuit layer Fig. 1A: 126+128.
Regarding claim 24, Gamini teaches the semiconductor device of claim 1, wherein the first interconnection layer Fig. 2: 104 has a first interconnection portion extended to the first electrical contact Fig. 2: 202 and a second interconnection portion extended to the second electrical contact Fig. 2: 202, wherein the first interconnection portion and the second interconnection portion of the first interconnection layer Fig. 2: 104 are integrally extended from each other and are perpendicular to each other (see annotated Fig. 2 below, corresponding to a first circuit layer), wherein the second interconnection layer Fig. 2: 104 (corresponding to a second circuit layer) has a first interconnection portion extended to the third electrical contact Fig. 2: 202 and a second interconnection portion extended to the fourth electrical contact Fig. 2: 202, wherein the first interconnection portion and the second interconnection portion of the second interconnection layer are integrally extended from each other and are perpendicular to each other (see annotated Fig. 2 below, corresponding to a second circuit layer).
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Regarding claim 25, Cheah teaches the semiconductor device of claim 1, wherein the body Fig. 1A: 120 has a fourth lateral surface (annotated Fig. 1C above) opposite to the second lateral surface and angled relative to the first lateral surface, and wherein the body Fig. 1A: 120 further comprises a third circuit layer Fig. 1A: 130+132, and wherein the third circuit layer Fig. 1A: 130+132 comprises: a fifth surface (Fig. 1A/1C bottom surface corresponding to third circuit layer) configured to form a part of the first lateral surface of the body Fig. 1A: 120; a sixth surface (Fig. 1A/1C right surface corresponding to third circuit layer) configured to form a part of the fourth lateral surface of the body Fig. 1A: 120; a fifth electrical contact Fig. 1A/1C: 104 disposed on the fifth surface; a sixth electrical contact Fig. 1A/1C: 104 disposed on the sixth surface; and a third interconnection structure Fig. 1A: 131+133+136+144 connecting the fifth electrical contact Fig. 1A/1C: 104 and the sixth electrical contact Fig. 1A/1C: 104. But, Cheah fails to explicitly teach wherein the third interconnection structure comprises a third interconnection layer (see annotated below) extended between the fifth surface of the third circuit layer and the sixth surface of the third circuit layer to electrically connect the fifth electrical contact and the sixth electrical contact with each other. However, Gamini teaches wherein the third interconnection structure comprises a third interconnection layer Fig. 2: 104 (corresponding to a third circuit layer) extended between the fifth surface Fig. 2: 106 of the third circuit layer and the sixth surface Fig. 2: 108 of the third circuit layer to electrically connect the fifth electrical contact Fig. 2: 202 and the sixth electrical contact Fig. 2: 202 (corresponding to a third circuit layer) with each other.
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Regarding claim 26, Cheah teaches wherein the third interconnection structure Fig. 1A: 131+133+136+144 is covered by a third dielectric layer Fig. 1A/1B: 142 of the third circuit layer Fig. 1A: 130+132. But Cheah fails to explicitly teach wherein the fifth electrical has an embedded portion embedded in the fifth surface of the third circuit layer and an exposed portion exposed out of the fifth surface of the third circuit layer, wherein the sixth electrical contact has an embedded portion embedded in the sixth surface of the third circuit layer and an exposed portion exposed out of the sixth surface of the third circuit layer, wherein the third interconnection layer is integrally extended between the embedded portion of the fifth electrical contact and the embedded portion of the sixth electrical contact. However, Gamini teaches wherein the fifth electrical contact Fig. 2: 202 (corresponding to surface 106 of a third circuit layer) has an embedded portion embedded in the fifth surface Fig. 2: 106 of the third circuit layer and an exposed portion exposed out of the fifth surface Fig. 2: 106 of the third circuit layer, wherein the sixth electrical contact Fig. 2: 202 (corresponding to surface 108 of a third circuit layer) has an embedded portion embedded in the sixth surface Fig. 2: 108 of the third circuit layer and an exposed portion exposed out of the sixth surface of the third circuit layer, wherein the third interconnection layer Fig. 2: 104 (corresponding to a third circuit layer) is integrally extended between the embedded portion of the fifth electrical contact Fig. 2: 202 and the embedded portion of the sixth electrical contact Fig. 2: 202. Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine these teachings for the purpose of enabling connection to active/passive devices, to additional interposers or packages (para. 0038/0068).
Regarding claim 27, Cheah teaches wherein the third circuit layer Fig. 1A: 130+132 is attached to the second circuit layer Fig. 1A: 126+128.
Regarding claim 28, Gamini teaches the semiconductor device of claim 25, wherein the third interconnection layer Fig. 2: 104 (corresponding to a third circuit layer) has a first interconnection portion extended to the fifth electrical contact Fig. 2: 202 (corresponding to a third circuit layer) and a second interconnection portion extended to the sixth electrical contact Fig. 2: 202, wherein the first interconnection portion and the second interconnection portion of the third interconnection layer are integrally extended from each other and are perpendicular to each other (see annotated Fig. 2 below, corresponding to a third circuit layer).
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Regarding claim 29, Cheah teaches wherein the first interconnection structure Fig. 1A: 123+125+136+144, the second interconnection structure Fig. 1A: 127+129+136+144, and the third interconnection structure Fig. 1A: 131+133+136+144 are formed within the body Fig. 1A: 120.
Regarding claim 30, as this claim is previously rejected as being indefinite, Examiner will interpret this claim as being dependent on claim 28, Gamini teaches the semiconductor device of claim 28, wherein the first interconnection portion and the second interconnection portion of the third interconnection layer Fig. 2: 104 (corresponding to a third circuit layer) are integrally extended to the embedded portion of the fifth electrical contact Fig. 2: 202 and the embedded portion of the sixth electrical contact Fig. 2: 202 respectively to electrically connect the fifth electrical contact Fig. 2: 202 and the sixth electrical contact Fig. 2: 202 with each other (as shown in annotated Fig. 2 showing the first and second interconnection portions above). Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions.
Regarding claim 31, as this claim is previously rejected as being indefinite, Examiner will interpret this claim as being dependent on claim 24, Gamini teaches the semiconductor device of claim 24, wherein the first interconnection portion and the second interconnection portion of the first interconnection layer Fig. 2: 104 (corresponding to a first circuit layer) are integrally extended to the embedded portion of the first electrical contact Fig. 2: 202 and the embedded portion of the second electrical contact Fig. 2: 202 respectively to electrically connect the first electrical contact Fig. 2: 202 and the second electrical contact Fig. 2: 202 with each other (as shown in annotated Fig. 2 showing the first and second interconnection portions above). Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions.
Regarding claim 32, as this claim is previously rejected as being indefinite, Examiner will interpret this claim as being dependent on claim 24, Gamini teaches the semiconductor device of claim 24, wherein the first interconnection portion and the second interconnection portion of the second interconnection layer Fig. 2: 104 (corresponding to a second circuit layer) are integrally extended to the embedded portion of the third electrical contact Fig. 2: 202 and the embedded portion of the fourth electrical contact Fig. 2: 202 respectively to electrically connect the third electrical contact Fig. 2: 202 and the fourth electrical contact Fig. 2: 202 with each other (as shown in annotated Fig. 2 showing the first and second interconnection portions above). Fig. 2 shows that the interconnection layer 104 extends from one contact 202 on a surface 106 to another contact 202 on another surface 108, and para. 0054 teaches the conductive ends 202 (i.e. electrical contacts) can be below, with, or above the surfaces 106, 108. Fig. 10 also shows the conductive ends (i.e. 1002, 1000) having an embedded portion and an exposed portion, and where the conductive traces (i.e. 104) are extended between the embedded portions.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, and 21-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 11, 2026