DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 19, and 34 filed on 09/16/2025 have been fully considered for examination based on their merits. The previously presented claims 16-18, 20-31, 33, and 35 have been considered. New Claim 36 has been considered and entered. Claims 1-15, and 32 are canceled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 16-31, and 33-35, filed on 09/16/2025 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sin-Yao Huang et al, (hereinafter HUANG), US 20210193712 A1, in view of Alexander Kalnitsky et al, (hereinafter KALNITSKY), US 20160351604 A1, in view of Homayoon Haddad et al, (hereinafter HADDAD), US 20150270306 A1, and further in view of Amane Oishi, (hereinafter OISHI), US 20160218138 A1.
Regarding Claim 16, HUANG teaches in Figures 1A-1E, a method for forming an image sensor (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), the method comprising:
doping a first semiconductor layer (Fig. 1A, 102, substrate) having a first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]) with a first dopant (Fig. 1A, 102, in some embodiments, the substrate, 102 is doped with a first dopant, [0011]) to form a first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) having the first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]) in the first semiconductor layer (Fig. 1A, 102, substrate);
doping the first semiconductor layer (Fig. 1A, 102, substrate) with a second dopant (Fig. 1A, doping substrate, 102 with a second dopant, [0012]) to form a second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) having a second doping type (Fig. 1A, doping the substrate, 102, with a second dopant having a second conductivity type, [0012]), different than the first doping type (Fig. 1A, 102/(B1, B2, and B3), the second dopant is different than the first dopant, [0012]) in the first semiconductor layer (Fig. 1A, 102, substrate), wherein the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) are formed laterally beside one another (annotated Figure 1A) in the first semiconductor layer (Fig. 1A, 102, substrate), and wherein a first side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) extends vertically (annotated Figure 1A) along a side of the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) at a p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]) between the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]);
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etching (Fig. 1B, in some embodiments, the patterning process may include a photolithography process and an etching process, [0015]) the first semiconductor layer (Fig. 1A, 102, substrate) to form a trench (Fig. 1B, OP1/OP2, openings, [0015]) in the first semiconductor layer (Fig. 1A, 102, substrate) laterally (annotated Figure 1B) beside the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), wherein a sidewall of the first semiconductor layer (Fig. 1A, 102, substrate) that delimits the trench extends vertically along a second side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), opposite the first side (Fig. 1B, 102BK, backside of the substrate, 102 doped with first dopant); and
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forming a second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) having the first doping type (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), of the first conductivity type, [0011]) in the trench (Fig. 1B, OP1/OP2, openings, [0015]) and along the second side (Fig. 1B, 102BK, backside) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]).
Though HUANG teaches a method of forming an image sensor, the method further comprising: a first semiconductor layer, a first doping region, a second doping region and a second semiconductor layer, and the p-n junction between the first doped region and the second doped region, HUANG does not explicitly disclose a method of forming an image sensor, the method further comprising: wherein the first doped region and the second doped region are formed laterally beside one another in the first semiconductor layer, and wherein a first side of the first doped region extends vertically along a side of the second doped region at a p-n junction between the first doped region and the second doped region.
KALNITSKY teaches a method of forming an image sensor (Fig. 15, diagrammatic fragmentary cross-sectional views of a back side illuminated (BSI) image sensor at various stages of fabrication, [0004]), the method comprising: wherein the first doped region (Fig. 15, 108, epi layer) and the second doped region (Fig. 15, 902, epi layer) are formed laterally beside one another (annotated Figure 15) in the first semiconductor layer (Fig. 15, 102, substrate), and wherein a first side (Fig. 15, 10, front side) of the first doped region (Fig. 15, 108, epi layer) extends vertically (annotated Figure 15) along a side of the second doped region (Fig. 15, 902, epi layer at a p-n junction (Fig. 15, 806, p-n junctions) between the first doped region (Fig. 15, 108, epi layer) and the second doped region (Fig. 15, 902, epi layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of KALNITSKY, such that a method for forming an image sensor, the method comprising: wherein the first doped region and the second doped region are formed laterally beside one another in the first semiconductor layer, and wherein a first side of the first doped region extends vertically along a side of the second doped region at a p-n junction between the first doped region and the second doped region. This arrangement defines the boundaries or interfaces between the p+ epi layer, 902 and the n epi layer, 108 are p-n junctions, 806 that form a photodiode structure for an image pixel (KALNITSKY, [0018]).
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Though HUANG teaches a method of forming an image sensor, the method comprising: etching the first semiconductor layer (substrate, 102) to form openings, OP1 and OP2, laterally beside the first doped region (substrate, 102 doped with first dopant, [0011]), HUANG as modified by KALNITSKY does not explicitly disclose a method of forming an image sensor, the method comprising: etching the first semiconductor layer to form a trench in the first semiconductor layer laterally beside the first doped region, wherein a sidewall of the first semiconductor layer that delimits the trench extends vertically along a second side of the first doped region, opposite the first side.
HADDAD teaches a method of forming an image sensor (Fig. 17, 170/172, various methods of making photosensitive diodes, pixels and imagers, [0096]), the method comprising: etching ([0066], [0090]) to form a trench (Figs. 7/12, 84 (shallow trench isolation/120 (deep trench isolation), [0090]) in the first semiconductor layer (Figs. 11/12, 72, semiconductor substrate) laterally beside (annotated Figure 12) the first doped region (Figs. 11/12, 74, doped region, [0084]), wherein a sidewall (annotated Figure 12) of the first semiconductor layer (Figs. 11/12, 72, semiconductor substrate) that delimits the trench extends vertically along a second side (annotated Figure 12) of the first doped region (Figs. 11/12, 74, doped region, [0084]), opposite the first side (annotated Figure 12).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of HADDAD, such that a method for forming an image sensor, the method comprising: etching the first semiconductor layer to form a trench in the first semiconductor layer laterally beside the first doped region, wherein a sidewall of the first semiconductor layer that delimits the trench extends vertically along a second side of the first doped region, opposite the first side, so that the trench isolation elements can maintain pixel to pixel uniformity by reducing optical and electrical crosstalk (HADDAD, [0085]).
Though HUANG teaches a method for forming an image sensor, the method comprising: forming a second semiconductor layer having the first doping type along side of the first doped region, HUANG as modified by KALNITSKY and HADDAD does not explicitly disclose a method for forming an image sensor, the method comprising: forming a second semiconductor layer having the first doping type in the trench and along the second side of the first doped region.
OISHI further teaches a method for forming an image sensor (Figs. 4/5, a method of manufacturing the pixel cell, 3, [0072]), the method comprising: forming a second semiconductor layer having the first doping type (Fig. 4, 42, a region doped with a P-type impurity, [0081]) in the trench (Fig. 4, 4, element separation region) and along the second side (annotated Figure 4) of the first doped region (Fig. 4, 31, P-type semiconductor region, [0037]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY and HADDAD to incorporate the teachings of OISHI, such that a method for forming an image sensor, the method comprising: forming a second semiconductor layer having the first doping type in the trench and along the second side of the first doped region, so that to achieve the electrical element separation between respective photoelectric conversion element, 30 is attained by an element separation region, 4 having P-type doped semiconductor region (OISHI, [0105]).
Regarding Claim 17, HUANG as modified by KALNITSKY, HADDAD and OISHI teaches the method of claim 16.
OISHI further teaches the method (Figs. 4/5, a method of manufacturing the pixel cell, 3, [0072]), wherein the second semiconductor layer (Fig. 4, 42, a region doped with a P-type impurity, [0081]) is formed in the trench (Fig. 4, 4, element separation region) by an epitaxy process (Figs. 4/5, the pixel cell, 3 is manufactured, first, a P-type or N-type silicon layer is epitaxially grown, [0073]) and comprises a different semiconductor material (Fig. 4, 42, region, doped with a P-type impurity, [0081]) than the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]).
Regarding Claim 18, HUANG as modified by KALNITSKY, HADDAD and OISHI teaches the method of claim 16.
OISHI further teaches the method (Figs. 4/5, a method of manufacturing the pixel cell, 3, [0072]), wherein the second semiconductor layer (Fig. 4, 42, a region doped with a P-type impurity, [0081]) is formed on the sidewall (annotated Figure 4) of the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]) that delimits the trench (Fig. 4, 4, element separation region).
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Regarding Claim 20, HUANG as modified by KALNITSKY, HADDAD and OISHI the method of claim 16.
HUANG further teaches the method for forming an image sensor (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), further comprising: forming a first contact region (Fig. 1C, Va, the control electrode, [0018]) in the second semiconductor layer (Fig. 1C, first doped wells, A2, [0011]) along a bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1C, first doped wells, A2, [0011]) and extending vertically (annotated Figure 1C) toward a top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1C, first doped wells, A2, [0011]); and forming a second contact region (Fig. 1C, Tx, transfer gate, [0018-0019]) in the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3) along the bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1C, first doped wells, A2, [0011]) and extending vertically (annotated Figure 1C) toward the top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1C, first doped wells, A2, [0011]).
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Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY, in view of HADDAD, further in view of OISHI, and further in view of Yueh-Chuan Lee et al, (hereinafter LEE), US 20170141153 A1.
Regarding Claim 19, HUANG as modified by KALNITSKY, HADDAD and OISHI teaches the method of claim 16.
OISHI further teaches the method (Figs. 4/5, a method of manufacturing the pixel cell, 3, [0072]), further comprising:
forming a trench isolation structure (Fig. 4, 4, element separation region) in the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]) and laterally surrounding the p-n junction (Fig. 4, 30, an element separation region, 4 surrounds side faces of the photoelectric conversion element, 30, which is a photodiode that is formed by P-N junction of the P-type semiconductor region, 31 and the N-type semiconductor region, 32, [0037-0038]), wherein the trench isolation structure (Fig. 4, 4, element separation region) extends vertically (Fig. 4, z-direction) between a bottom side (annotated Figure 4) of the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]) and a top side (annotated Figure 4) of the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]).
HUANG as modified by KALNITSKY, HADDAD and OISHI does not teach the method, wherein the trench isolation structure is laterally spaced from the first doped region, the second doped region, and the second semiconductor layer.
LEE teaches the method (Figs. 6-12, method for manufacturing a CMOS image sensor, [0056]), wherein the trench isolation structure (Figs. 2B/9, 112, STI region, [0061]) is laterally spaced (annotated Figure 2B) from the first doped region (Fig. 2B, 114a, photodetector doped region, [0024-0025]), the second doped region (Fig. 2B, 206a, conductive channel region with a doping gradient, [0026-0027]), and the second semiconductor layer (Fig. 2B, 208, second semiconductor stack, plurality of doped layers, 210-218, [0028-0029]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY, HADDAD, and OISHI to incorporate the teachings of LEE, such that the method, wherein the trench isolation structure is laterally spaced from the first doped region, the second doped region, and the second semiconductor layer, so that the isolation region, 112 is configured to isolate the pixel sensors for the photodetector advantageously operate with good sensitivity and absorption of long-wavelength radiation, such as, for example, infrared radiation (LEE, [0017], [0055]).
Claim(s) 21-24, 28, 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY, and further in view of Kazuya Mori et al, (hereinafter MORI), US 20180247969 A1.
Regarding Claim 21, HUANG teaches in Figures 1A-1E, a method for forming an image sensor (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), the method comprising:
providing a first semiconductor layer (Fig. 1A, 102, substrate), the first semiconductor layer (Fig. 1A, 102, substrate) having a bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) in a first plane (annotated Figure 1A) and a top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) in a second plane (annotated Figure 1A), the first semiconductor layer (Fig. 1A, 102, substrate) having a first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]);
forming a first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and a second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) in the first semiconductor layer (Fig. 1A, 102, substrate), the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) extending vertically along a first sidewall (annotated Figure 1A) of the first semiconductor layer (Fig. 1A, 102, substrate), the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) having the first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]), the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) extending vertically along a first side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) from the bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate) toward the top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate), the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) having a second doping type (Fig. 1A, doping the substrate, 102, with a second dopant having a second conductivity type, [0012]) different than the first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]); and
forming a second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) between the first sidewall (annotated Figure 1A) of the first semiconductor layer (Fig. 1A, 102, substrate) and a second sidewall (annotated Figure 1A) of the first semiconductor layer (Fig. 1A, 102, substrate), the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) extending vertically (annotated Figure 1A) along a second side (annotated Figure 1A) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) from the bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate) toward the top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate), the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) having the first doping type (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), of the first conductivity type, [0011]),
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wherein the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) and the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) meet at a p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]), wherein the p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]) extends vertically along a first side (annotated Figure 1A) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and along a side (annotated Figure 1A) of the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]), and wherein the p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]).
Though HUANG teaches a method of forming an image sensor, the method further comprising: a first semiconductor layer, a first doping region, a second doping region and a second semiconductor layer, and the p-n junction between the first doped region and the second doped region, HUANG does not explicitly disclose a method of forming an image sensor, the method further comprising: wherein the second doped region and the first doped region meet at a p-n junction, wherein the p-n junction extends vertically along a first side of the first doped region and along a side of the second doped region, and wherein the p-n junction is in a third plane that intersects the first plane and the second plane.
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KALNITSKY teaches a method of forming an image sensor (Fig. 15, diagrammatic fragmentary cross-sectional views of a back side illuminated (BSI) image sensor at various stages of fabrication, [0004]), the method comprising: wherein the second doped region (Fig. 15, 902, epi layer) and the first doped region (Fig. 15, 108, epi layer) meet at a p-n junction (Fig. 15, 806, p-n junctions), wherein the p-n junction (Fig. 15, 806, p-n junctions) extends vertically along a first side (annotated Figure 15) of the first doped region (Fig. 15, 108, epi layer) and along a side (annotated Figure 15) of the second doped region (Fig. 15, 902, epi layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of KALNITSKY, such that a method for forming an image sensor, the method comprising: wherein the second doped region and the first doped region meet at a p-n junction, wherein the p-n junction extends vertically along a first side of the first doped region and along a side of the second doped region. This arrangement defines the boundaries or interfaces between the p+ epi layer, 902 and the n epi layer, 108 are p-n junctions, 806 that form a photodiode structure for an image pixel (KALNITSKY, [0018]).
Though HUANG as modified by KALNITSKY teaches the formation of p-n junction with respect to first plane (or first side) and second plane (or second side) of an image sensor, HUANG as modified by KALNITSKY does not explicitly disclose a method of forming an image sensor, the method further comprising: wherein the p-n junction extends vertically along a first side of the first doped region and along a side of the second doped region, and wherein the p-n junction is in a third plane that intersects the first plane and the second plane.
MORI teaches a method of forming an image sensor (a method for manufacturing the solid-state imaging device, [0015]), the method further comprising: wherein the p-n junction (Figs. 7A/7B, p-n junction parts, C1′/C2′/C3′, p-n junction capacitances, between 221, first conductivity type semiconductor layers, and 222, second conductivity type semiconductor layers, [0109]) extends vertically (Fig. 7A, Z direction) along a first side (annotated Figure 7A) of the first doped region (Fig. 7A, 221, first conductivity type semiconductor layers) and along a side (annotated Figure 7A) of the second doped region (Fig. 7A, 222, second conductivity type semiconductor layers), and wherein the p-n junction (Figs. 7A/7B, p-n junction parts, C1′/C2′/C3′, p-n junction capacitances, between 221, first conductivity type semiconductor layers, and 222, second conductivity type semiconductor layers, [0109]) is in a third plane (annotated Figure 7A, pn-junction parts in a direction (X or Y direction) perpendicular to the normal line of the substrate, 210, inside the pixel [0166]) that intersects the first plane and the second plane (Figs. 7A/7B, X, Y, Z intersecting axes).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of MORI, such that a method for forming an image sensor, the method comprising: wherein the p-n junction extends vertically along a first side of the first doped region and along a side of the second doped region, and wherein the p-n junction is in a third plane that intersects the first plane and the second plane. This arrangement of a plurality of pn-junction parts in a direction (horizontal direction) perpendicular to the normal line of the substrate are provided in the pixel to make it possible to read out the accumulated charge by one charge transfer part, it becomes possible to increase the storage capacity while reducing the noise and raising sensitivity (MORI, [0070]).
Regarding Claim 22, HUANG as modified by KALNITSKY and MORI teaches the method of claim 21.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) is laterally between (annotated Figure 1A) the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) and the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]).
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Regarding Claim 23, HUANG as modified by KALNITSKY and MORI teaches the method of claim 22.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first semiconductor layer (Fig. 1A, 102, substrate) comprises a first semiconductor (the substrate, 102 may comprise any type of semiconductor body, e.g., silicon/CMOS bulk, SiGe, SOI, etc., [0011]) and the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) comprises a second semiconductor (the substrate, 102 is doped with first dopant having a first conductivity type as the plurality of first doped wells (A1-A5) and have the same or different concentrations, [0011]), different than the first semiconductor ([0048]).
Regarding Claim 24, HUANG as modified by KALNITSKY and MORI teaches the method of claim 21.
MORI further teaches the method (a method for manufacturing the solid-state imaging device, [0015]), wherein the third plane (annotated Figure 7A, pn-junction parts in a direction (X or Y direction) perpendicular to the normal line of the substrate, 210, inside the pixel [0166]) is approximately perpendicular to the first plane and the second plane (Figs. 7A/7B, X, Y, Z intersecting axes).
Regarding Claim 28, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) and the top side (Fig. 1A, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate) extend along a horizontal direction (annotated Figure 1A, lateral direction), and wherein the p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]) extends along a vertical direction (annotated Figure 4, vertical direction) transverse to the horizontal direction (annotated Figure 4, lateral direction perpendicular to vertical direction).
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HUANG as modified by KALNITSKY does not explicitly disclose the method, wherein the bottom side and the top side of the first semiconductor layer extend along a horizontal direction, and wherein the p-n junction extends along a vertical direction transverse to the horizontal direction.
MORI teaches the method (a method for manufacturing the solid-state imaging device, [0015]), wherein the bottom side (annotated Figure 4) and the top side (annotated Figure 4) of the first semiconductor layer (Fig. 4, 210, substrate, [0085]) extend along a horizontal direction (Fig. 4, X-direction), and wherein the p-n junction (Figs. 4/7A/7B, p-n junction parts, C1′/C2′/C3′, p-n junction capacitances, between 221, first conductivity type semiconductor layers, and 222, second conductivity type semiconductor layers, [0109]) extends along a vertical direction (Fig. 4, Z-direction), transverse to the horizontal direction (Fig. 4, Z- direction is perpendicular to X- direction).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of MORI, such that the method, wherein the bottom side and the top side of the first semiconductor layer extend along a horizontal direction, and wherein the p-n junction extends along a vertical direction transverse to the horizontal direction. This arrangement of a plurality of pn-junction parts in a direction (horizontal direction) perpendicular to the normal line of the substrate are provided in the pixel to make it possible to read out the accumulated charge by one charge transfer part, it becomes possible to increase the storage capacity while reducing the noise and raising sensitivity (MORI, [0070]).
Regarding Claim 36, HUANG as modified by KALNITSKY and MORI teaches the method of claim 21.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein a bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) is in the first plane (annotated Figure 1A).
Claim(s) 25-27, 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY.
Regarding Claim 25, HUANG teaches in Figures 1A-1E, a method for forming an image sensor (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), the method comprising:
providing a first semiconductor layer (Fig. 1A, 102, substrate) having a first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]);
forming a first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and a second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) in the first semiconductor layer (Fig. 1A, 102, substrate), the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) having the first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]), the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) having a second doping type (Fig. 1A, doping the substrate, 102, with a second dopant having a second conductivity type, [0012]) different than the first doping type (Fig. 1A, 102, a substrate is doped with a first dopant having a first conductivity type, [0011], [0039]), the second doped region (Fig. 1A, doping substrate, 102 with a second dopant, [0012]) laterally beside (annotated Figure 1A) the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), extending vertically along a side (annotated Figure 1A) of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), and forming a p-n junction (annotated Figure 1A, in some embodiment, the photosensing region, PD (second doped wells B1, B2, B3) and the substrate (102) are in contact with each other to form a P-N junction photodiode configured to convert radiation into an electric signal, [0013]) with the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]); and
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forming a second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) having the first doping type (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), of the first conductivity type, [0011]) between sidewalls of the first semiconductor layer (Fig. 1A, 102, substrate) and extending vertically along the sidewalls of the first semiconductor layer (Fig. 1A, 102, substrate) from a bottom side (Fig. 1A, 102BK, backside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate) toward a top side (Fig. 1B, 102FT, frontside of the substrate, 102 doped with first dopant) of the first semiconductor layer (Fig. 1A, 102, substrate), wherein the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) is laterally beside (annotated Figure 1A) the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), and wherein a sidewall of the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) extends vertically along a side of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]).
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Though HUANG teaches a method of forming an image sensor, the method further comprising: a first semiconductor layer, a first doping region, a second doping region and a second semiconductor layer, and the p-n junction between the first doped region and the second doped region, HUANG does not explicitly disclose a method of forming an image sensor, the method further comprising: the second doped region laterally beside the first doped region, extending vertically along a side of the first doped region, and forming a p-n junction with the first doped region.
KALNITSKY teaches a method of forming an image sensor (Fig. 15, diagrammatic fragmentary cross-sectional views of a back side illuminated (BSI) image sensor at various stages of fabrication, [0004]), the method comprising: the second doped region (Fig. 15, 902, epi layer) laterally beside (annotated Figure 15) the first doped region (Fig. 15, 108, epi layer), extending vertically along a side (annotated Figure 15) of the first doped region (Fig. 15, 108, epi layer), and forming a p-n junction (Fig. 15, 806, p-n junctions) with the first doped region (Fig. 15, 108, epi layer);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUANG to incorporate the teachings of KALNITSKY, such that a method for forming an image sensor, the method comprising: the second doped region laterally beside the first doped region, extending vertically along a side of the first doped region, and forming a p-n junction with the first doped region. This arrangement defines the boundaries or interfaces between the p+ epi layer, 902 and the n epi layer, 108 are p-n junctions, 806 that form a photodiode structure for an image pixel (KALNITSKY, [0018]).
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Regarding Claim 26, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) is directly between (annotated Figure 1A) the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) and the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]).
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Regarding Claim 27, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) is laterally separated (annotated Figure 1A) from the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]) and the first semiconductor layer (Fig. 1A, 102, substrate).
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Regarding Claim 29, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first semiconductor layer (Fig. 1A, 102, substrate) extends along a top of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]), along a top of the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]), and along an upper surface of the second semiconductor layer (annotated Figure 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]).
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Regarding Claim 30, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first semiconductor layer (Fig. 1A, 102, substrate) extends along a top of the first doped (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) region and is directly between (annotated Figure 1A) the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) and the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]).
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Regarding Claim 31 HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG further teaches in Figures 1A-1E, the method (Figs. 1A-1E, schematic sectional views of various stages in a method of fabricating an image sensor, [0011]), wherein the first semiconductor layer (Fig. 1A, 102, substrate) extends along a bottom of the first doped region (annotated Figure 1A, substrate, 102 is doped with a first dopant, [0011]) and is directly between (annotated Figure 1A) the second doped region (annotated Figure 1A, PD is formed by forming a second doped wells (B1, B2, and B3), [0012]) and the second semiconductor layer (Fig. 1A, first doped wells (A1, A2, A3, A4, and A5), [0011]).
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Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY, and further in view of Yasushi Maruyama et al, (hereinafter MARUYAMA), US 20070210395 A1.
Regarding Claim 33, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG as modified by KALNITSKY does not explicitly disclose the method, wherein a width of the second semiconductor layer along a lateral direction is greater than a width of the first doped region along the lateral direction and greater than a width of the second doped region along the lateral direction.
MARUYAMA teaches the method (Fig. 11, a method for producing the solid-state imaging device, [0091]), wherein a width of the second semiconductor layer (annotated Figure 11, 42, the p well, [0092]) along a lateral direction is greater than (annotated Figure 11) a width of the first doped region (Fig. 11, 46, the p-type region, [0092]) along the lateral direction (annotated Figure 11) and greater than (annotated Figure 11) a width of the second doped region (Fig. 11, 41, n-type charge-accumulation region, [0092]) along the lateral direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of MARUYAMA, such that the method, wherein a width of the second semiconductor layer along a lateral direction is greater than a width of the first doped region along the lateral direction and greater than a width of the second doped region along the lateral direction, so that the charge-accumulation region, 41 is surrounded by a p-well, 42 in the substrate, 30 for the operations of transfer transistor, 22 in the pixel of the solid state imaging device (MARUYAMA, [0078]).
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Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY, further in view of OISHI, and further in view of LEE.
Regarding Claim 34, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG as modified by KALNITSKY does not explicitly disclose the method, further comprising: forming a trench isolation structure laterally surrounding the p-n junction and extending vertically between the bottom side and the top side of the first semiconductor layer.
OISHI teaches the method (Figs. 4/5, a method of manufacturing the pixel cell, 3, [0072]), further comprising:
forming a trench isolation structure (Fig. 4, 4, element separation region) laterally surrounding the p-n junction (Fig. 4, 30, an element separation region, 4 surrounds side faces of the photoelectric conversion element, 30, which is a photodiode that is formed by P-N junction of the P-type semiconductor region, 31 and the N-type semiconductor region, 32, [0037-0038]), and extending vertically (Fig. 4, z-direction) between the bottom side (annotated Figure 4) and the top side (annotated Figure 4) of the first semiconductor layer (Fig. 4, 30, photoelectric conversion element, [0104]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of OISHI, such that the method, further comprising: forming a trench isolation structure laterally surrounding the p-n junction and extending vertically between the bottom side and the top side of the first semiconductor layer, so that to provide electrical separation between respective photoelectric conversion elements, 30 is attained by an element separation region, 4, of a solid state image pickup device (OISHI, [0105]).
HUANG as modified by KALNITSKY and OISHI does not teach the method, wherein the second doped region is laterally spaced from the trench isolation structure and laterally between the trench isolation structure and the first doped region, and wherein the first doped region is laterally between the trench isolation structure and the second semiconductor layer.
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LEE teaches the method (Figs. 6-12, method for manufacturing a CMOS image sensor, [0056]), wherein the second doped region (Fig. 2B, 206a, conductive channel region with a doping gradient, [0026-0027]) is laterally spaced from the trench isolation structure (Figs. 2B/9, 112, STI region, [0061]) and laterally between the trench isolation structure (Figs. 2B/9, 112, STI region, [0061]) and the first doped region, and wherein the first doped region (Fig. 2B, 114a, photodetector doped region, [0024-0025]) is laterally between the trench isolation structure (Figs. 2B/9, 112, STI region, [0061]) and the second semiconductor layer (Fig. 2B, 208, second semiconductor stack, plurality of doped layers, 210-218, [0028-0029]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY and OISHI to incorporate the teachings of LEE, such that the method, wherein the second doped region is laterally spaced from the trench isolation structure and laterally between the trench isolation structure and the first doped region, and wherein the first doped region is laterally between the trench isolation structure and the second semiconductor layer, so that the isolation region, 112 is configured to isolate the pixel sensors for the photodetector advantageously operate with good sensitivity and absorption of long-wavelength radiation, such as, for example, infrared radiation (LEE, [0017], [0055]).
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG, in view of KALNITSKY, and further in view of Norbert Moussy et al, (hereinafter MOUSSY), US 20210159257 A1.
Regarding Claim 35, HUANG as modified by KALNITSKY teaches the method of claim 25.
HUANG as modified by KALNITSKY does not explicitly disclose the method, wherein the first doped region is ring shaped and laterally surrounds the second semiconductor layer in a first closed path, and wherein the second doped region is ring shaped and laterally surrounds the first doped region in a second closed path.
MOUSSY teaches the method (Fig. 4B, 400), wherein the first doped region is ring shaped (Fig. 4B, 421, N-type ring-shaped region) and laterally surrounds the second semiconductor layer (Fig. 4B, 419, N-type doped region) in a first closed path ([0073]), and wherein the second doped region (Fig. 4B, 413, P-type doped layer, [0069]) is ring shaped and laterally surrounds the first doped region in a second closed path ([0073]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUANG as modified by KALNITSKY to incorporate the teachings of MOUSSY, such that the method for forming an image sensor, wherein the first doped region is ring shaped and laterally surrounds the second semiconductor layer in a first closed path, and wherein the second doped region is ring shaped and laterally surrounds the first doped region in a second closed path, so that each of the ring-shape doped regions extends laterally to form island, 109, and stops before reaching the trenches, 107 to define pixel area (MOUSSY, [0073]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210175452 A1 – Figure 1
STATEMENT OF RELEVANCE – The inorganic photoelectric converters, 11B, and 11R each include, a PIN photodiode, and each have a p-n junction in a predetermined region of the semiconductor substrate, 11.
US 20180040651 A1 – Figure 8
STATEMENT OF RELEVANCE – Schematic diagram illustrating a process flow of the fabrication method of the image sensor, forming the first-conductivity-type doped region near the surface of the semiconductor substrate and in the photosensitive area, and the second-conductivity-type doped region on the surface of the recess in the photosensitive area.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812