DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Applicant’s amendments to claims 1 and 5 dated 8 January 2026 are hereby acknowledged. Claims 11 to 20 were previously withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al (US 20200185357 A1, hereinafter “Byun”), in view of Parker et al (US 20230187371 A1, hereinafter “Parker”), and further in view of Pietambaram et al (US 20220278032 A1, hereinafter “Pietambaram”).
Regarding Claim 1 – Byun discloses an electronic package (100 in Byun Fig. 6 and [0050], comprising: a plurality of carrier structures (the plurality of connection structures 111, 112, and 113 of interposer 110 in Byun Fig. 6, and Byun [0050], are considered to be carrier structures), wherein a separation space is formed between adjacent two of the plurality of carrier structures (“Separation Space” in annotated Byun Fig. 7); a plurality of electronic elements (semiconductor chips 122 in Byun Fig. 6 and in Byun [0050] are considered to be electronic elements), wherein each of the electronic elements is disposed on and electrically connected to each of the carrier structures (122 disposed on 110 with connection pads 122P as in Byun Fig. 6 and [0050]); a bridging element (semiconductor chip 121 of Byun Fig. 6 and [0050] is considered to be the bridging element) disposed between at least two of the plurality of carrier structures to electrically bridge the at least two of the plurality of carrier structures (semiconductor chip 121 overlaps connection structures 111 and 113, as shown in Byun Fig. 12 and explained in [0062]), wherein the bridging element is a semiconductor chip (121 defined as a semiconductor chip [0050]); and a packaging layer (130, Byun Fig. 6 and [0057]) covering the plurality of carrier structures, the plurality of electronic elements and the bridging element (“…encapsulant 130 disposed on the interposer 110 and covering at least a portion of each of the first and second semiconductor chips 121 and 122…” Byun [0057]).
Byun fails to disclose the packaging layer is formed in the separation space between adjacent two of the plurality of carrier structures.
However, Parker discloses the packaging layer (118, Parker [0085]) is formed in the separation space between adjacent structures throughout the electronic package (118 may be mold compound and may be used between structures at multiple levels. Parker [0085] and Fig. 1B).
Parker describes a multicomponent electronic device analogous to Byun. Parker teaches a packaging layer such as mold compound to bind multiple types of semiconductor chips into one electronic assembly for the advantage of using a manufacturing process optimized for each chip separately, resulting in improved cost and yield of the combined die solution (Parker [0025]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a packaging layer in the separation space between adjacent structures for the advantage of optimized cost and yield of the final electronic device.
Byun fails to disclose each of the carrier structures includ(e) a silicon-containing board body.
However, Pietambaram discloses the carrier structures may include a silicon-containing board body (interposers can be made of glass, ceramic, or semiconductor materials, Pietambaram [0022]).
Pietambaram discloses a similar multicomponent electronic device to Byun. Pietambaram teaches a silicon-containing body may be used for the carrier structures as a substitute for other material options (Pietambaram [0022]). This application of silicon-containing material in carrier structures is acknowledged by Byun as common (Byun [0003]). Such substitution of known equivalents for the same purpose is a prima facie case of obviousness. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Byun and Pietambaram to use a silicon-containing material in the carrier structures.
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Regarding Claim 2 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses each of the carrier structures has a first side, a second side opposing to the first side, and a plurality of conductive vias connecting the first side and the second side (Conductive vias 111c, 112c, 113c, and 114b as in Byun [0054] and [0055]), and wherein the plurality of conductive vias are electrically connected to the plurality of electronic elements and the bridging element (A plurality of under-bump metals 114 connect to the pads 121P and 122P of semiconductor chips 121 and 122 through connection members 140 in Byun [0056]).
Regarding Claim 3 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses each of the carrier structures is formed with a circuit structure (Considered as redistribution layers 111b, 112b, and 113b in Byun [0050]), and wherein a plurality of the circuit structures of the plurality of carrier structures are electrically connected to the plurality of electronic elements and the bridging element (A plurality of connection structures 111, 112, and 113 may be electrically connected to at least one of the connection pads 121P and 122P as in Byun [0050]).
Regarding Claim 4 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses the bridging element spans the separation space and is electrically connected between the adjacent two of the plurality of carrier structures (121 can be seen to span the separation space(s) in annotated Byun Fig. 12).
Regarding Claim 5 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses the bridging element is disposed between the at least two of the plurality of carrier structures via a plurality of conductive bumps and is electrically connected to the at least two of the plurality of carrier structures (Semiconductor chip 121 electrically connected to at least 111 and two 113 connection structures as shown in Byun Fig. 6).
Regarding Claim 7 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses the packaging layer has a first surface and a second surface opposing to the first surface, and wherein at least part of the plurality of electronic elements are exposed from the first surface (“A back surface of each of the first and second semiconductor chips 121 and 122 and a back surface of the capsule and 130 may optionally be coplanar…” Byun [0057]).
Regarding Claim 8 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses the packaging layer has a first surface (top of 130, as in Byun Fig. 6) and a second surface (bottom of 115, as in Byun Fig. 6) opposing to the first surface, and wherein at least part of the plurality of carrier structures are exposed from the second surface (“A lowermost surface of the (first, second, third) insulation layer (111a in Byun [0064], 112a in [0068], 113a in Byun [0072]) may be coplanar with a lowermost surface of the passivation layer 115”, as can be seen where connection metal 160 protrudes in Byun Fig. 6).
Regarding Claim 9 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses further comprising a substrate structure (considered as printed circuit board 200, as defined in Byun [0086]) for disposing the plurality of carrier structures, wherein the substrate structure is electrically connected to the plurality of carrier structures (“…the semiconductor package 100 may be surface mounted on the printed circuit board 200 through the first electrical connection metal 160.” and “The printed circuit board 200 may be a BGA substrate…” Byun [0086]).
Regarding Claim 10 – Byun modified by Parker, and further modified by Pietambaram, discloses all the limitations of claim 1.
The combination of Byun, Parker, and Pietambaram further discloses the plurality of carrier structures are disposed on the substrate structure via a plurality of conductive elements (First conductive metal 160 connecting connection structures 111, 112, and 113 to printed circuit board 200 as in Byun Fig. 6).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898