Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 12/22/2025 has been entered. Claim 1 is amended. Claims 13, 21 are canceled. Claims 15 – 20, 22 are withdrawn. Claims 1 – 12, 14 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kao ( Pub. No. US 20110049710 A1 ), hereinafter Kao.
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Regarding Independent Claim 1 ( Currently Amended ), Kao teaches an interface ( Kao, FIG. 2, 202, 204, 206; [0038], interconnect structure layout 202; interconnect structures 204; [0039], region 206 ) for a semiconductor chip ( Kao, FIG. 1, 110; [0025], semiconductor chip 110 ), having device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ) and via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ), wherein each of the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ) is located between two of the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) in a first direction ( Kao, FIG. 2, p1; [0043], pitch, p1 ) to form a unit layout channel extending in a second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ) intersecting the first direction ( Kao, FIG. 2, p1; [0043], pitch, p1 ), and the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408 ) extend from a top edge of the interface to a bottom edge of the interface ( FIG. 2, in 206, column area between column of 204, column areas extend from top edge of 206 to a bottom edge of 206 ), wherein the interface ( Kao, FIG. 2, 202, 204, 206; [0038], interconnect structure layout 202; interconnect structures 204; [0039], region 206 ) comprises:
a plurality of bonds ( Kao, FIG. 1, 104; FIG. 2, 204; [0033], via structures 104; [0038], interconnect structures 204 ), arranged in a bond map following the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) and outside the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ), wherein most adjacent two of the bonds ( Kao, FIG. 1, 104; FIG. 2, 204; [0033], via structures 104; [0038], interconnect structures 204 ) in the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ) are arranged in a vertical pitch ( Kao, [0043], pitch, p2, is about 200 microns ), two bonds located at two opposite sides of the device layout channel in the first direction ( Kao, FIG. 2, p1; [0043], pitch, p1 ) are arranged in a transversal pitch ( Kao, [0043], pitch, p1, is about 403 microns ), and the transversal pitch ( Kao, [0043], pitch, p1, is about 403 microns ) is greater than the vertical pitch ( Kao, [0043], pitch, p2, is about 200 microns ),
wherein the semiconductor chip ( Kao, FIG. 1, 110; [0025], semiconductor chip 110 ) comprises a circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ), wherein at least a portion of the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) is disposed in the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ).
Regarding Claim 2 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein one of the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) is arranged between ( Kao, FIG. 2, column of 204 is between two “column area between column of 204” ) two of the unit layout channels in the first direction ( Kao, FIG. 2, p1; [0043], pitch, p1 ).
Regarding Claim 3 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) comprises a plurality of electronic components, a plurality of routing patterns or a combination thereof, and the electronic components comprise at least one semiconductor component ( Kao, FIG. 1, 110; [0025], semiconductor chip 110; [0029], semiconductor materials silicon or germanium ).
Regarding Claim 4 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) is spaced from the bonds ( Kao, [0047], Openings 408 ) by a distance ( Kao, [0041], The design features in the substrate layout can include, for example, dimensions associated with mask registration (SR); [0042], substrate design rules where SR=35 microns; [0048], FIG. 4 further depicts various dimensions used in design rules … SR is a registration value associated with the mask 406 and/or opening 408 ) not smaller than a keep-out distance of the bonds ( Kao, [0047], Openings 408 ).
Regarding Claim 5 ( Original ), Kao teaches the interface for the semiconductor chip of claim 4, on which this claim is dependent, Kao further teaches:
wherein a spacing distance ( Kao, [0043], p2, is about 200 microns ) between the most adjacent two of the bonds in the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ) is greater than twice of the keep-out distance (Kao, [0042], substrate design rules where SR=35 microns).
Regarding Claim 6 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) is absent ( Kao, [0054], In an embodiment where no trace is routed between the interconnect structures 204, pitch e represents a minimum pitch between any pair of interconnect structures 204 on an electronic device (e.g., semiconductor chip 200 of FIG. 2); claim 5, “ … at least a second pair of bumps adjacent to one another having no trace routed on the substrate between the second pair of bumps. ”) between the most adjacent two of the bonds in the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ).
Regarding Claim 7 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein the semiconductor chip ( Kao, FIG. 1, 110; [0025], semiconductor chip 110 ) further comprising a metallization structure ( Kao, FIG. 1, 106; [0028], bump lands 106; [0032], The bump lands 106 are formed using an electrically conductive material such as, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), or gold (Au) or combinations thereof ) disposed on the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) and electrically connecting ( Kao, [0034], Traces (not shown in FIG. 1) or other structures having similar functionality are generally formed on surfaces of the chip substrate 102 to provide an electrical pathway between the bump lands 106 and corresponding via structures of the plurality of via structures 104 ) the bonds ( Kao, FIG. 1, 104; [0033], via structures 104 ) and the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ).
Regarding Claim 8 ( Original ), Kao teaches the interface for the semiconductor chip of claim 7, on which this claim is dependent, Kao further teaches:
wherein the metallization structure ( Kao, FIG. 1, 106; [0028], bump lands 106; [0032], The bump lands 106 are formed using an electrically conductive material such as, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), or gold (Au) or combinations thereof ) comprises a conductive pattern ( Kao, [0040], interconnect structures 204 of the plurality of outer interconnect structures can be electrically routed out on a surface of the corresponding substrate using, for example, corresponding traces (e.g., 404 of FIG. 4). The plurality of inner interconnect structures can be electrically routed using via structures (e.g., 104 of FIG. 1) formed in the substrate; [0047], Although four of the traces 404 are routed between the interconnect lands 402 in the illustrated embodiment, more or fewer traces can be routed between the interconnect lands 402 in other embodiments ) continuously extending from one of the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) to one of the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ).
Regarding Claim 9 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein the unit layout channel is divided into unit blocks arranged in the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ), each of the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) in one of the unit blocks forms a via region ( Kao, FIG. 2, in 206, unit area where contains a 204; [0039], region 206; [0038], interconnect structures 204 ), each of the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ) in one of the unit blocks forms a device region ( Kao, FIG. 2, in 206, unit area where does not contain a 204; [0039], region 206; [0038], interconnect structures 204 ), and each of the unit blocks has a width in the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ) substantially identical to the vertical pitch ( Kao, [0043], pitch, p2, is about 200 microns ) of the bonds.
Regarding Claim 10 ( Original ), Kao teaches the interface for the semiconductor chip of claim 9, on which this claim is dependent, Kao further teaches:
wherein each of the via regions ( Kao, FIG. 2, in 206, unit area where contains a 204; [0039], region 206; [0038], interconnect structures 204 ) accommodates one of the bonds ( Kao, FIG. 2, 204; [0038], interconnect structures 204 ).
Regarding Claim 11 ( Original ), Kao teaches the interface for the semiconductor chip of claim 9, on which this claim is dependent, Kao further teaches:
wherein a quantity of the bonds is less than or equal to a quantity of the via regions and at least one of the via regions ( Kao, FIG. 2, in 206, unit area where contains a 204; [0039], region 206; [0038], interconnect structures 204 ) is absent of the bonds ( Kao, FIG. 3, comparing “top row of 204” vs. “bottom row of 204”, the quantity of 204 is “6” vs. “3”, so the “bottom row of 204” is absent of three units of 204 ).
Regarding Claim 12 ( Original ), Kao teaches the interface for the semiconductor chip of claim 11, on which this claim is dependent, Kao further teaches:
wherein another portion of the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) is disposed in the at least one of the via regions ( Kao, FIG.4 , 404; [0040], traces 404; The substrate 400 further includes traces 404. Although four of the traces 404 are routed between the interconnect lands 402 in the illustrated embodiment, more or fewer traces can be routed between the interconnect lands 402 in other embodiments; FIG. 2, in 206, unit area where contains a 204; [0039], region 206; [0038], interconnect structures 204 ) absent of the bonds ( Kao, FIG. 3, comparing “top row of 204” vs. “bottom row of 204”, the quantity of 204 is “6” vs. “3”, so the “bottom row of 204” is absent of three units of 204 ).
Regarding Claim 14 ( Original ), Kao teaches the interface for the semiconductor chip of claim 1, on which this claim is dependent, Kao further teaches:
wherein in each of the via layout channels ( Kao, FIG. 2, column of 204; [0038], interconnect structures 204 ), the bonds ( Kao, FIG. 2, 204; [0038], interconnect structures 204 ) are arranged along the second direction ( Kao, FIG. 2, p2; [0043], pitch, p2 ) in one single line ( FIG. 2, in 250, 204 are aligned in columns; [0039], region 250; [0065], the interconnect structure layout 700 can be applied to interconnect structures 204 within example region 250 of FIG. 2 depicting a plurality of inner interconnect structures ).
Response to Arguments
Applicant’s argument for claim 1: page 8, line 2, cited “ Therefore, Kao fails to disclose the feature "the device layout channels extend from a top edge of the interface to a bottom edge of the interface ... a plurality of bonds, arranged in a bond map following the via layout channels and outside the device layout channels" of the amended claim 1. ”
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 102 of this office action, cited “ the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408 ) extend from a top edge of the interface to a bottom edge of the interface ( FIG. 2, in 206, column area between column of 204, column areas extend from top edge of 206 to a bottom edge of 206 ) … a plurality of bonds ( Kao, FIG. 1, 104; FIG. 2, 204; [0033], via structures 104; [0038], interconnect structures 204 ), arranged in a bond map following the via layout channels ( Kao, FIG. 1, 104; FIG. 2, column of 204; [0033], via structures 104; [0038], interconnect structures 204 ) and outside the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ) ”. As shown in Kao, FIG. 1, 102 is between 104; FIG. 2, in 206, column area is between column of 204; therefore, a plurality of bonds ( Kao, FIG. 1, 104; FIG. 2, 204 ) are outside the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204 ).
Applicant’s argument for claim 1: page 9, line 5 from bottom, cited “ Therefore, Kao fails to disclose the feature "the semiconductor chip comprises a circuitry and routing structure, wherein at least a portion of the circuitry and routing structure is disposed in the device layout channels" recited in the amended claim 1 of the present application. ”
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 102 of this office action, cited “ wherein the semiconductor chip ( Kao, FIG. 1, 110; [0025], semiconductor chip 110 ) comprises a circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ), wherein at least a portion of the circuitry and routing structure ( FIG. 1, 102 between 104; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; FIG. 4, 404 between 408; [0040], traces 404; [0047], Openings 408 ) is disposed in the device layout channels ( Kao, FIG. 1, 102 between 104; FIG. 2, in 206, column area between column of 204; FIG. 4, 404 between 408; [0025], chip substrate 102; [0033], via structures 104; That is, the plurality of via structures can include via structures that are electrically routed in other configurations or directions within the chip substrate 102 than illustrated; [0039], region 206; [0038], interconnect structures 204; [0040], traces 404; [0047], Openings 408 ). ”. Besides, for s a skilled person in the field, a semiconductor chip can be used as a substrate to bond other semiconductor chips onto it, a process called System-in-Package (SiP) or 3D packaging.
Applicant’s argument for claim 15: page 10, line 6, cited “ In addition, the independent claim 15, currently withdrawn in the previous election, has recited the similar feature "the semiconductor chip comprises a circuitry and routing structure, wherein at least a portion of the circuitry and routing structure is disposed in the device layout channels" as in the amended claim 1 of the present application. Therefore, claim 15 should have also included the similar allowable critical feature as the amended claim 1, as claim 1 is finally allowed, claim 15 is requested to be considered for rejoinder. ”.
Examiner’s response: First, as shown in requirement restriction office action filed 3/31/2025, claim 1 and claim 15 are distinct, because they have different designs. Second, claim 1 remains rejected in this office action, so claim 15 could not be considered for rejoinder.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817