DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (PG Pub. No. US 2017/0263518 A1).
Regarding claim 1, Yu teaches an electronic package (¶ 0036 & fig. 20: 72), comprising:
a first packaging layer (¶ 0024: encapsulation 44) having a first side and a second side opposing to the first side (fig. 20: 44 includes opposing top and bottom sides);
a plurality of conductive pillars (¶ 0014: conductive posts 30) embedded in the first packaging layer and communicating with the first side and the second side of the first packaging layer (fig. 20: 30 embedded in 44 and communicates with top and bottom of 44);
an electronic module (¶ 0016: 100) embedded in the first packaging layer (fig. 20: 100 embedded in 44) and comprising:
an encapsulation layer (¶ 0016: 128) having a first surface and a second surface opposing to the first surface (fig. 20: 128 encapsulates elements 126 and 136A/136B, and includes opposing top and bottom surfaces);
a first electronic element (¶ 0016: circuit 126) embedded in the encapsulation layer (fig. 20: 126 embedded in 128);
a plurality of conductive vias (¶ 0021: 136) embedded in the encapsulation layer and communicating the first surface and the second surface (fig. 20: 136 embedded in 128 and communicating with top and bottom surfaces); and
a first circuit structure (¶ 0019: 140) formed on the first surface of the encapsulation layer to electrically connect to the first electronic element and the plurality of conductive vias (fig. 20: 140 at least indirectly disposed on top surface of 128 and electrically connected to 126 and 136);
a first routing structure (¶ 0026: RDL 48) disposed on the first side of the first packaging layer and electrically connected to the plurality of conductive pillars and the first circuit structure of the electronic module (fig. 20: 48 disposed on top side of 44 and electrically connected to 30 and 140); and
a plurality of second electronic elements (¶ 0032: 66A, 66B) disposed on the first routing structure and electrically connected to the first routing structure (fig. 20: 66A/66B disposed on and electrically connected to 48), wherein at least two of the plurality of second electronic elements are electrically connected to the electronic module via the first routing structure (fig. 20: 66A, 66B electrically connected to 126 via 48), such that the electronic module electrically bridges the at least two of the plurality of second electronic elements (fig. 20: 100 bridges 66A and 66B).
Regarding claim 2, Yu teaches the electronic package of claim 1, further comprising a second circuit structure (¶ 0031: RDL 62) formed on the second surface of the encapsulation layer of the electronic module (fig. 20: 62 at least indirectly disposed on bottom surface of 128), wherein the plurality of conductive vias are electrically connected to the second circuit structure (fig. 20: 30 electrically connected to 62).
Regarding claim 3, Yu teaches the electronic package of claim 1, wherein the first electronic element of the electronic module has an active surface and an inactive surface opposing to the active surface (implicit: 100 includes a surface proximal to circuit 126 and an opposing surface distal from circuit 126), and
wherein the active surface has a plurality of electrode pads (¶ 0019: interconnects 132 disposed on surface of 128 proximal to 126) electrically connected to the first circuit structure (fig. 20: 132 electrically connected to 140).
Regarding claim 4, Yu teaches the electronic package of claim 1, wherein the second electronic elements are electrically connected to the first routing structure via a plurality of conductive bumps (fig. 20: 66A, 66B electrically connected to 48 through solder regions 68).
Regarding claim 5, Yu teaches the electronic package of claim 1, further comprising a second packaging layer (¶ 0034: 69) covering the plurality of second electronic elements (fig. 20: 69 covers 66A/66B).
Regarding claim 6, Yu teaches the electronic package of claim 1, further comprising a second routing structure (¶ 0031: 60/62/64) formed on the second side of the first packaging layer (fig. 20: 60/62/64 formed on bottom side of 44), wherein the plurality of conductive pillars are electrically connected to the second routing structure (fig. 20: 30 electrically connected to 60/62/64).
Regarding claim 7, Yu teaches the electronic package of claim 6, wherein the second routing structure comprises at least one insulating layer (¶ 0031: dielectric layers 60) and at least one routing layer (¶ 0031: RDLs 62 and/or UBM 64) bonded to the insulating layer (62/64 bonded to 60), and wherein an outermost routing layer of the at least one routing layer has an electrical contact pad or an under bump metallurgy layer (¶ 0031; 64 comprises UBMs).
Regarding claim 8, Yu teaches the electronic package of claim 1, further comprising a plurality of conductive elements (¶ 0037: 70) formed on the second side of the first packaging layer and electrically connected to the plurality of conductive pillars and/or the electronic module (fig. 20: 70 at least indirectly disposed on bottom side of 44 and electrically connected to 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Sundaram et al. (PG Pub. No. US 2016/0141257 A1).
Regarding claim 9, Yu teaches the electronic package of claim 1, wherein the first circuit structure of the electronic module comprises a plurality of conductive vias (¶ 0019 & fig. 20: 140 comprises metal pillars).
Yu does not explicitly teach the vias of the first circuit structure comprise staggered conductive blind vias.
Sundaram teaches an electronic package (fig. 1) including blind staggered vias (¶ 0075: 810).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first circuit structure of Yu to include a plurality of staggered conductive blind vias, as a means to help to ease the interconnection conflicts present in high density interconnect packaging (Sundaram, ¶ 0075).
Response to Arguments
Applicant’s arguments, see pages 6-7, filed 10/22/2025, with respect to the claim objection of claim 1 and 35 USC § 112 rejection of claim 7 have been fully considered and are persuasive. Accordingly, these objections/rejections have been withdrawn.
Applicant's arguments regarding the 35 USC § 102 and 35 USC § 103 rejections of claims 1-9 have been fully considered but they are not persuasive.
Regarding the Applicant’s argument stating:
“Thus, in Yu, the package components and the device dies are electrically connected in a one-to-one or one-to-multiple manner, which is significantly different from claim 1 of the present application. Therefore, Yu fails to disclose the feature "at least two of the plurality of second electronic elements are electrically connected to the electronic module via the first routing structure, such that the electronic module electrically bridges the at least two of the plurality of second electronic elements," as recited in claim 1 of this application”
The Examiner notes that the package component of Yu is represented by element 100, which encompasses 100A, 100B, 100C and 100D. Yu further discloses that at least two second electronic elements (at least two of 66A, 66B, 66C) are electrically connected to 100 via a routing structure (RDL 48). Furthermore, Yu teaches embodiments wherein second electronic elements 66 include die stacks and/or integrated circuits. Therefore, the Applicant’s arguments are not persuasive, and the rejections of record are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang et al. (PG. Pub. No. US 2021/0183794 A1) teaches an electronic package (100B) including a plurality of second electronic elements (226) disposed on and electrically connected to a first routing structure (144), wherein at least two of the plurality of second electronic elements are electrically connected to an electronic module via the first routing structure (fig. 6E: plurality of 226 electrically connected to module 130 through 144).
Lin et al. (PG Pub. No. US 2022/0223534 A1) teaches an electronic package (PKG2) including a plurality of second electronic elements (101) disposed on and electrically connected to a first routing structure (203a/203b), wherein at least two of the plurality of second electronic elements are electrically connected to an electronic module via the first routing structure (fig. 3H: plurality of 110 electrically connected to die 10c through 203a/203b).
Lai et al. (PG Pub. No. US 2016/0358889 A1) teaches an electronic package (100) including a plurality of second electronic elements (110) disposed on and electrically connected to a first routing structure (140), wherein at least two of the plurality of second electronic elements are electrically connected to an electronic module via the first routing structure (¶ 0039 & fig. 7: module 150 controls voltage to die 110).
Yu et al. (PG Pub. No. US 2019/0341376 A1) teaches an electronic package (200) including a plurality of second electronic elements (304) disposed on and electrically connected to a first routing structure (302/310), wherein at least two of the plurality of second electronic elements are electrically connected to an electronic module via the first routing structure (¶ 0023: 304 electrically connected to chip 102 through 302/310).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818