DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/22/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub. No. US 2017/0263518 A1) in view of Choi et al. (PG Pub. No. US 2022/0254756 A1).
Regarding claim 1, Yu teaches an electronic package (¶ 0036 & fig. 20: 72), comprising:
a first packaging layer (¶ 0024: encapsulation 44) having a first side and a second side opposing to the first side (fig. 20: 44 includes opposing top and bottom sides);
a plurality of conductive pillars (¶ 0014: conductive posts 30) embedded in the first packaging layer and communicating with the first side and the second side of the first packaging layer (fig. 20: 30 embedded in 44 and communicates with top and bottom of 44);
an electronic module (¶ 0016: 100) embedded in the first packaging layer (fig. 20: 100 embedded in 44) and comprising:
an encapsulation layer (¶ 0016: 128) having a first surface and a second surface opposing to the first surface (fig. 20: 128 encapsulates elements 126 and 136A/136B, and includes opposing top and bottom surfaces);
a first electronic element (¶ 0016: circuit 126) embedded in the encapsulation layer (fig. 20: 126 embedded in 128);
a plurality of conductive vias (¶ 0021: 136) embedded in the encapsulation layer and communicating the first surface and the second surface (fig. 20: 136 embedded in 128 and communicating with top and bottom surfaces); and
a first circuit structure (¶ 0019: 140) formed on the first surface of the encapsulation layer to electrically connect to the first electronic element and the plurality of conductive vias (fig. 20: 140 at least indirectly disposed on top surface of 128 and electrically connected to 126 and 136);
a first routing structure (¶ 0026: RDL 48) disposed on the first side of the first packaging layer and electrically connected to the plurality of conductive pillars and the first circuit structure of the electronic module (fig. 20: 48 disposed on top side of 44 and electrically connected to 30 and 140); and
a plurality of second electronic elements (¶ 0032: 66A, 66B) disposed on the first routing structure and electrically connected to the first routing structure (fig. 20: 66A/66B disposed on and electrically connected to 48), wherein at least two of the plurality of second electronic elements are electrically connected to the electronic module via the first routing structure (fig. 20: 66A, 66B electrically connected to 126 via 48), such that the electronic module electrically bridges the at least two of the plurality of second electronic elements (fig. 20: 100 bridges 66A and 66B).
Yu further teaches the first electronic element comprises a voltage regulator circuit (¶ 0017), but fails to explicitly teach the first electronic element is a bridge chip.
Choi teaches an electronic package (fig. 2) including a bridge die (¶¶ 0034-0036: 230-1, 230-2, 230-3), the bridge die including a voltage regulator (¶ 0046).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first electronic element of Yu as a bridge chip, as a means to increase the degree of integration of semiconductor devices (Choi, ¶ 0004).
Regarding claim 2, Yu in view of Choi teaches the electronic package of claim 1, further comprising a second circuit structure (Yu, ¶ 0031: RDL 62) formed on the second surface of the encapsulation layer of the electronic module (Yu, fig. 20: 62 at least indirectly disposed on bottom surface of 128), wherein the plurality of conductive vias are electrically connected to the second circuit structure (Yu, fig. 20: 30 electrically connected to 62).
Regarding claim 3, Yu in view of Choi teaches the electronic package of claim 1, wherein the first electronic element of the electronic module has an active surface and an inactive surface opposing to the active surface (implicit: 100 of Yu includes a surface proximal to circuit 126 and an opposing surface distal from circuit 126), and
wherein the active surface has a plurality of electrode pads (Yu, ¶ 0019: interconnects 132 disposed on surface of 128 proximal to 126) electrically connected to the first circuit structure (Yu, fig. 20: 132 electrically connected to 140).
Regarding claim 4, Yu in view of Choi teaches the electronic package of claim 1, wherein the second electronic elements are electrically connected to the first routing structure via a plurality of conductive bumps (Yu, fig. 20: 66A, 66B electrically connected to 48 through solder regions 68).
Regarding claim 5, Yu in view of Choi teaches the electronic package of claim 1, further comprising a second packaging layer (Yu, ¶ 0034: 69) covering the plurality of second electronic elements (Yu, fig. 20: 69 covers 66A/66B).
Regarding claim 6, Yu in view of Choi teaches the electronic package of claim 1, further comprising a second routing structure (Yu, ¶ 0031: 60/62/64) formed on the second side of the first packaging layer (Yu, fig. 20: 60/62/64 formed on bottom side of 44), wherein the plurality of conductive pillars are electrically connected to the second routing structure (Yu, fig. 20: 30 electrically connected to 60/62/64).
Regarding claim 7, Yu in view of Choi teaches the electronic package of claim 6, wherein the second routing structure comprises at least one insulating layer (Yu, ¶ 0031: dielectric layers 60) and at least one routing layer (Yu, ¶ 0031: RDLs 62 and/or UBM 64) bonded to the insulating layer (Yu, 62/64 bonded to 60), and wherein an outermost routing layer of the at least one routing layer has an electrical contact pad or an under bump metallurgy layer (Yu, ¶ 0031: 64 comprises UBMs).
Regarding claim 8, Yu in view of Choi teaches the electronic package of claim 1, further comprising a plurality of conductive elements (Yu, ¶ 0037: 70) formed on the second side of the first packaging layer and electrically connected to the plurality of conductive pillars and/or the electronic module (Yu, fig. 20: 70 at least indirectly disposed on bottom side of 44 and electrically connected to 30).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Choi as applied to claim 1 above, and further in view of Sundaram et al. (PG Pub. No. US 2016/0141257 A1).
Regarding claim 9, Yu in view of Choi teaches the electronic package of claim 1, wherein the first circuit structure of the electronic module comprises a plurality of conductive vias (Yu, ¶ 0019 & fig. 20: 140 comprises metal pillars).
Yu in view of Choi does not explicitly teach the vias of the first circuit structure comprise staggered conductive blind vias.
Sundaram teaches an electronic package (fig. 1) including blind staggered vias (¶ 0075: 810).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first circuit structure of Yu in view of Choi to include a plurality of staggered conductive blind vias, as a means to help to ease the interconnection conflicts present in high density interconnect packaging (Sundaram, ¶ 0075).
Response to Arguments
Applicant’s arguments, see pages 6-9, filed 4/22/2026, with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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