DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
This action is responsive to communication on 9 February 2026, in which claims 1-2, 8-9, 10-14, 21-22, and 26 were amended. Claims 15-20 were previously cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 1 – Amended claim 1 incorporates the term “unidirectional path”, although the term is not defined in the specification. Given the ambiguity of the term, “unidirectional path” will be read as “path” for the purpose of examination.
Regarding Claim 6 – In claim 6, the amended limitation “starting imaging used for alignment of the die with the wafer after the die reaches the predetermined position” begins with three verbs followed by four prepositional phrases, making the intended meaning of the limitation ambiguous. This limitation will be interpreted as “starting alignment of the die with the wafer after the die reaches the predetermined position” for the purpose of examination.
Claims 2-7 are rejected under 35 U.S.C. 112(b) for their dependency on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Warner et al (US 9,984,943 B2, hereinafter “Warner”), in view of Drye et al (WO 8505733 A, hereinafter “Drye”), and further in view of Seyama et al (US 20190304852 A1, hereinafter “Seyama”), and further in view of Hashimoto et al (JP 2002026074 A, hereinafter “Hashimoto”).
Regarding Claim 1 – Warner discloses a method of manufacturing a semiconductor structure, comprising: moving a die towards an upper surface of a wafer along a path that extends between a first position and the upper surface of the wafer by using a pick-and-place tool (alignment device 600 as described in Warner column 17, line 60-66 and shown in Warner Fig. 6 positioning the structures to be bonded into contact as in Warner 24, line 44 through column 25, line 17); using the IR detection device to determine a positional relationship between a first set of collective alignment marks disposed on the die and a second set of alignment marks disposed on the wafer while the die is on the path, wherein the first set of collective alignment marks include one or more alignment marks disposed on the die (Multiple alignment marks on each structure used for alignment, Warner column 21, line 57 to column 24, line 11); bonding the die to the wafer (as described in Warner column 24, lines 42-49, and column 25, lines 11-17).
Warner fails to disclose one or more seal rings disposed on the die for alignment.
However, Drye discloses using a seal ring for alignment (52, Drye page 14, lines 14-30, and Fig. 6D).
Seal rings are well-known in the semiconductor industry, and have been commonly used for alignment. Drye discloses an assembly with a seal ring in an analogous semiconductor assembly to Warner. Drye teaches using a seal ring to facilitate alignment (Drye page 14, lines 14-30). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Warner and Drye to use a seal ring to facilitate alignment.
Warner fails to disclose the pick-and-place tool comprising an infrared (IR) detection device attached to the pick-and-place tool in a fixed relationship.
However, Seyama discloses the pick-and-place tool comprising an infrared (IR) detection device (camera 70 in Seyama Fig. 9, further clarified as an infrared camera in [0075]) attached to the pick-and-place tool in a fixed relationship (provided on bond head 30 (30A in [0061]) as described in [0060]);
Seyama is analogous to Warner because they are both in the area of semiconductor structure bonding. Seyama teaches the use of a camera in a fixed position relative to the bonding head for the benefit of maintaining a known offset for alignment calculation (Seyama [0061]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use an infrared detection device in a fixed relationship with the bonding head to enable the predictable result of accurate die placement and bonding using a pick and place tool with an infrared detection device.
The combination of Warner and Seyama fails to disclose aligning the die with the wafer based upon the positional relationship while the die is on the path.
However, Hashimoto discloses aligning the die with the wafer based upon the positional relationship while the die is on the path by using the detection device (“...the first bonding head bonds the chip to a first surface of the substrate while aligning the chip and the substrate based on the position of the chip detected by the first detection device and the position of the substrate detected by the third detection device...”, Hashimoto [0011]).
Hashimoto is in the same field of semiconductor structure bonding as Warner. Hashimoto teaches high precision bonding can be achieved by aligning the substrate in the chip based on position of the chip received by the first bonding head detected by the first detection device and the position the substrate by the third detection device (Hashimoto [0014]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to bond a chip while using data from the two detection devices to align for the benefit of high precision.
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Regarding Claim 2 – Warner, modified by Drye, Seyama, and Hashimoto, discloses all the limitations of the method of Claim 1.
The combination of Warner, Drye, Seyama, and Hashimoto further discloses the die comprises a first alignment mark (die considered to be semiconductor structure 100 in Warner column 8, lines 63-66), the wafer comprises a second alignment mark (wafer considered to be semiconductor structure 1100 in Warner column 10, lines 42-49), and aligning the die with the wafer comprises: obtaining the positional relationship between the first alignment mark and the second alignment mark by using the IR detection device (Warner column 2, lines 28-32, and column 24, lines 3-8); and generating a position correction instruction, using a processing unit, based on the positional relationship (as explained in Warner column 2, lines 52-64).
Regarding Claim 3 – Warner, modified by Drye, Seyama, and Hashimoto, discloses all the limitations of Claim 2.
The combination of Warner, Drye, Seyama, and Hashimoto further discloses aligning the die (100 in Warner Fig. 1 and described in Warner column 7, lines 56-59) with the wafer (1100 in Warner Fig. 1A and described in Warner column 9, lines 20-25) further comprises: adjusting a position of the die (100 in Warner Fig. 1 and described in Warner column 7, lines 56-59, held by mounting portion 530 as in Warner column 14, lines 65-67) to an aligned position based on the position correction instruction (as described in Warner column 18, lines 25-34) received from the processing unit (512 in Warner Fig. 6). (position adjustment described in Warner column 23, lines 37-41)
Regarding Claim 4 – Warner, modified by Drye, Seyama, and Hashimoto, discloses all the limitations of Claim 3.
The combination of Warner, Drye, Seyama, and Hashimoto further discloses bonding the die to the wafer comprises: bringing the die from the aligned position into contact with the wafer by the pick- and-place tool (alignment device 600 as described in Warner column 17, line 60-66 and shown in Warner Fig. 6 positioning the structures to be bonded into contact as in Warner column 24, line 44 through column 25, line 17).
Regarding Claim 5 – Warner, modified by Drye, Seyama, and Hashimoto, discloses all the limitations of Claim 2.
The combination of Warner, Drye, Seyama, and Hashimoto further discloses the first alignment mark (Warner column 8, lines 63-66) and the second alignment mark (Warner column 10, lines 42-46) comprise metal (Warner column 9, lines 8-11) configured to reflect IR light (Warner column 15, lines 46-56).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Warner et al (US 9,984,943 B2, hereinafter “Warner”), in view of Seyama et al (US 20190304852 A1, hereinafter “Seyama”), and further in view of Hashimoto et al (JP 2002026074 A, hereinafter “Hashimoto”), and further in view of Lu et al (JP 2011014866 A, hereinafter “Lu”).
Regarding Claim 6 – Warner modified by Seyama, and further modified by Hashimoto discloses all the limitations of Claim 1.
The combination of Warner, Seyama, and Hashimoto further discloses moving the die towards the wafer at a first speed (rapidly, as described in Warner column 3, lines 20-26) until the die is at a predetermined position that is separated from the wafer by a predetermined distance (predetermined position in Seyama [0062] and first predetermined distance, as described in Warner column 23, lines 7-20); starting alignment of the die with the wafer after the die reaches the predetermined position (Warner col. 3, lines 20-32).
The combination of Warner, Seyama, and Hashimoto fails to disclose moving the die from the predetermined position towards the wafer at a second speed less than the first speed.
However, Lu discloses moving the die from the predetermined position towards the wafer at a second speed less than the first speed (Lu [0029]).
Like Warner, Seyama, and Hashimoto, Lu describes a die bonding process. Lu teaches a second bonding head speed lower than the first for the benefit of higher precision (Lu [0029]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using a second, slower speed to move a bonding head from a predetermined position to the bonding site for the benefit of higher precision.
Regarding Claim 7 – Warner modified by Seyama, and further modified by Hashimoto and Lu, discloses all the limitations of Claim 6.
The combination of Warner, Seyama, Hashimoto, and Lu further discloses the die continues movement towards the wafer at the second speed simultaneous to aligning the die with the wafer using the IR detection device (Hashimoto [0011], IR detection device Warner col. 2, lines 44-46).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Warner et al (US 9,984,943 B2, hereinafter “Warner”), in view of Hashimoto et al (JP 2002026074 A, hereinafter “Hashimoto”).
Regarding Claim 8 – Warner discloses a method of manufacturing a semiconductor structure, comprising: providing a pick-and-place tool (alignment device 600 in Warner Fig. 6 and column 16, lines 52-62) comprising one or more IR detection devices (520 in Warner column 16, lines 52-62); obtaining a positional relationship between a first alignment mark (Warner column 8, lines 62-66) on a first device structure (100 in Warner Fig. 1) and a second alignment mark (Warner column 10, lines 42-49) on a second device structure (1100 in Warner Fig. 1A) by using the first IR detection device of the pick-and-place tool (Warner column 22, lines 20-52); aligning the first device structure with the second device structure by the pick- and-place tool according to the positional relationship (Warner column 23, line 37 through column 24, line 41); and moving the first device structure towards the second device structure at a first non-zero speed (Warner column 22, line 53 through column 23, line 20).
Warner fails to disclose obtaining the positional relationship and aligning the first device structure with the second device structure are performed simultaneous to moving the first device structure towards the second device structure.
However, Hashimoto discloses obtaining the positional relationship and aligning the first device structure with the second device structure are performed simultaneous to moving the first device structure towards the second device structure. (“...the first bonding head bonds the chip to a first surface of the substrate while aligning the chip and the substrate based on the position of the chip detected by the first detection device and the position of the substrate detected by the third detection device...”, Hashimoto [0011]).
Hashimoto is in the same field of semiconductor structure bonding as Warner. Hashimoto teaches high precision bonding can be achieved by aligning the substrate in the chip based on position of the chip received by the first bonding head detected by the first detection device and the position the substrate by the third detection device (Hashimoto [0014]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to bond a chip while using data from the two detection devices to align for the benefit of high precision.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Warner et al (US 9,984,943 B2, hereinafter “Warner”), in view of Hashimoto et al (JP 2002026074 A, hereinafter “Hashimoto”), and further in view of Seyama et al (US 20190304852 A1, hereinafter “Seyama”).
Regarding Claim 9 – Warner modified by Hashimoto discloses all the limitations of Claim 8.
The combination of Warner and Hashimoto further discloses the pick-and-place tool comprises a surface configured to receive the first device structure (530 Warner col. 14, line 65 to col. 15, line 3).
The combination of Warner and Hashimoto fails to disclose the one or more IR detection devices are located along the surface of the pick-and-place tool that is configured to receive the first device structure.
However, Seyama discloses the one or more IR detection devices are located along the surface of the pick-and-place tool that is configured to receive the first device structure (Seyama [0061] and Fig. 9).
Seyama is analogous to Warner because they are both in the area of semiconductor structure bonding. Seyama teaches the use of a camera in a fixed position relative to the bonding head for the benefit of maintaining a known offset for alignment calculation (Seyama [0061]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using an infrared detection device in a fixed relationship with the bonding head to enable the predictable result of accurate die placement and bonding.
Furthermore, while Seyama discloses only one camera in a fixed position relative to the bonding head, adding additional cameras is merely a matter of duplication of parts and has no patentable significance. See MPEP 2144.04(VI)(B).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Warner et al (US 9,984,943 B2, hereinafter “Warner”), in view of Hashimoto et al (JP 2002026074 A, hereinafter “Hashimoto”), and further in view of Harn et al (US 20110115057 A, hereinafter “Harn”).
Regarding Claim 10 – Warner modified by Hashimoto discloses all the limitations of Claim 8.
The combination of Warner and Hashimoto further discloses the positional relationship is obtained between alignment marks positioned on the first device structure and a second set of alignment marks on the second device structure using the one or more IR detection devices of the pick-and-place tool (Warner column 22, lines 20-28 and column 23, lines 21-41).
The combination of Warner and Hashimoto fails to disclose four distinct alignment marks positioned on four corners of the first device structure.
However, Harn discloses four distinct alignment marks positioned on four corners of the first device structure (304 and 306, Harn [0026] and Fig. 5).
Harn discloses analogous alignment marks to Warner. Harn teaches placing alignment marks in all four corners of a die for the benefits of saving area for the integrated circuit region, and easy integration into the manufacturing process (Harn [0026]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Warner and Harn to place alignment marks in the four corners of a die for the benefits of saving area for the integrated circuit region, and easy integration into the manufacturing process.
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Regarding Claim 11 – Warner modified by Hashimoto and Harn discloses all the limitations of Claim 10.
The combination of Warner, Hashimoto, and Harn further discloses the four distinct alignment marks on the first device structure and the second set of alignment marks on the second structure comprise two-dimensional (2D) patterns (Warner column 9, lines 8-11, two-dimensional in design, as they are formed in a device layer), and the positional relationship comprises a misalignment of the 2D patterns of the four distinct alignment marks and the second set of alignment marks (alignment error in Warner column 18, lines 15-18).
Regarding Claim 12 – Warner modified by Hashimoto and Harn discloses all the limitations of Claim 10.
The combination of Warner, Hashimoto, and Harn further discloses the one or more IR detection devices comprise: a first IR detection device configured to detect a position of one of the four distinct alignment marks (Warner column 17, lines 49-57); and a second IR detection device configured to detect a position of one of the second set of alignment marks (Warner column 17, lines 49-57 and 60-66).
Allowable Subject Matter
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 would be allowable at least because of the limitation “...wherein the first IR detection device and the second IR detection device are arranged within a first corner of the pick-and-place tool” as stated in the claim. This step of the method is not anticipated nor rendered obvious by the prior art known to the examiner. The closest prior art is from Warner (US 9,984,943 B2), Seyama (US 20190304852 A1), and Hashimoto (JP 2002026074 A). Warner teaches “(f)irst and second imaging devices 520, 620 and first and second mounting portions 530, 540 are each coupled to the mounting structure 610” ([0109]). Seyama teaches “The mounting apparatus 1A of the present embodiment includes a bonding head 30A having the bonding tool 31 and the camera 70” ([0061]), however does not teach the first IR detection device or the second IR detection device are arranged within a first corner of the pick-and-place tool. Hashimoto teaches “The flip chip bonder 10 also has a camera 21 constituting a third detection device for pattern-recognizing the bonding portion of the substrate 1 supported by the substrate support device 11, a camera 22 constituting a first detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 14A of the bonding head 14, and a camera 23 constituting a second detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 15A of the bonding stage 15.” However, none of these teaches the first IR detection device and the second IR detection device are arranged within a first corner of the pick-and-place tool.
Claim 14 would be allowable at least because of the limitations “...wherein the first IR detection device and the second IR detection device are arranged along a same side of a vertical line bisecting the pick-and-place tool; and wherein the first IR detection device and the second IR detection device have different penetration depths” as stated in the claim. These steps of the method are not anticipated nor rendered obvious by the prior art known to the examiner. The closest prior art is from Warner (US 9,984,943 B2), Seyama (US 20190304852 A1), and Hashimoto (JP 2002026074 A). Warner teaches “(f)irst and second imaging devices 520, 620 and first and second mounting portions 530, 540 are each coupled to the mounting structure 610” ([0109]). Seyama teaches “The mounting apparatus 1A of the present embodiment includes a bonding head 30A having the bonding tool 31 and the camera 70” ([0061]), however does not teach the first IR detection device or the second IR detection device are arranged within a first corner of the pick-and-place tool. Hashimoto teaches “The flip chip bonder 10 also has a camera 21 constituting a third detection device for pattern-recognizing the bonding portion of the substrate 1 supported by the substrate support device 11, a camera 22 constituting a first detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 14A of the bonding head 14, and a camera 23 constituting a second detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 15A of the bonding stage 15.” However, none of these teaches the first IR detection device and the second IR detection device are arranged along a same side of a vertical line bisecting the pick-and-place tool, or the first IR detection device and the second IR detection device have different penetration depths.
Claims 21-26 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21 is allowable at least because of the limitation “...two of the two or more IR detection devices being embedded within a same side of the surface relative to a center of the surface” as stated in the claim. This step of the method is not anticipated nor rendered obvious by the prior art known to the examiner. The closest prior art is from Warner (US 9,984,943 B2), Seyama (US 20190304852 A1), and Hashimoto (JP 2002026074 A). Warner teaches “(f)irst and second imaging devices 520, 620 and first and second mounting portions 530, 540 are each coupled to the mounting structure 610” ([0109]). Seyama teaches “The mounting apparatus 1A of the present embodiment includes a bonding head 30A having the bonding tool 31 and the camera 70” ([0061]), however does not teach the first IR detection device or the second IR detection device are arranged within a first corner of the pick-and-place tool. Hashimoto teaches “The flip chip bonder 10 also has a camera 21 constituting a third detection device for pattern-recognizing the bonding portion of the substrate 1 supported by the substrate support device 11, a camera 22 constituting a first detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 14A of the bonding head 14, and a camera 23 constituting a second detection device for pattern-recognizing the position of the chip 2 received by the suction nozzle 15A of the bonding stage 15.” However, none of these teaches two of the two or more IR detection devices being embedded within a same side of the surface relative to a center of the surface.
Claims 22-26 are allowable for their dependency on claim 21.
Response to Arguments
Applicant's arguments filed 9 February 2026 have been fully considered but they are not persuasive.
Regarding the rejection of claims 1-7 under 35 USC 112(b) - The term “unidirectional” is not defined in the specification, as stated above. Explanation of the claimed method must be consistent with the specification.
Regarding the rejection of claims 1-7 under 35 USC 103 - Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Regarding the rejection of claims 8-14 under 35 USC 103 - The applicant argues that “bonding is not the same (as) moving towards”. However, the process of die bonding inherently involves movement to the final position where the die will remain bonded. The examiner respectfully submits that defining bonding as a step after all movement has occurred (i.e. “fastening the chip and substrate together in a fixed relationship”) cannot apply in the context of alignment, because no alignment can occur after all die movement has ceased. Hashimoto discloses obtaining the positional relationship and aligning the first device structure with the second device structure are performed simultaneous to moving the first device structure towards the second device structure. (“...the first bonding head bonds the chip to a first surface of the substrate while aligning the chip and the substrate based on the position of the chip detected by the first detection device and the position of the substrate detected by the third detection device...”, Hashimoto [0011]).
Regarding the rejection of claims 10-12 under 35 USC 103 - Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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