DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200135475 (Cheng et al) in view of US 10825736 (Zhang et al).
Referring to claim 1, Cheng discloses a semiconductor device (Fig. 15), comprising: a substrate (206); a fin structure (208) disposed on the substrate; . . . and first and second gate structures. . . , respectively, comprising: first and second interfacial oxide (IO) layers (502), respectively (Fig. 15 and [0028] note that the first interfacial layer is formed on PMOS device 902 and the second interfacial layer is formed on the NMOS device 904); first and second high-K (HK) gate dielectric layers (504) disposed on the first and second IO layers ([0029]-[0030] and Fig. 15 note that the first high-k dielectric layer is formed on PMOS device 902 and the second high-k dielectric layer is formed on the NMOS device 904 and that the materials used for the dielectric layer are disclosed as high-k materials), respectively; . . . first (602) and second dopant (604) control layers disposed on the first and second HK gate dielectric layers ([0034] note that the examiner is interpreting that the first dopant control layer is formed of TiN and the second dopant control layer is formed of TiSiN), respectively, wherein the second dopant control layer has a semiconductor-to-metal atomic concentration ratio greater than a semiconductor-to-metal atomic concentration ratio of the first dopant control layer ([0034], note that the Ti to Si atomic concentration in the first dopant control layer TiN is 0% which is lower than the Ti to Si atomic concentration in the second dopant control layer TiSiN which is greater than 0%); and first and second gate metal fill layers (1208) disposed on the first and second HK gate dielectric layers, respectively ([0058] the first gate fill metal layer is formed on PMOS device 902 and the second gate fill metal layer is formed on the NMOS device 904).
Cheng does not disclose first and second nanostructured layers disposed on the fin structure; or the first and second gate structures surrounding the first and second nanostructured layers or wherein the first and second HK gate dielectric layers comprise first and second dopants . . . wherein a first concentration of the first dopants at an interface between the first HK gate dielectric layer and the first dopant control layer is different from a second concentration of the first dopants at an interface between the first HK gate dielectric layer and the first IO layer. However, Zhang discloses a semiconductor device structure that utilizes high-k dielectrics (Abstract and Figs. 7-10) and these configurations include fin structures as well as nanostructured layers in which first and second gate structures are surrounding the first and second nanostructured layers. Zhang disclose that the nanostructured semiconductor benefit from tight device-device spacing due to scaling to smaller node technology sizes (col. 1 lines 10-20). Zhang also discloses forming a first and second IO layer (42) and high-k dielectric layers (44/62/64) (col. 6 lines 6-36) and that the high-k (HK) layers contain dopants (62/64) (col. 6 lines 21-29, it is noted that LaSiO is disclosed as an HK material and the examiner is relying on that material (with La being the first dopant and Si being the second dopant) as being the material for examination purposes). Zhang discloses additionally doping only the first HK layer with Si in order to form an amorphous HK layer which allows for the dipole material can selectively diffuse through the amorphous dielectric layer, but no diffusion occurs in the crystalline dielectric layer. This enables multi-Vt without patterning between nanosheet channels. The dipole forming element is present at the interfacial layer of the low Vt nFET and the high Vt pFET. Thus, a high Vt nFET and a low Vt pFET can include a crystallized HK layer with smaller intersheet spacing (T.sub.sus), whereas a low Vt nFET and a high Vt pFET can include an amorphous HK layer, with a detectable dopant in the HK layer, and with larger intersheet spacing (T.sub.sus). The amorphous HK layer has a dopant, such as Si, due to its higher crystallization temperature than a pure HK material (col. 3 lines 27-42). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the device of Cheng to include nanostructured layers where the first and second gate structures surround the first and second nanostructured layers and the first and second HK gate dielectric layers comprise first and second dopants wherein a first concentration of the first dopants at an interface between the first HK gate dielectric layer and the first dopant control layer is different from a second concentration of the first dopants at an interface between the first HK gate dielectric layer and the first IO layer in order to form smaller scale devices with multi- gate threshold voltages without patterning between the nanosheet channels as disclosed by Zhang.
Regarding claim 2, Cheng in view of Zhang discloses wherein the second dopant control layer has a silicon (Si) to-metal atomic concentration ratio greater than a Si-to-metal atomic concentration ratio of the first dopant control layer (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0%).
Pertaining to claim 3, Cheng in view of Zhang disclose wherein the second dopant control layer has a silicon (Si)-to-titanium (Ti) atomic concentration ratio greater than an Si-to-Ti atomic concentration ratio of the first dopant control layer (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0% which is different from the first dopant control layer).
Pertaining to claim 4, Cheng in view of Zhang disclose wherein an interface between the second HK gate dielectric layer and the second IO layer has a concentration of the second dopants that is less than the second concentration of the first dopants at an interface between the first HK gate dielectric and the first IO layer. (Zhang col. 3 lines 27-42 and col. 6 lines 21-29)
As to claim 5, Cheng in view of Zhang disclose wherein a first interface between the first HK gate dielectric layer and the first dopant control layer has a first silicon (Si) concentration, and wherein a second interface between the second HK gate dielectric layer and the second dopant layer has a second Si concentration that is greater than the first Si concentration (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0% which is greater therefore the concentration of Si at the interface will be greater for the second than the first because there is no Si present in the first dopant control layer).
Concerning claim 6, Cheng in view of Zhang discloses wherein a an interface between the second HK gate dielectric layer and the second dopant layer has a dopant concentration of the firs dopants at an interface between the first HK gate dielectric layer and the first dopant control layer (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0% which is greater therefore the concentration of Si at the interface will be greater for the second than the first because there is no Si present in the first dopant control layer and Zhang col. 3 lines 27-42 and col. 6 lines 21-29).
As to claim 7, Cheng in view of Zhang disclosed wherein the first and second dopants comprise metal -based dopants wherein a dopant concentration of the first dopants in the first HK gate dielectric layer is less than a dopant concentration of the second dopants in the second HK gate dielectric layer (Zhang col. 3 lines 27-42 and col. 6 lines 21-29).
Continuing to claim 8, Cheng in view of Zhang discloses wherein a first concentration of silicon (Si) in a top portion of the first HK gate dielectric layer is less than a second concentration of Si in a top portion of the second HK gate dielectric layer (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0% which is greater therefore the concentration of Si at the interface will be greater for the second than the first because there is no Si present in the first dopant control layer).
Considering claim 9, Cheng in view of Zhang discloses wherein the first and second dopant control layers comprise titanium silicon nitride layers of different silicon-to-titanium atomic concentration ratio (Cheng [0034], note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0% the second dopant control layer TiSiN with a Si atomic concentration of greater than 0% which is different from the first dopant control layer).
Referring to claim 10, Cheng in view of Zhang disclose wherein the first dopant control layer comprises a titanium silicon nitride (TiSiN) layer with about 0 atomic % to about 30 atomic % of Si with respect to Ti (Cheng [0034] note that the first dopant control layer TiN is a TiSiN layer with a Si atomic concentration of 0%).
Regarding claim 12, Cheng in view of Zhang discloses further comprising first and second work function metal layers disposed on the first and second dopant control layers, respectively (Cheng [0053]-[0054]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200135475 (Cheng et al) in view of US 10825736 (Zhang et al) as applied to claim 1 above, and further in view of US 20040232467 (Otsuki et al).
Concerning claim 11, Cheng in view of Zhang discloses forming the second dopant control layer.
Cheng in view of Zhang does not explicitly disclose the Ti to Si atomic ratio of the TiSiN dopant control layer formed and therefore does not disclose wherein the second dopant control layer comprises a titanium silicon nitride (TiSiN) layer with about 30 atomic % to about 100 atomic % of Si with respect to Ti. However, Otsuki discloses a method of forming a TiSiN layer and a TiSiN layer formed from this method that has an atomic ratio of 10-40% Si with respect to Ti ([0016]). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). See MPEP 2144.04 I. Therefore, absent evidence that the claimed concentration is critical, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the TiSiN layer with the Si atomic ratio 10-40% as disclosed by Otsuki.
Allowable Subject Matter
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 13 recites the limitations wherein the second nitride layer has a semiconductor-to-metal atomic concentration ratio greater than a semiconductor-to-metal atomic concentration ratio of the first nitride layer, wherein the first nitride layer comprises a first semiconductor concentration profile with a decreasing slope from a top surface to a bottom surface of the first nitride layer; and wherein the second nitride layer comprises a second semiconductor concentration profile with an increasing slope from a top surface to a bottom surface of the second nitride layer. These limitations in combination with the other limitations as set forth in the claims are neither taught nor suggested in the prior art. Claims 14-16 depend from this claim and are allowable for at least that reason.
Claim 17 recites the limitations depositing a first nitride layer on the first and second layer portions, comprising depositing the first nitride layer with a first semiconductor concentration profile that has a decreasing slope from a top surface to a bottom surface of the first nitride layer; removing a portion of the first nitride layer to expose the second layer portion; depositing a second nitride layer on the first nitride layer and the second layer portion, comprising depositing the second nitride layer with a second semiconductor concentration profile that has an increasing slope from a top surface to a bottom surface of the second nitride layer, wherein the second nitride layer comprises a semiconductor-to-metal atomic concentration ratio greater than a semiconductor-to-metal atomic concentration ratio of the first nitride layer. These limitations in combination with the other limitations as set forth in the claims are neither taught not suggested in the prior art. Claims 18-20 depend from this claim and are allowable for at least that reason.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/Examiner, Art Unit 2823 10/30/25
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897