DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 2/12/2026. Claims 1, 3-5, 7-10, 12, 21-24, and 26-32 are pending in this application. Claims 1, 12, and 30 are amended. Claims 2 and 25 are canceled. Claims 31-32 are new.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 4/8/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claims 1, 26, and 30 are objected to because of the following informalities:
In claim 1, line 21, “a space between the first and second” should read --the space between the first and second-- (emphasis added).
In claim 26, line 17 “the second side of the substrate” should read --the second side of the semiconductor substrate-- (emphasis added).
In claim 30, line 10 “the through-via to” should read --the through-via -- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pietambaram et al. (US 2020/0258847; hereinafter ‘Pietambaram’).
Regarding claim 1, Pietambaram teaches a structure (401, FIG. 4D, [0078]), comprising:
a package substrate (470, [0079]);
a first molding compound layer (420 surrounding 407, [0079, 0083]; hereinafter ‘420-1’) disposed on the package substrate (420-1 disposed on 470);
first (second 407 from the left; hereinafter ‘407-1’) and second interconnect substrates (third 407 from the left; hereinafter ‘407-2’) disposed on a same surface of the first molding compound layer (407-1 and 407-2 disposed along the same backside surface of 420-1 facing 471, FIG. 4D, [0079]);
a second molding compound layer (420 surrounding 410A and 410B, [0083]; hereinafter ‘420-2’) disposed on the first and second interconnect substrates (420-2 disposed on 407-1 and 407-2, FIG. 4D);
first (410A, [0083]) and second integrated circuit (IC) chips (410B) disposed on the second molding compound layer (410A and 410B disposed on 420-2),
wherein the first IC chip overlaps the first interconnect substrate and is non-overlapping with the second interconnect substrate (410A overlaps 407-1 and is not-overlapping with 407-2), and
wherein the second IC chip overlaps the second interconnect substrate and is non-overlapping with the first interconnect substrate (410B overlaps 407-2 and is not-overlapping with 407-1);
an IC chip coupler (430, [0084]) disposed on the second molding compound layer and on the first and second interconnect substrates (430 disposed 420-2, 407-1, and 407-2) and configured to provide a signal transmission path between the first and second IC chips (430 provides electrical coupling between 410A and 410B, [0084]),
wherein the second molding compound layer extends vertically from a bottom surface of the IC chip coupler to a top surface of the first molding compound layer through a space between the first and second interconnect substrates (420-2 extends vertically from the bottom surface of 430 to the top surface of 420-1 through a space between 407-1 and 407-2, FIG. 4D), and
wherein the IC chip coupler (430) comprises:
a first coupler region (a left portion of 430 overlapping 407-1; hereinafter ‘430-L’) that overlaps with the first interconnect substrate (shown in FIG. 4D),
a second coupler region (a right portion of 430 overlapping 407-2; hereinafter ‘430-R’) that overlaps with the second interconnect substrate (shown in FIG. 4D),
a third coupler region (a central portion of 430 extending over the space between 407-1 and 407-2; hereinafter ‘430-C’) that overlaps with a space between the first and second interconnect substrates (430-C overlaps with the space between 407-1 and 407-2, FIG. 4D); and
a redistribution structure (RDLs comprising pads 425 and vias 424, [0086]; hereinafter ‘RDL’) disposed on the first and second IC chips and the IC chip coupler (RDL disposed on 410A,410B, and 430).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Jung et al. (US 2020/0312826; hereinafter ‘Jung’).
Regarding claim 3, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein top surfaces of the first and second IC chips and the IC chip coupler are substantially coplanar.
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Jung teaches a structure (10, FIG. 1, [0023]), wherein top surfaces of the first (leftmost 500; hereinafter ‘500L’) and second IC chips (second 400 from the left; hereinafter ‘400R’) and the IC chip coupler (leftmost 400, [0050-0051]; hereinafter ‘400L’) are substantially coplanar (the top surface of 500L, 400R and 400L are substantially coplanar, [0053], see the annotated FIG. 1).
As taught by Jung, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein top surfaces of the first and second IC chips and the IC chip coupler are substantially coplanar as claimed, because the resulting level surface facilitates a subsequent process of attaching a common package component over the chips [0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Jung in combination with Pietambaram due to the above reason.
Claims 4-5, 7-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Hou et al. (US 2021/0366814; hereinafter ‘Hou’).
Regarding claim 4, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein surface areas of the first and second coupler regions are substantially equal to each other.
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Hou teaches a structure (150, Fig. 5B, [0016]) wherein surface areas of the first (the region where the dies 131/131A or 131/131C corresponding to the IC chip coupler overlaps with the first interposer 100A corresponding to the first interconnect substrate, FIGS. 5A and 5B, [0033, 0039-0040]; hereinafter referred to as ‘FCRH’) and second coupler regions (the region where 131/131A or 131/131C overlaps with the second interposer 100A corresponding to the second interconnect substrate; hereinafter referred to as ‘SCRH’) are substantially equal (131/131C is positioned symmetrically on both sides of the dashed line 145, which represents the location of the gap (third coupler region; hereinafter referred to as the ‘TCRH’)’, see the annotated FIG. 5B) to each other.
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein surface areas of the first and second coupler regions are substantially equal to each other as claimed, because it enables uniform distribution of electrical connections, thereby enhancing structural robustness and minimizing stress-induced failures [0035]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have been led to the recited overlap symmetry through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram due to the above reason.
Regarding claim 5, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein a total surface area of the first and second coupler regions is equal to or greater than about 50% of a surface area of the third coupler region.
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Hou teaches a structure (150, Fig. 5A, [0033]) wherein a total surface area of the first (FCRH) and second coupler regions (SCRH) is equal to or greater (see the annotated FIG. 5A) than about 50% of a surface area of the third coupler region (TCRH).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein a total surface area of the first and second coupler regions is equal to or greater than about 50% of a surface area of the third coupler region as claimed, because it contributes to reducing interposer warpage, facilitating easier bonding of the device to the substrate while also minimizing stress that could lead to cracking or delamination of the interposer or substrate [0044]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have led to the recited overlap ratio through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram due to the above reason.
Regarding claim 7, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein a surface area of each of the first and second coupler regions is greater than about 5% of a total surface area of the first and second coupler regions.
Hou teaches a structure (150, Fig. 5B, [0016]) wherein a surface area of each of the first (FCRH) and second coupler regions (SCRH) is greater (shown in FIG. 5B) than about 5% of a total surface area of the first (FCRH) and second coupler regions (SCRH).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein a surface area of each of the first and second coupler regions is greater than about 5% of a total surface area of the first and second coupler regions as claimed, because it enables uniform distribution of electrical connections, thereby enhancing structural robustness and minimizing stress-induced failures [0035]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have been led to the recited overlap symmetry through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram due to the above reason.
Regarding claim 8, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein a surface area of the first coupler region is equal to or greater than about 10% of a surface area of the second coupler region.
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Hou teaches a structure (150, Fig. 5A, [0033]) wherein a surface area of the first coupler region (FCRH) is equal to or greater (see the annotated FIG. 5A) than about 10% of a surface area of the second coupler region (SCRH).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein a surface area of the first coupler region is equal to or greater than about 10% of a surface area of the second coupler region as claimed, because it contributes to reducing interposer warpage, facilitating easier bonding of the device to the substrate while also minimizing stress that could lead to cracking or delamination of the interposer or substrate [0044]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have led to the recited overlap ratio through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram due to the above reason.
Regarding claim 9, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein a difference between surface areas of the first and second coupler regions is equal to or less than about 80% of a total surface area of the first and second coupler regions.
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Hou teaches a structure (150, Fig. 5B, [0016]) wherein a difference between surface areas of the first (FCRH) and second coupler regions (SCRH) is equal to or less (see the annotated FIG. 5B) than about 80% of a total surface area of the first (FCRH) and second coupler regions (SCRH).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein a difference between surface areas of the first and second coupler regions is equal to or less than about 80% of a total surface area of the first and second coupler regions as claimed, because it enables uniform distribution of electrical connections, thereby enhancing structural robustness and minimizing stress-induced failures [0035]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have been led to the recited overlap symmetry through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram due to the above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Wu et al. (US 2021/0375785; hereinafter ‘Wu’).
Regarding claim 10, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein a smallest horizontal dimension of each of the first and second coupler regions is greater than about 10 μm.
Wu teaches a structure (300, Fig. 18, [0026, 0060]) wherein a smallest horizontal dimension (separation distance of the adjacent interconnect regions D1, FIGS. 2A and 18, [0024]) of each of the first (the region where the integrated circuit package 350 overlaps with the interconnect region 200B, [0054, 0060]) and second coupler regions (the region where 350 overlaps with the interconnect region 200A, [0054, 0060]) is greater than about 10 μm (D1 in the range of about 40 μm to about 5000 μm, [0024]).
As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein a smallest horizontal dimension of each of the first and second coupler regions is greater than about 10 μm as claimed, because the horizontal dimension between interconnect substrates can be adjusted within an appropriate range to minimize signal interference and promote heat dissipation in electrical circuits, while maintain the mechanical strength of the package, it is necessary to consider the distribution density of all interconnect substrates included in the package [0024].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wu in combination with Pietambaram due to the above reason.
Claims 12 and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Lane et al. (US 9331062; hereinafter ‘Lane’).
Regarding claim 12, Pietambaram teaches the structure of claim 1, but does not teach the structure, wherein the IC chip coupler further comprises; a substrate; an active device layer disposed on the substrate; a first interconnect structure with first conductive lines and first conductive vias disposed on a first side of the substrate and connected to a first side of the active device layer; and a second interconnect structure with second conductive lines and second conductive vias disposed on a second side of the substrate and connected to a second side of the active device layer.
Lane teaches a structure (300, FIG. 4, col. 5, line 35), wherein the IC chip coupler (programmable integrated circuit 10 configured as an interface between a processor and another system component, FIGS. 4 and 5, col. 3, lines 17-21 and col. 8, lines 6-8) further comprises;
a substrate (202, FIG. 5, col. 6, line 41);
an active device layer (an active device layer including transistors 404-1 and 404-2, FIG. 5, col. 6, lines 40-41; hereinafter ‘404L’) disposed on the substrate (404L disposed on 202);
a first interconnect structure (208, FIG. 5, col. 6, line 47) with first conductive lines and first conductive vias (metal routing paths and conductive via structures, col. 4, lines 40-43) disposed on a first side of the substrate (208 disposed on 204, FIG. 3, col. 4, lines 30-34) and connected to a first side of the active device layer (208 connected to a upper side of 404L, FIG. 5); and
a second interconnect structure (210, FIG. 5, col. 6, line 50) with second conductive lines and second conductive vias (metal routing paths and conductive via structures, col. 4, lines 49-51) disposed on a second side of the substrate (210 disposed on 206, FIG. 3, col. 4, lines 30-34) and connected to a second side of the active device layer (210 connected to a lower side of 404L, FIG. 5).
As taught by Lane, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure, wherein the IC chip coupler further comprises; a substrate; an active device layer disposed on the substrate; a first interconnect structure with first conductive lines and first conductive vias disposed on a first side of the substrate and connected to a first side of the active device layer; and a second interconnect structure with second conductive lines and second conductive vias disposed on a second side of the substrate and connected to a second side of the active device layer as claimed, because it separates user signal routing from power supply routing, thereby reducing front-side routing complexity and congestion and allowing power to be supplied directly to the active devices through backside metal routing paths and a bulk via without requiring additional power bus routing in the front-side interconnect stack (col. 3, lines 4-6).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Lane in combination with Pietambaram due to the above reason.
Regarding claim 26, Pietambaram teaches a structure (401, FIG. 4D, [0078]), comprising:
a package substrate (470, [0079]);
first (second 407 from the left, [0079]; hereinafter ‘407-1’) and second interconnect substrates (third 407 from the left; hereinafter ‘407-2’) disposed on a same surface of the package substrate (407-1 and 407-2 disposed on the same upper surface of 470);
first (410A, [0083]) and second integrated circuit (IC) chips (410B) disposed on the first (300L) and second interconnect substrates (410A and 410B disposed on 407-1 and 407-2), respectively;
an IC chip coupler (430, [0084]), disposed on the first and second interconnect substrates (430 disposed between 407-1 and 407-2) and between the first and second IC chips (430 disposed on 410A and 410B); and
a redistribution structure (RDLs comprising pads 425 and vias 424, [0086]; hereinafter ‘RDL’).
Pietambaram does not teach the structure comprising: the IC chip coupler comprises; a semiconductor substrate; a dielectric layer disposed on a first side of the semiconductor substrate; a conductive line disposed in the dielectric layer; a conductive via disposed on a second side of the semiconductor substrate; and a through-via extending vertically from the conductive line to the conductive via through the semiconductor substrate and the dielectric layer and in physical contact with the conductive line and the conductive via; and a redistribution structure disposed on the second side of the substrate and in physical contact with the conductive via.
Lane teaches a structure (300, FIG. 4, col. 5, line 35) comprising:
the IC chip coupler (programmable integrated circuit 10 configured as an interface between a processor and another system component, FIGS. 4 and 5, col. 3, lines 17-21 and col. 8, lines 6-8) comprises;
a semiconductor substrate (202, FIG. 5, col. 6, line 41);
a dielectric layer (a dielectric layer of 208, FIG. 5, col. 4, lines 40-42; hereinafter ‘208D’) disposed on a first side of the semiconductor substrate (208D on 204, FIG. 3, col. 4, lines 30-34);
a conductive line (406, FIG. 5, col. 4, lines 46-47) disposed in the dielectric layer (406 disposed in 208D, FIG. 5);
a conductive via (a conductive via portion formed in 210, vertically aligned with and directly adjoining a lower end of TSV 408, FIG. 5, col. 4, lines 49-51 and col. 7, lines 27-29; hereinafter ‘210V’) disposed on a second side of the semiconductor substrate (210V disposed on 206, FIG. 3, col. 4, lines 30-34); and
a through-via (408, FIG. 5, col. 6, line 46) extending vertically from the conductive line to the conductive via through the semiconductor substrate and the dielectric layer (408 extending vertically from 406 to 210V through 202 and 208D, FIG. 5) and in physical contact with the conductive line and the conductive via (408 in physically contacting 406 and 210V, FIG. 5); and
a redistribution structure (a redistribution layers of 210, col. 4, lines 40-43 and lines 49-51; hereinafter ‘210RS’) disposed on the second side of the substrate (210RS disposed on 206, FIG. 5) and in physical contact with the conductive via (210RS in physically contacting 210V).
As taught by Lane, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure comprising: the IC chip coupler comprises; a semiconductor substrate; a dielectric layer disposed on a first side of the semiconductor substrate; a conductive line disposed in the dielectric layer; a conductive via disposed on a second side of the semiconductor substrate; and a through-via extending vertically from the conductive line to the conductive via through the semiconductor substrate and the dielectric layer and in physical contact with the conductive line and the conductive via; and a redistribution structure disposed on the second side of the substrate and in physical contact with the conductive via as claimed, because it separates user signal routing from power supply routing, thereby reducing front-side routing complexity and providing a vertically integrated connection between the front-side conductive line and the backside redistribution structure through the semiconductor substrate (col. 3, lines 4-6).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Lane in combination with Pietambaram due to the above reason.
Regarding claim 27, Pietambaram in view of Lane teaches the structure of claim 26, further comprising an encapsulating layer (Pietambaram: an encapsulating layer 420 surrounding 410A and 410B, FIG. 4C, [0083]) disposed between the IC chip and the IC chip coupler (420 disposed between 410A/410B and 430, FIG. 4C).
Regarding claim 28, Pietambaram in view of Lane teaches the structure of claim 26, but Pietambaram does not teach the structure wherein the IC chip coupler further comprises an active device layer.
Lane teaches the structure wherein the IC chip coupler further comprises an active device layer (an active device layer including transistors 404-1 and 404-2, FIG. 5, col. 6, lines 40-41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Lane to obtain and achieve the structure wherein the IC chip coupler further comprises an active device layer as claimed, because providing the IC chip coupler with an active device layer enables the coupler itself to perform active processing and interface functions between system components (col. 4, lines 37-39 and col. 8, lines 6-8).
Regarding claim 29, Pietambaram in view of Lane teaches the structure of claim 26, further comprising another encapsulating layer (Pietambaram: an encapsulating layer 420 surrounding 407, FIG. 4A, [0079, 0083]; hereinafter ‘420R’) disposed between the IC chip coupler and package substrate (420R disposed between 430 and 407-1/407-2, FIG. 4D).
Claims 21, 30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Lane (US 9331062) and Chen et al. (US 2014/0077356; hereinafter ‘Chen’).
Regarding claim 21, Pietambaram teaches a structure (401, FIG. 4D, [0078]), comprising:
first (second 407 from the left, [0079]; hereinafter ‘407-1’) and second interconnect substrates (third 407 from the left; hereinafter ‘407-2’) on a same surface level (407-1 and 407-2 disposed on the same upper surface of 471);
first (410A, [0083]) and second integrated circuit (IC) chips (410B) disposed on the first (300L) and second interconnect substrates (410A and 410B disposed on 407-1 and 407-2), respectively;
an IC chip coupler (430, [0084]) disposed between the first and second IC chips (430, [0084] disposed between 407-1 and 407-2) and on the first and second interconnect substrates (430 disposed on 407-1 and 407-2); and
a redistribution structure (RDLs comprising pads 425 and vias 424, [0086]; hereinafter ‘RDL’) disposed on the IC chip coupler (RDL disposed on 410A,410B, and 430).
Pietambaram does not teach the structure wherein the IC chip coupler comprises; a semiconductor substrate; a transistor disposed on a front side of the semiconductor substrate; a dielectric layer disposed on the transistor and on the front side of the semiconductor substrate; a first interconnect structure with first conductive lines and first conductive vias disposed on the dielectric layer and connected to a front side of the transistor; a second interconnect structure with second conductive lines and second conductive vias disposed on a back side of the semiconductor substrate and connected to a back side of the transistor.
Lane teaches a structure (300, FIG. 4, col. 5, line 35) wherein the IC chip coupler (programmable integrated circuit 10 configured as an interface between a processor and another system component, FIGS. 4 and 5, col. 3, lines 17-21 and col. 8, lines 6-8) comprises;
a semiconductor substrate (202, FIG. 5, col. 6, line 41);
a transistor (404-1 and 404-2, FIG. 5, col. 6, lines 40-41; hereinafter ‘404’) disposed on a front side of the semiconductor substrate (404 disposed on 204, FIGS. 3 and 5, col. 4, lines 30-34);
a dielectric layer (a dielectric layer of 208, FIG. 5, col. 4, lines 40-42; hereinafter ‘208D’) disposed on the transistor (208D disposed on 404) and on the front side of the semiconductor substrate (208D on 204, FIGS. 3 and 5, col. 4, lines 30-3);
a first interconnect structure (a first interconnect structure including metal routing paths and conductive via structures of 208, col. 4, lines 40-43; hereinafter ‘208IS’) with first conductive lines (metal routing paths) and first conductive vias (conductive via structures) disposed on the dielectric layer (208IS disposed on 208D) and connected to a front side of the transistor (208IS connected to a upper side of 404, FIG. 5);
a second interconnect structure (a second interconnect structure including metal routing paths and conductive via structures of 210, col. 4, lines 49-51; hereinafter ‘210IS’) with second conductive lines (metal routing paths) and second conductive vias (conductive via structures disposed on a back side of the semiconductor substrate (210IS disposed on 206, FIGS. 3 and 5, col. 4, lines 30-34) and connected to a back side of the transistor (210IS connected to a lower side of 404L, FIG. 5).
As taught by Lane, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein the IC chip coupler comprises; a semiconductor substrate; a transistor disposed on a front side of the semiconductor substrate; a dielectric layer disposed on the transistor and on the front side of the semiconductor substrate; a first interconnect structure with first conductive lines and first conductive vias disposed on the dielectric layer and connected to a front side of the transistor; a second interconnect structure with second conductive lines and second conductive vias disposed on a back side of the semiconductor substrate and connected to a back side of the transistor as claimed, because it separates user signal routing from power supply routing, thereby reducing front-side routing complexity and congestion and allowing power to be supplied directly to the active devices through backside metal routing paths and a bulk via without requiring additional power bus routing in the front-side interconnect stack (col. 3, lines 4-6).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Lane in combination with Pietambaram due to the above reason.
Pietambaram in view of Lane does not teach the structure wherein the IC chip coupler comprises; a stress buffer layer disposed on the first interconnect structure; and a metal via disposed in the stress buffer layer; and wherein the metal via is in physical contact with the redistribution structure.
Chen teaches a structure (100, Fig. 4A, [0004, 0010])
wherein the IC chip coupler (an IC chip coupler including interconnect structure 24, stress buffer layer 36, metal via 44, Figs. 1 and 4A, [0011-0012, 0014]; hereinafter ‘ICCC’) comprises;
a stress buffer layer (36) disposed on the first interconnect structure (24, Fig. 1); and
a metal via (44) disposed in the stress buffer layer (36, Fig. 4A); and
wherein the metal via is in physical contact with the redistribution structure (44 is in physical contact with a redistribution structure including polymer layer 48, under-bump-metallurgy layer 50, and connector 52, Fig. 4A, [0016-0018]).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram in view of Lane to obtain and achieve the structure wherein the IC chip coupler comprises; a stress buffer layer disposed on the first interconnect structure; and a metal via disposed in the stress buffer layer; and wherein the metal via is in physical contact with the redistribution structure as claimed, because the interleaved configuration of conductive features and stress-buffering layers is employed to mitigate mechanical stress arising from subsequent manufacturing process, thereby preventing reliability degradation and enhancing the mechanical integrity of the interconnections [0027-0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chen in combination with Pietambaram in view of Lane due to the above reason.
Regarding claim 30, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein the IC chip coupler further comprises; a semiconductor substrate; a through-via comprising a first end and a second end and extending vertically through the semiconductor substrate; an interconnect structure with conductive lines disposed on a first side of the semiconductor substrate, wherein the first end of the through-via is in physical contact with one of the conductive lines of the interconnect structure; a polymer-based layer disposed on a second side of the semiconductor substrate; and a conductive via extending vertically from the second end of the through-via to to the redistribution structure through the polymer-based layer.
Lane teaches a structure (300, FIG. 4, col. 5, line 35) wherein the IC chip coupler (programmable integrated circuit 10 configured as an interface between a processor and another system component, FIGS. 4 and 5, col. 3, lines 17-21 and col. 8, lines 6-8) further comprises;
a semiconductor substrate (202, FIG. 5, col. 6, line 41);
a through-via (408, FIG. 5, col. 6, line 46) comprising a first end (an upper end of 408 in 208, col. 4, lines 46-47; hereinafter ‘408T’) and a second end (a lower end of 408 in 210, col. 4, lines 43-46; hereinafter ‘408B’) and extending vertically through the semiconductor substrate (408 extending vertically through 202, FIG. 5);
an interconnect structure (208, col. 4, lines 40-43) with conductive lines (406, col. 4, lines 46-47) disposed on a first side of the semiconductor substrate (406 disposed on 204, FIGS. 3 and 5, col. 4, lines 30-34), wherein the first end of the through-via is in physical contact with one of the conductive lines of the interconnect structure (408T is in physically contacting 406, FIG. 5); and
a conductive via (a conductive via portion formed in 210, vertically aligned with and directly adjoining a lower end of TSV 408, FIG. 5, col. 4, lines 49-51 and col. 7, lines 27-29; hereinafter ‘210V’) extending vertically from the second end of the through-via to to the redistribution structure (210V extending vertically from 408B to a redistribution layers of 210, FIG. 5, col. 4, lines 40-43 and lines 49-51).
As taught by Lane, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein the IC chip coupler further comprises; a semiconductor substrate; a through-via comprising a first end and a second end and extending vertically through the semiconductor substrate; an interconnect structure with conductive lines disposed on a first side of the semiconductor substrate, wherein the first end of the through-via is in physical contact with one of the conductive lines of the interconnect structure; and a conductive via extending vertically from the second end of the through-via to to the redistribution structure as claimed, because it separates user signal routing from power supply routing, thereby reducing front-side routing complexity and providing a vertically integrated connection between the front-side conductive line and the backside redistribution structure through the semiconductor substrate (col. 3, lines 4-6).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Lane in combination with Pietambaram due to the above reason.
Pietambaram in view of Lane does not teach the structure wherein the IC chip coupler comprises; a polymer-based layer disposed on a second side of the semiconductor substrate; and a conductive via extending to the redistribution structure through the polymer-based layer.
Chen teaches a structure (100, Fig. 4A, [0004, 0010])
wherein the IC chip coupler (an IC chip coupler including interconnect structure 24, stress buffer layer 36, metal via 44, Figs. 1 and 4A, [0011-0012, 0014]; hereinafter ‘ICCC’) comprises;
a polymer-based layer (36); and
a conductive via (44) extending to the redistribution structure (a redistribution structure including polymer layer 48, under-bump-metallurgy layer 50, and connector 52, Fig. 4A, [0016-0018]; hereinafter ‘RS’) through the polymer-based layer (44 extending to RS through 36, Fig. 4A).
Although, Chen does not explicitly teach the polymer-based layer disposed on a second side of the semiconductor substrate.
Chen, however, discloses that connector 52 is formed over under-bump-metallurgy layer 50 and electrically connected to metal via 44 for providing an external electrical connection (FIG. 4A, [0016-0018]). Lane similarly provides bumps 402 on the second side of the semiconductor substrate for external electrical connection. Accordingly, one of ordinary skill in the art would have understood that Chen’s polymer-based layer 36 and associated conductive interconnect structure are applicable to the bump-bearing second side of Lane’s semiconductor substrate.
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram in view of Lane to obtain and achieve the structure wherein the IC chip coupler comprises; a polymer-based layer disposed on a second side of the semiconductor substrate; and a conductive via extending to the redistribution structure through the polymer-based layer as claimed, because providing Chen’s polymer-supported conductive interconnect structure on the bump-bearing second side of Lane’s semiconductor substrate reduces delamination caused by a mismatch between the coefficients of thermal expansion of the conductive interconnect and polymer layers during thermal cycling, thereby improving the mechanical integrity and reliability of the interconnections [0027-0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chen in combination with Pietambaram in view of Lane due to the above reason.
Regarding claim 32, Pietambaram in view of Lane and Chen teaches the structure of claim 21, Pietambaram in view of Chen does not teach the structure wherein the IC chip coupler further comprises a through-via extending vertically, through the semiconductor substrate, from a back side of a source/drain region of the transistor and to one of the second conductive lines of the second interconnect structure.
Lane teaches the structure wherein the IC chip coupler (programmable integrated circuit 10 configured as an interface between a processor and another system component, FIGS. 4 and 5, col. 3, lines 17-21 and col. 8, lines 6-8) further comprises a through-via (412, FIG. 5, col. 6, line 51) extending vertically, through the semiconductor substrate, from a back side of a source/drain region of the transistor and to one of the second conductive lines of the second interconnect structure (4412 extending vertically through 202 from a back side of 405 of 404-2 to metal routing paths of 210IS, FIG. 5, col. 4, lines 49-51 and col. 6, lines 51-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Lane to obtain and achieve the structure wherein the IC chip coupler further comprises a through-via extending vertically, through the semiconductor substrate, from a back side of a source/drain region of the transistor and to one of the second conductive lines of the second interconnect structure as claimed, because it separates user signal routing from power supply routing, thereby reducing front-side routing complexity and providing a vertically integrated connection between the front-side conductive line and the backside redistribution structure through the semiconductor substrate (col. 3, lines 4-6).
Claims 22-24 is rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Lane (US 9331062) and Chen (US 2014/0077356), and further in view of Hou (US 2021/0366814).
Regarding claim 22, Pietambaram in view of Lane and Chen teaches the structure of claim 21, but does not teach the structure wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 50 % of a surface area of the IC chip coupler overlapping a space between the first and second interconnect substrates.
Hou teaches a structure (150, Fig. 5B, [0016]) wherein a surface area of the IC chip coupler (surface area of 131/131A, FIG. 5A, [0033]; hereinafter referred to as coupler region, ‘CR’) overlapping the first and second interconnect substrates (CR overlapping 100A and 100B, [0035]) is equal to or greater (shown in FIG. 5A) than about 50 % of a surface area of the IC chip coupler (surface area of 131/131A; hereinafter referred to as third coupler region, ‘TCR’) overlapping a space (space, FIG. 5A) between the first and second interconnect substrates (TCR overlapping the space between 100A and 100B).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram in view of Lane and Chen to obtain and achieve the structure wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 50 % of a surface area of the IC chip coupler overlapping a space between the first and second interconnect substrates as claimed, because it contributes to reducing interposer warpage, facilitating easier bonding of the device to the substrate while also minimizing stress that could lead to cracking or delamination of the interposer or substrate [0044]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have led to the recited overlap ratio through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram in view of Lane and Chen due to the above reason.
Regarding claim 23, Pietambaram in view of Lane and Chen teaches the structure of claim 21, but does not teach the structure wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 50 % of a surface area of the IC chip coupler overlapping a space between the first and second interconnect substrates.
Hou teaches a structure (150, Fig. 5B, [0016]) wherein a surface area of the IC chip coupler (CR) overlapping the first and second interconnect substrates (CR overlapping 100A and 100B) is equal to or greater (shown in FIG. 5A) than about 20 % of a total surface area of the IC chip coupler (TCR).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into J Pietambaram in view of Lane and Chen to obtain and achieve wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 20 % of a total surface area of the IC chip coupler as claimed, because it contributes to reducing interposer warpage, facilitating easier bonding of the device to the substrate while also minimizing stress that could lead to cracking or delamination of the interposer or substrate [0044]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have led to the recited overlap ratio through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram in view of Lane and Chen due to the above reason.
Regarding claim 24, Pietambaram in view of Lane and Chen teaches the structure of claim 21, but does not teach the structure wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 50 % of a surface area of the IC chip coupler overlapping a space between the first and second interconnect substrates.
Hou teaches a structure (150, Fig. 5B, [0016]) wherein a first surface area of the IC chip coupler (first surface area of 131 and 131A; hereinafter referred to as ‘FCR’) overlapping (shown in FIG. 5A) the first interconnect substrate (100A) is equal to or greater (shown in FIG. 5A) than about 10 % of a second surface area of the IC chip coupler (second surface area of 131 and 131A; hereinafter referred to as ‘SCR’) overlapping (shown in FIG. 5A) the second interconnect substrate (100B).
As taught by Hou, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram in view of Lane and Chen to obtain and achieve the structure wherein a surface area of the IC chip coupler overlapping the first and second interconnect substrates is equal to or greater than about 20 % of a total surface area of the IC chip coupler as claimed, because it contributes to reducing interposer warpage, facilitating easier bonding of the device to the substrate while also minimizing stress that could lead to cracking or delamination of the interposer or substrate [0044]. Further, the overlap ratio between the interconnect substrate and the IC chip coupler region is well known to influence the structural properties and varies depending on the intended structural arrangement and target characteristics, such as electrical connectivity and mechanical stability. One of ordinary skill in the art would have led to the recited overlap ratio through routine experimentation to achieve desired characteristics of the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hou in combination with Pietambaram in view of Lane and Chen due to the above reason.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US 2020/0258847) in view of Wodnicki et al. (US 2011/0071397; hereinafter ‘Wodnicki’).
Regarding claim 31, Pietambaram teaches the structure of claim 1, but does not teach the structure wherein the third coupler region comprises a width of about 10 µm to about 200 µm.
Wodnicki teaches a structure (FIG. 8, [0058]) having a minimal gap 835 between a first interconnect substrate (the interposer 840 of the tileable module 805) and a second interconnect substrate (the interposer 840 of the tileable module 810), wherein the gap has a width of about 100 µm (module-to-module edge placement 1130, FIG. 11B, [0064]). Accordingly, configuring the spacing between Pietambaram’s first and second interconnect substrates 407-1 and 407-2 in accordance with Wodnicki’s teaching would provide the third coupler region 430-C, which extends over the space between interconnect substrates 407-1 and 407-2, with a corresponding width within the claimed range of about 10 µm to about 200 µm.
As taught by Wodnicki, one of ordinary skill in the art would utilize and modify the above teaching into Pietambaram to obtain and achieve the structure wherein the third coupler region comprises a width of about 10 µm to about 200 µm as claimed, because minimizing the gap between adjacent interconnect substrate assemblies provides a compact structure and increases usable component coverage [0007, 0032, 0077]. Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Wodnicki in combination with Pietambaram due to the above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new grounds of rejection based on newly applied prior art. The claims were not amended in a manner that overcame the newly applied rejections. Response to arguments on newly added limitations are responded to in the above rejection.
Claim 1
Applicant submits, in pages 9-10 of Remark, that
“amended claim 1 is not obvious over Jung individually or in combination with Pietambaram, Lin, Hou, Wu, or Chen”.
The examiner respectfully disagrees.
The arguments address the prior obviousness rejection based on the combination of Jung, Pietambaram and Lin. As amended, however, claim 1 is rejected under 35 U.S.C. §102 based on Pietambaram alone. As set forth above, Pietambaram teaches each limitation of amended claim 1. Accordingly, Applicant’s arguments concerning the prior combination do not overcome the present rejection.
Claim 1
Applicant submits, in pages 9-10 of Remark, that
“amended claim 1 is not obvious over Jung individually or in combination with Pietambaram, Lin, Hou, Wu, or Chen”.
The examiner respectfully disagrees.
The arguments address the prior obviousness rejection based on the combination of Jung, Pietambaram and Lin. As amended, however, claim 1 is rejected under 35 U.S.C. §102 based on Pietambaram alone. As set forth above, Pietambaram teaches each limitation of amended claim 1. Accordingly, Applicant’s arguments concerning the prior combination do not overcome the present rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Delacruz et al. (US 2020/0357641) and GANESAN et al. (US 2021/0043570) as a semiconductor package with integrated circuit chip couplers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703) 756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/3/26
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