DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 29 December 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (2017/0104060) in view of Jung et al. (U.S. Pub. 2020/0027992) in view of Li (U.S. Pub. 2018/0102363).
Claim 1: Balakrishnan et al. discloses a method in Figs. 1-9, comprising:
depositing a first semiconductor stack (stack of layer 14, layers 16 and layers 18) over a first area (24A) and a second area (24B) of a silicon substrate (10) such that the first semiconductor stack (stack of layer 14, layers 16 and layers 18) interfaces a top surface (top surface of 10 in 24A) of the first area (24A) and a top surface (top surface of 10 in 24B) of the second area (24B), the first semiconductor stack (stack of layer 14, layers 16 and layers 18) comprising a first number of channel layers (16) interleaved by a second number of sacrificial layers (14 and 18) (paragraph 32);
depositing a hard mask layer (22 and/or 22A) over the first semiconductor stack (stack of layer 14, layers 16 and layers 18) directly over the first area (24A) (paragraph 33);
after the depositing of the hard mask layer (22 and/or 22A), removing (recessing using a RIE process) the first semiconductor stack (stack of layer 14, layers 16 and layers 18) directly over the second area (24B) (paragraph 33);
after the removing, depositing a second semiconductor stack (stack of layers 26 and layers 28) directly over the second area (24B), the second semiconductor stack (stack of layers 26 and layers 28) comprising a third number of channel layers (26) interleaved by a fourth number of sacrificial layers (28) (paragraph 35);
removing the hard mask layer (22 and/or 22A) (paragraph 39);
patterning the first semiconductor stack (stack of layer 14, layers 16 and layers 18) in the first area (24A) to form a first fin-shaped structure (32A) having a channel region (region of 32A) and a source/drain region (region where source/drain features are formed) and extending along a first direction (vertical direction in Fig. 5A) (paragraphs 37 and 38);
patterning the second semiconductor stack (stack of layers 26 and layers 28) in the second area (24B) to form a second fin-shaped structure (32B) having a channel region (region of 32B) and a source/drain region (region where source/drain features are formed) and extending along the first direction (paragraphs 37 and 38);
forming a first dummy gate stack (dummy gate) over the channel region (region of 32A) of the first fin-shaped structure (32A) and a second dummy gate stack (44) over the channel region (region of 32B) of the second fin-shaped structure (32B) (paragraph 44);
forming a first source/drain feature (source/drain) over the source/drain region (region where source/drain features are formed) of the first fin-shaped structure (32A) and a second source/drain feature (source/drain) over the source/drain region (region where source/drain features are formed) of the second fin-shaped structure (32B) (paragraph 44);
removing the first dummy gate stack (dummy gate) and the second dummy gate stack (44) (paragraphs 44 and 49);
selectively removing the second number of sacrificial layers (14 and 18) in the channel region (region of 32B) of the first fin-shaped structure (32B) and the fourth number of sacrificial layers (28) in the channel region (region of 32B) of the second fin-shaped structure (32B) to form a first number of channel members (16) in the first area (24A) and a second number of channel members (26) in the second area (24B) (paragraphs 40 and 41); and
forming a first gate structure (40) to wrap around each of the first number of channel members (16) and a second gate structure (54) to wrap around each of the second number of channel members (26) (paragraphs 44 and 50).
Balakrishnan et al. appears not to explicitly disclose patterning a portion of the silicon substrate in the first area to form the first fin-shaped structure;
patterning a portion of the silicon substrate in the second area to form the second fin-shaped structure;
after patterning the first semiconductor stack and the second semiconductor stack, forming an isolation feature over the silicon substrate to interface lower sidewalls of the first fin-shaped structure and sidewalls of the second fin-shaped structure; and
forming gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction, wherein the gate end dielectric features are disposed on the isolation feature.
Jung et al., however, in Figs. 4B, 6A, 6D and 7D and in paragraphs 17, 20, 52, 57, 63, 65 and 66, discloses patterning a portion of the silicon substrate (100) in the first area (RG2) to form the first fin-shaped structure (PCH and AP4);
patterning a portion of the silicon substrate (100) in the second area (RG1) to form the second fin-shaped structure (PAP);
after patterning the first semiconductor stack (111 and 112) and the second semiconductor stack (lower 113 and upper 113), forming an isolation feature (ST1) over the silicon substrate (100) to interface lower sidewalls (lower sidewalls of AP4 and PAP) of the first fin-shaped structure (PCH and AP4) and sidewalls of (lower sidewalls of PAP) the second fin-shaped structure (PAP); and
forming gate end dielectric features (GS), wherein the gate end dielectric features (GS) are disposed on the isolation feature (ST1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Jung et al. to have patterned a portion of the silicon substrate in the first area to form the first fin-shaped structure; and patterned a portion of the silicon substrate in the second area to form the second fin-shaped structure in order to have more functionality in the device; and to have after patterning the first semiconductor stack and the second semiconductor stack, formed an isolation feature over the silicon substrate to interface lower sidewalls of the first fin-shaped structure and sidewalls of the second fin-shaped structure; and
formed gate end dielectric features, wherein the gate end dielectric features are disposed on the isolation feature in order to protect the surrounding the elements.
Since the gate end dielectric features of Jung et al. is substantially the same as the gate end dielectric features of the claims, Jung et al. would therefore disclose forming gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction.
Balakrishnan et al. in view of Jung et al. appears not to explicitly disclose the silicon substrate comprising a plurality of n-type doped regions and a plurality of p-type doped regions; and
the isolation feature over the silicon substrate to interface one of the plurality of n-type doped regions.
Li, however, in Fig. 1 and in paragraph 16, discloses the substrate (10) comprising a plurality of n-type doped regions (left and right regions of 11) and a plurality of p-type doped regions (left and right regions of 12); and
the isolation feature (13) over the substrate to interface one of the plurality of n-type doped regions (left region of 11).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. in view of Jung et al. with the disclosure of Li to have the silicon substrate comprising a plurality of n-type doped regions and a plurality of p-type doped regions; and
the isolation feature over the silicon substrate to interface one of the plurality of n-type doped regions in order to in order to have NMOS and PMOS that has fast switching speeds and lower leakage current, respectively, while protecting the surrounding elements.
Claim 2: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1, and Balakrishnan et al., in Fig. 3 and in paragraphs 32 and 35, further discloses wherein the first number of channel members (16) and the third number of channel members (26) consist essentially of silicon (Si).
Claim 3: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1, and Balakrishnan et al., in Fig. 3 and in paragraphs 32 and 35, further discloses wherein the second number of sacrificial layers (14 and 18) and the fourth number of sacrificial layers (28) consist essentially of silicon germanium (SiGe).
Claim 4: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1, and Balakrishnan et al., in Fig. 3 and in paragraphs 32 and 35, further discloses
wherein the first number (number of layers 16) is greater than the third number (number of layers 26),
wherein the second number (number of layers 14 and 18) is greater than the fourth number (number of layers 28).
Claim 5: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1, and Balakrishnan et al., in Fig. 3 and in paragraphs 32 and 35, further discloses
wherein each of the second number of sacrificial layers (14 and 18) has a first thickness (thickness of 14 and thickness of 18),
wherein each of the fourth number of sacrificial layers (28) has a second thickness (thickness of 28),
wherein the second thickness (thickness of 28) is greater than the first thickness (thickness of 14 and thickness of 18).
Claim 6: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 5.
Balakrishnan et al. in view of Jung et al., as applied to claim 5, appears not to explicitly disclose discloses wherein a ratio of the second thickness to the first thickness is between about 1.1 and 1.5.
Balakrishnan et al., however, further discloses a ratio of the second thickness to the first thickness is a result affecting parameter because it affects the ability to integrate diverse applications on a single substrate (paragraph 30 and 31).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the ratio of the second thickness to the first thickness of Balakrishnan et al. in view of Jung et al. in order to achieve the integration of diverse applications on a single substrate to have a device having multiple functions while having small device dimensions according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Claim 7: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1, and Balakrishnan et al., in Fig. 3 and in paragraphs 32 and 35, further discloses
wherein each of the first number of channel layers (16) has a third thickness (thickness of 16),
wherein each of the third number of channel layers (26) has a fourth thickness (thickness of 26),
wherein the third thickness (thickness of 16) is substantially equal to the fourth thickness (thickness of 26).
Claim 8: Balakrishnan et al. in view of Jung et al. in view of Li discloses the method of claim 1.
Balakrishnan et al. in view of Jung et al. in view of Li, as applied to claim 1, appears not to explicitly disclose wherein the forming of the gate end dielectric features is performed before the forming of the first source/drain feature and the second source/drain feature.
Jung et al., however, in Figs. 6D and 7D and in paragraphs 63, 65 and 66, discloses the forming of the gate end dielectric features (GS) is performed before the forming of the first source/drain feature (SD1) and the second source/drain feature (SD1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Jung et al. to have made the forming of the gate end dielectric features performed before the forming of the first source/drain feature and the second source/drain feature in order to protect the surrounding the elements.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (2017/0104060) in view of Jung et al. (U.S. Pub. 2020/0027992) in view of Min et al. (U.S. Pub. 2017/0345712).
Claim 9: Balakrishnan et al. discloses a method in Figs. 1-9, comprising:
forming a first stack (stack of layer 14, layers 16 and layers 18) directly on a first area (24A) of a semiconductor substrate (10), the first stack (stack of layer 14, layers 16 and layers 18) comprising first channel layers (16) interleaved by a first sacrificial layers (14 and 18) (paragraph 32);
forming a second stack (stack of layers 26 and layers 28) directly on a second area (24B) of a semiconductor substrate (10), the second stack (stack of layers 26 and layers 28) comprising second channel layers (26) interleaved by second sacrificial layers (28) (paragraph 35);
patterning the first stack (stack of layer 14, layers 16 and layers 18) in the first area (24A) to form a first fin-shaped structure (32A) extending lengthwise along a first direction (vertical direction in Fig. 5A) (paragraphs 37 and 38);
patterning the second stack (stack of layers 26 and layers 28) in the second area (24B) to form a second fin-shaped structure (32B) extending lengthwise along the first direction (paragraph 37 and 38);
forming a first dummy gate stack (dummy gate) over the first fin-shaped structure (32A) and a second dummy gate stack (44) over the second fin-shaped structure (32B) (paragraph 44);
forming a first source/drain feature (source/drain) adjacent the first dummy gate stack (dummy gate) and a second source/drain feature (source drain) adjacent the second dummy gate stack (44) (paragraph 44);
removing the first dummy gate stack (dummy gate) and the second dummy gate stack (44) (paragraphs 44 and 49);
selectively removing the first sacrificial layers (18) of the first fin-shaped structure (32A) and the second sacrificial layers (28) of the second fin-shaped structure (32B) to form first channel members (16) in the first area (24A) and second channel members (26) in the second area (24B) (paragraphs 40 and 41); and
forming a first gate structure (38 and 40) to wrap around each of the first channel members (16) and a second gate structure (52 and 54) to wrap around each of the second channel members (26) (paragraphs 44, 47 and 50),
wherein, after the forming of the first stack (stack of layer 14, layers 16 and layers 18), a bottommost (14) one of the first sacrificial layers (14 and 18) interfaces a top surface (top surface of 10 in 24A) of the first area (24A) of the semiconductor substrate (10) and a top surface (top surface of 10 in 24B) of the second area (24B) of the semiconductor substrate (10),
wherein the first gate structure (38 and 40) comprises a first gate dielectric layer (38) and the second gate structure (52 and 24) comprises a second gate dielectric layer (52),
wherein the first gate dielectric layer (38) has a first thickness (thickness of 38) and the second gate dielectric layer (52) has a second thickness (thickness of 52) greater than the first thickness.
Balakrishnan et al. appears not to explicitly disclose patterning a portion of the semiconductor substrate in the first area to form the first fin-shaped structure;
patterning a portion of the semiconductor substrate in the second area to form the second fin-shaped structure;
forming an isolation feature over the semiconductor substrate to interface lower sidewalls of the first fin-shaped structure and the second fin-shaped structure;
forming gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction; and
depositing a gate-top mask layer over the first gate structure, the second gate structure, and the gate end dielectric feature.
Jung et al., however, in Figs. 4B, 6A, 6D, 8C and 9D and in paragraphs 17, 20, 49, 52, 57, 63, 65, 70, 74 and 84, discloses
patterning a portion of the semiconductor substrate (100) in the first area (left area of RG2) to form the first fin-shaped structure (left PCH and AP3);
patterning a portion of the semiconductor substrate (100) in the second area (right area of RG2) to form the second fin-shaped structure (right PCH and AP3);
forming an isolation feature (ST1) over the semiconductor substrate (100) to interface lower sidewalls (lower sidewalls of left AP3 and right AP3) of the first fin-shaped structure (left PCH and AP3) and the second fin-shaped structure (right PCH and AP3);
forming gate end dielectric features (GS); and
depositing a gate-top mask layer (120) over the first gate structure (GE1 on the left), the second gate structure (GE2 on the right), and the gate end dielectric feature (GS).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Jung et al. to have patterned a portion of the semiconductor substrate in the first area to form the first fin-shaped structure; and
patterned a portion of the semiconductor substrate in the second area to form the second fin-shaped structure in order to have more functionality in the device; and
to have formed an isolation feature over the semiconductor substrate to interface lower sidewalls of the first fin-shaped structure and the second fin-shaped structure;
formed gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction; and
deposited a gate-top mask layer over the first gate structure, the second gate structure, and the gate end dielectric feature,
wherein the gate end dielectric features are disposed on the isolation feature in order to protect the surrounding elements.
Since the gate end dielectric features of Jung et al. is substantially the same as the gate end dielectric features of the claims, Jung et al. would therefore disclose forming gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction.
Balakrishnan et al. in view of Jung et al. appears not to explicitly disclose the first dummy gate stack comprising a first dimension along the first direction and the second dummy gate stack comprising a second dimension along the first direction,
wherein the second dimension is greater than the first dimension.
Min et al., however, in Fig. 8A and in paragraph 95, discloses the first dummy gate stack (D107A) comprising a first dimension (D107aW) along the first direction (X direction) and the second dummy gate stack (D307b) comprising a second dimension (D307bW) along the first direction (X direction),
wherein the second dimension (D307bW) is greater than the first dimension (D107aW).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. in view of Jung et al. with the disclosure of Min et al. to have made the first dummy gate stack comprising a first dimension along the first direction and the second dummy gate stack comprising a second dimension along the first direction,
wherein the second dimension is greater than the first dimension in order to have different gate widths that has lower gate resistance with greater widths and lower parasitic capacitance with smaller widths.
Claim 10: Balakrishnan et al. in view of Jung et al. in view of Min et al. discloses the method of claim 9 and Balakrishnan et al. further discloses wherein the semiconductor substrate comprises silicon (paragraphs 32 and 35).
Balakrishnan et al. in view of Jung et al. in view of Min et al., as applied to claim 9, appears not to explicitly disclose wherein the gate end dielectric features are disposed on the isolation feature.
Jung et al., however, in Figs.6A, 6B and 6D and in paragraphs 60 and 63, further discloses the gate end dielectric features (GS) are disposed on the isolation feature (ST1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. in view of Jung et al. in view of Min et al. with the further disclosure of Jung et al. to have made the gate end dielectric features are disposed on the isolation feature in order to protect the surrounding elements.
Claim 11: Balakrishnan et al. in view of Jung et al. in view of Min et al. discloses the method of claim 9.
Balakrishnan et al. in view of Jung et al. appears not to explicitly disclose wherein a ratio of the second thickness to the first thickness is between about 1.3 and about 3.0.
The ratio of the second thickness to the first thickness is a resulting affecting parameter because the ratio of the second thickness to the first thickness affects the electrical properties of the device.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to optimize, for example by routine experimentation, the ratio of the first thickness to the second thickness of Balakrishnan et al. in view of Jung et al. in order to have the desired electrical properties according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Claim 12: Balakrishnan et al. in view of Jung et al. in view of Min et al. discloses the method of claim 9, and Balakrishnan et al., in paragraph 47, further discloses wherein the first gate dielectric layer (38) and the second gate dielectric layer (52) comprise ZrO, Y2O3, La2O5, Gd2O5, TiO2, Ta2O5, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, or SrTiO (paragraph 47).
Claim 13: Balakrishnan et al. in view of Jung et al. in view of Min et al. discloses the method of claim 9.
Balakrishnan et al. in view of Jung et al. in view of Min et al., as applied to claim 9, appears not to explicitly disclose wherein, after the selectively removing the first sacrificial layers and the second sacrificial layers, the first channel members are disposed directly over a first base fin and the second channel members are disposed directly over a second base fin,
wherein the first base fin and the second base fin are formed from the semiconductor substrate.
Jung et al., however, in Fig. 8C and in paragraphs 65 and 70, further discloses after the selectively removing the first sacrificial layers (portion of 111 on the left) and the second sacrificial layers (portion of 111 on the right), the first channel members (CH3 on the left) are disposed directly over a first base fin (AP3 on the left) and the second channel members (CH3 on the right) are disposed directly over a second base fin (AP3 on the right), and
wherein the first base fin (AP2 on the left) and the second base fin (AP3 on the right) are formed from the semiconductor substrate (100).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. in view of Jung et al. in view of Min et al. with the further disclosure of Jung et al. to, after the selectively removing the first sacrificial layers and the second sacrificial layers, the first channel members are disposed directly over a first base fin and the second channel members are disposed directly over a second base fin,
the first base fin and the second base fin are formed from the semiconductor substrate in order to have more functionality in the device.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. in view of Jung et al. in view of Min et al. as applied to claim 13 above, and further in view of Noh et al. (U.S. Pub. 2020/0006333).
Claim 14: Balakrishnan et al. in view of Jung et al. in view of Min et al. discloses the method of claim 13.
Balakrishnan et al. in view of Jung et al. in view of Min et al. appears not to explicitly disclose wherein, after the forming of the first gate structure and the second gate structure, the first gate structure is in direct contact with the first base fin and the second gate structure is in direct contact with the second base fin.
Noh et al., however, in Fig. 25 and in paragraph 130, further discloses after the forming of the gate structure (362), the structure is in direct contact with the base fin (102)
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. in view of Jung et al. in view of Min et al. with the disclosure of Noh et al. to have the made first gate structure is in direct contact with the first base fin and the second gate structure is in direct contact with the second base fin after the forming of the first gate structure and the second gate structure in order to control the current in the base fin.
Claim(s) 15-17 and 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan et al. (2017/0104060) in view of Song et al. (U.S. Pub. 2020/0286992) in view of Jung et al. (U.S. Pub. 2020/0027992) in view of Pae et al. (U.S. Pub. 2017/0140997).
Claim 15: Balakrishnan et al. discloses a method in Figs. 1-9, comprising:
receiving a substrate (10) comprising a first region (24A) and a second region (24B),
forming a first plurality of alternating semiconductor layers (stack of layers Si and SiGe) over the first region (24B) and the second region (24A) of a substrate (10), the first plurality of alternating semiconductor layers (stack of layers Si and SiGe) comprising a first plurality (16) of first semiconductor layers (Si) interleaved by a second plurality (18) of second semiconductor layers (SiGe) (paragraph 32);
removing the first plurality of alternating semiconductor layers (stack of layers Si and SiGe) over the first region (24B) of the substrate (10) (paragraph 33); and
forming a second plurality of alternating semiconductor layers (stack of layers Si and SiGe) over the first region (24B) of the substrate (10), the second plurality of alternating semiconductor layers (stack of layers Si and SiGe) comprising a third plurality (26) of first semiconductor layers (Si) interleaved by a fourth plurality (28) of second semiconductor layers (SiGe) (paragraph 35),
patterning the second plurality of alternating semiconductor layers (stack of layers Si and SiGe) over the first region (24B) to form a first active region (32B) extending lengthwise along a first direction (vertical direction in Fig. 5A) and having a first width (width of 32B) along a second direction (horizontal direction in Figs. 4 and 5A) perpendicular to the first direction (paragraphs 37 and 38);
patterning the first plurality of alternating semiconductor layers (stack of layers Si and SiGe) over the second region (24A) to form a second active region (32A) extending lengthwise along the first direction (vertical direction in Fig. 5A) and having a second width (width of 32A) along the second direction (horizontal direction in Figs. 4 and 5A) (paragraphs 37 and 38);
wherein, after the forming of the first plurality of alternating semiconductor layers (stack of layers Si and SiGe), a bottommost (bottommost SiGe) one of the second plurality of second semiconductor layers (SiGe) interfaces the substrate (10).
Balakrishnan et al. appears not to explicitly disclose the first region comprises a first plurality of doped regions and the second region comprises a second plurality of doped regions, and
the bottommost one of the second plurality of second semiconductor layers interfaces the first plurality of doped regions and the second plurality of doped region.
Song et al., however, in Fig. 2 and in paragraphs 22 and 24, discloses the first region (left region of 102 and 104) comprises a first plurality of doped region (left region of 102 and left region of 104) and the second region (right region of 102 and 104) comprises a second plurality of doped regions (right region of 102 and right region of 104),
the bottommost (106-1) one of the second plurality of second semiconductor layers (106-1, 106-2, 106-3 and 106-4) interfaces the first plurality of doped regions (left region of 102 and left region of 104) and the second plurality of doped region (left region of 102 and left region of 104) in order to be able to form the desired device type.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Song et al. to have made the first region comprises a first plurality of doped regions and the second region comprises a second plurality of doped regions, and
the bottommost one of the second plurality of second semiconductor layers interfaces the first plurality of doped regions and the second plurality of doped region in order to be able to form the desired device type (paragraph 24 of Song et al.).
Balakrishnan et al. also appears not to explicitly disclose after the patterning over the first region and the second region, forming a shallow trench isolation (STI) feature over the substrate to surround lower portions of the first active region and the second active region; and
forming a first gate end dielectric feature over the STI feature in the first region and a second gate end dielectric feature of the STI feature in the second region.
Jung et al., however, in Fig. 4B and in paragraph 57, discloses after the patterning over the first region (RG2) and the second region (RG1), forming a shallow trench isolation (STI) feature over the substrate (100) to surround lower portions (lower portions of AP4 and PAP) of the first active region (PCH and AP4) and the second active region (PAP); and
forming a first gate end dielectric feature (GS) over the STI feature (ST1) in the first region (RG2) and a second gate end dielectric feature (GS) of the STI feature (ST1) in the second region (RG1).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Jung et al. to have, after the patterning over the first region and the second region, forming a shallow trench isolation (STI) feature over the substrate to surround lower portions of the first active region and the second active region; and
forming a first gate end dielectric feature over the STI feature in the first region and a second gate end dielectric feature of the STI feature in the second region in order to protect the surrounding elements and to have more functionality in the device.
Balakrishnan et al. also appears not to explicitly disclose wherein the second width is greater than the first width.
Pae et al., however, in Fig. 16 and in paragraphs 65 and 71, discloses the second width (W2+W4) is greater than the first width (W3) in order to have nMOSFET and pMOSFET.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Balakrishnan et al. with the disclosure of Pae et al. to have made the second width is greater than the first width in order to in order to have nMOSFET and pMOSFET that has fast switching speeds and lower leakage current, respectively.
Claim 16: Balakrishnan et al. in view of Song et al. in view of Jung et al. in view of Pae et al. discloses the method of claim 15, and Balakrishnan et al., in Fig. 3, further discloses
wherein the first plurality (16) of first semiconductor layers (Si) comprises a first layer pitch (distance between 16),
wherein the third plurality (26) of first semiconductor layers (Si) comprises a second layer pitch (distance between 26) greater than the first layer pitch.
Claim 17: Balakrishnan et al. in view of Song et al. in view of Jung et al. in view of Pae et al. discloses the method of claim 15, and Balakrishnan et al., in Fig. 3, further discloses
wherein each of the second plurality (18) of second semiconductor layers (SiGe) comprises a first layer thickness (thickness of 18),
wherein each of the fourth plurality (28) of fourth semiconductor layers (SiGe) comprises a second layer thickness (thickness of 28) greater than the first layer thickness.
Claim 19: Balakrishnan et al. in view of Song et al. in view of Jung et al. in view of Pae et al. discloses the method of claim 15, and Balakrishnan et al., in Fig. 3 and in paragraphs 37 and 38, discloses further comprising:
in a first channel region (region of 32B) of the first active region (24B), forming a first plurality of channel members (26) out of the first plurality of first semiconductor layers (stack of layers Si and SiGe); and
in a second channel region (region of 32A) of the second active region (24A), forming a second plurality of channel members (16) out of the third plurality of first semiconductor layers (stack of layers Si and SiGe).
Claim 20: Balakrishnan et al. in view of Song et al. in view of Jung et al. in view of Pae et al. discloses the method of claim 15, and Balakrishnan et al., in Fig. 8 and in paragraphs 44, 47 and 50, discloses further comprising:
forming a first gate dielectric layer (52) to a first thickness (thickness of 52) over the first plurality of channel members (26); and
forming a second gate dielectric layer (38) to a second thickness (thickness of 38) over the second plurality of channel members (16),
wherein the first thickness (thickness of 52) is greater than the second thickness (thickness of 38).
Claim 21: Balakrishnan et al. in view of Song et al. in view of Jung et al. in view of Pae et al. discloses the method of claim 15, and Balakrishnan et al., in Fig. 3 and in paragraph 35, further discloses
wherein each of the first plurality (16) of first semiconductor layers (Si) comprises a third layer thickness (thickness of 16),
wherein each of the third plurality (26) of first semiconductor layers (Si) comprises a fourth layer thickness (thickness of 26) substantially similar to the third layer thickness (thickness of 16).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 19-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights