DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 09/04/2025 is acknowledged.
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 09/04/2025. Claims 16-20 are withdrawn.
Claim Objections
Claims 4, 8, and 13 are objected to because of the following informalities:
Regarding claim 4, it recites “the channel” in line 2, it appears it should read “the channel region”, or another appropriate correction is required.
Regarding claim 8, it recites “the gate” in line 1, it appears it should read “the gate contact layer”, or another appropriate correction is required.
Regarding claim 13, it recites “the gate” in line 1, it appears it should read “the gate contact layer”, or another appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, it recites the limitation "the GAA transistor" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of compact prosecution, the Examiner interprets the claim to mean “The GAA transistor structure of claim 9, further comprising a plurality of device regions, wherein the plurality of device regions are laterally spaced”, in which case proper antecedent basis is established.
Regarding claim 11, it recites the limitation "the GAA transistor" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of compact prosecution, the Examiner interprets the claim to mean “The GAA transistor structure of claim 9, further comprising a plurality of device regions, wherein the plurality of device regions are vertically stacked”, in which case proper antecedent basis is established.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210091207 A1, hereafter Yu) in view of Chung et al (US 20220037497 A1, hereafter Chung).
Regarding claim 1, Yu teaches: A transistor structure (Yu 100, fig 1, 14, 17A, 17B) comprising:
a stack of layers (Yu 101, fig 1, 14) including:
a source contact layer (Yu 106a, 1704, ¶0039, at least in contact with source-drain regions 1302),
a gate contact layer (Yu 1406, 110a, ¶0082) with a first insulation layer (108a, ¶0042, 0043, 0068, comprised of insulator materials “silicon nitride … silicon dioxide”) between the gate contact layer and the source contact layer (Yu fig 1, 14, 17A, 17B), and
a drain contact layer (Yu 106b, 1704, ¶0039, at least in contact with source-drain regions 1302) with a second insulation layer (Yu 108b, ¶0042, 0043, 0068, comprised of insulator materials “silicon nitride … silicon dioxide”) between the gate contact layer and the drain contact layer (Yu fig 1, 14, 17A, 17B);
a device region (Yu VFET1, 304, 1302, ¶0081, under a broadest reasonable interpretation (BRI), VFET1 contains a source and a drain separated by a channel, see applicant spec ¶0006) orthogonal to a plane defined by a surface of at least one of the layers in the stack of layers (VFET1 has a major axis that is at least oriented orthogonal to a horizontal surface of 108a, with regard to Yu figs 1, 14, and/or 17), the device region comprising a source (Yu 1302, ¶0077, bottom 1302 fig 17A, “source-drain regions” is at least capable of being a source) and drain (Yu 1302, ¶0077, top 1302 fig 17A, “source-drain regions” is at least capable of being a drain) separated by a channel region (Yu 304, ¶0081)(Yu fig 14).
Yu does not teach: silicide regions at ends of the device region proximal to the source and drain.
Yu further teaches: metal contacts (Yu 1704) corresponding to the source and drain (Yu 1302)(Yu ¶0091-0092, fig 17A, 17B), at ends of the device region (Yu VFET1, 304, 1302) proximal to the source and drain (at least top and bottom with regard to Yu fig 17B).
Chung, in the same field of endeavor of semiconductor device manufacturing, teaches: silicide layers (Chung 240) at an interface between a first metal contact (Chung 236, ¶0040) and a source (Chung 228S) and an interface between a second metal contact (Chung 234, ¶0040) and a drain (Chung 228D)(Chung ¶0040, fig 12B, 12C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silicide layers of Chung between the source and drain and respective metal contacts of Yu, such that “silicide regions at ends of the device region proximal to the source and drain”, in order to reduce contact resistance between the source and drain and their respective metal contacts (Chung ¶0040).
Regarding claim 2, Yu in view of Chung teaches: The transistor structure of claim 1 wherein the gate contact layer (Yu 1406, 110a, ¶0082) at least partially surrounds the channel region (Yu 304, ¶0081) with a gate dielectric (Yu 1206, 1202, ¶0076, 0087) interposed between the gate contact layer and the channel region (Yu fig 13, 14, 17B).
Regarding claim 4, Yu in view of Chung teaches: The transistor structure of claim 1 wherein each one of the source (Yu 1302, ¶0077, bottom 1302 fig 17A), the drain (Yu 1302, ¶0077, top 1302 fig 17A), and the channel (as best understood to mean “the channel region”, Yu 304, ¶0081) are at least partially surrounded by one or more dielectric materials (Yu 1702, 1102, 108a, 108b, 1206)(Yu fig 17A).
Regarding claim 5, Yu in view of Chung teaches: The transistor structure of claim 1, comprising:
a first silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of top 1302 and 1704 fig 17A) at a first end of the device region in electrical contact with the source (Yu 1302, ¶0077, bottom 1302 fig 17A)(Yu ¶0091, Chung ¶0040) and a second silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of top 1302 and 1704 fig 17A) at a second end of the device region in electrical contact with the drain (Yu 1302, ¶0077, top 1302 fig 17A)(Yu ¶0091, Chung ¶0040).
Examiner’s note: Yu is modified to include the silicide layer 240 of Chung between and adjacent to the metal contacts 1704 of Yu and the source/drain 1302 of Yu to reduce the contact resistance, therefore the silicide regions and source and drain are at least in electrical contact. Further, the source and drain are located at opposite vertical ends of the device region of Yu.
Regarding claim 6, Yu in view of Chung teaches: The transistor structure of claim 1, comprising a hollow core (Yu 1010, 1102) extending orthogonally through a central portion (vertical center with regard to Yu fig 10A, best shown by 304)(Yu fig 10B) of the device region (Yu VFET1), wherein the hollow core comprises one of air or dielectric material (Yu 1102, ¶0037, 0070 “silicon oxide”, ¶0073).
Regarding claim 7, Yu in view of Chung teaches: The transistor structure of claim 1, wherein the source contact layer (Yu 106a, 1704) is in electrical contact with the source (Yu 1302, bottom 1302 fig 17A) via a first silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of bottom 1302 and 1704 fig 17A) of the silicide regions (Yu as modified to include Chung 240) and the drain contact layer (Yu 106b, 1704) is in electrical contact with the drain (Yu 1302, top 1302 fig 17A) via a second silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of top 1302 and 1704 fig 17A) of the silicide regions (Yu as modified to include Chung 240).
Regarding claim 8, Yu in view of Chung teaches: The transistor structure of claim 7, wherein the source (Yu 1302, top 1302 fig 17A), the gate (as best understood to mean “the gate contact layer”)(Yu 1406, 110a) and the drain (Yu 1302, top 1302 fig 17A) are vertically aligned and orthogonal to the plane (Yu fig 17A).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210091207 A1, hereafter Yu) in view of Chung et al (US 20220037497 A1, hereafter Chung), as applied to claim 1, and further in view of Jacob (US 9831131 B1).
Regarding claim 3, Yu in view of Chung teaches: The transistor structure of claim 1.
Yu in view of Chung does not teach: wherein the gate contact layer forms a ring around the channel region with a gate dielectric interposed between the gate contact layer and the channel region.
Jacob, in the same field of endeavor of semiconductor device manufacturing, teaches: A gate all around (GAA) transistor structure (Jacob fig 1U, 1L, Col 1, Lines 22-25, Col 6, Line 64, fig 1AG, 131) comprising:
a device region comprising a plurality of nanowires (Jacob 131, fig 1B, 121, 131, Jacob shows a mask configuration 121 for forming plurality of nanowires 131), and
wherein a gate contact layer (Jacob 149, 145) forms a ring around a channel region (Jacob 105) with a gate dielectric (Jacob 151, 143) interposed between the gate contact layer and the channel region (Jacob figs 1J-N, 1B, Col 6, Lines 52-65, Jacob shows a mask configuration 121 for forming plurality of nanowires 131 conformally covered by 143 and 145, thereby forming a ring around 105).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu in view of Chung to use a nanowire structure instead of a trench structure, such that “the gate contact layer forms a ring around the channel region with a gate dielectric interposed between the gate contact layer and the channel region”, in order to increase performance and/or transistor density (Jacob Col5, Lines 40-43).
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20210091207 A1, hereafter Yu) in view of Chung et al (US 20220037497 A1, hereafter Chung) and Jacob (US 9831131 B1).
Regarding claim 9, Yu teaches: A transistor structure (Yu 100, fig 1, 14, 17A, 17B) comprising:
a substrate (Yu 102);
a stack of layers (Yu 101, fig 1, 14) upon the substrate (Yu fig 1, 14), the stack of layers including:
a source contact layer (Yu 106a, 1704, Yu 106a, 1704, ¶0039, at least in contact with source-drain regions 1302),
a gate contact layer (Yu 1406, 110a, ¶0082) with a first insulation layer (Yu 108a, ¶0042, 0043, 0068, comprised of insulator materials “silicon nitride … silicon dioxide”) between the gate contact layer and the source contact layer (Yu fig 1, 14, 17A, 17B), and
a drain contact layer (Yu 106b, 1704, ¶0039, at least in contact with source-drain regions 1302) with a second insulation layer (Yu 108b, ¶0042, 0043, 0068, comprised of insulator materials “silicon nitride … silicon dioxide”) between the gate contact layer and the drain contact layer (Yu fig 1, 14, 17A, 17B);
a device region (Yu VFET1, 304, 1302, ¶0081, under a broadest reasonable interpretation (BRI), VFET1 contains a source and a drain separated by a channel, see applicant spec ¶0006) orthogonal to a plane defined by a surface of at least one of the layers in the stack of layers (VFET1 has a major axis that is at least oriented orthogonal to a horizontal surface of 108a, with regard to Yu figs 1, 14, and/or 17), the device region comprising a source (Yu 1302, ¶0077, bottom 1302 fig 17A, “source-drain regions” is at least capable of being a source) and drain (Yu 1302, ¶0077, top 1302 fig 17A, “source-drain regions” is at least capable of being a drain) separated by a channel region (Yu 304, ¶0081)(Yu fig 14) that is at least partially surrounded by a gate dielectric (Yu 1206, 1202, ¶0076, 0087) interposed between the gate contact layer and the channel region (Yu fig 13, 14, 17B); and
a first end of the device region is the source and a second region at a second end of the device region is the drain (Yu fig 17A).
Yu does not teach: a first region comprising a silicide formed at a first end of the device region proximal to the source and a second region comprising the silicide formed at a second end of the device region proximal to the drain.
Yu further teaches: metal contacts (Yu 1704) corresponding to a source (Yu bottom 1302 with regard to fig 17A) and a drain (Yu top 1304 with regard to fig 17A)(Yu ¶0091-0092, fig 17A, 17B).
Chung, in the same field of endeavor of semiconductor device manufacturing, teaches: silicide layers (Chung 240) at an interface between a first metal contact (Chung 236, ¶0040) and a source (Chung 228S) and an interface between a second metal contact (Chung 234, ¶0040) and a drain (Chung 228D)(Chung ¶0040, fig 12B, 12C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the silicide layers of Chung between and in contact with the source and drain and their respective metal contacts of Yu, such that “a first region comprising a silicide formed at a first end of the device region proximal to the source and a second region comprising the silicide formed at a second end of the device region proximal to the drain”, in order to reduce contact resistance between the source and drain and their respective metal contacts (Chung ¶0040).
Yu in view of Chung does not explicitly teach: A gate all around (GAA) transistor structure.
Yu in view of Chung further teaches: a trench (202).
Jacob, in the same field of endeavor of semiconductor device manufacturing, teaches: A gate all around (GAA) transistor structure (Jacob fig 1U, 1L, Col 1, Lines 22-25, Col 6, Line 64, fig 1AG, 131) comprising:
a stack of layers (Jacob fig 1A, 1AG, 101, 111, 119) upon the substrate (Jacob fig 1A), and
a device region comprising a plurality of nanowires (Jacob 131, fig 1B, 121, 131, Jacob shows a mask configuration 121 for forming plurality of nanowires 131).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Yu in view of Chung to use a nanowire structure instead of a trench structure in order to increase performance and/or transistor density (Jacob Col5, Lines 40-43).
Regarding claim 10, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, wherein the GAA transistor is laterally spaced from an additional GAA transistor structure (as best understood to mean “The GAA transistor structure of claim 9, further comprising a plurality of device regions, wherein the plurality of device regions are laterally spaced”)(Jacob fig 1B, 121, 131, Jacob shows a mask configuration 121 for forming plurality of nanowires 131, comprising the device region, arranged laterally spaced in at least one direction).
Regarding claim 11, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, wherein the GAA transistor is vertically stacked over an additional GAA transistor structure (as best understood to mean “The GAA transistor structure of claim 9, further comprising a plurality of device regions, wherein the plurality of device regions are vertically stacked”)(Yu fig 1, 17A, VFET1 and VFET2 are stacked vertically).
Regarding claim 12, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, wherein the source contact layer (Yu 106a, 1704) is in electrical contact with the source (Yu 1302, bottom 1302 fig 17A) via the first region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of bottom 1302 and 1704 fig 17A) and the drain contact layer (Yu 106b, 1704) is in electrical contact with the drain (Yu 1302, top 1302 fig 17A) via the second region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of top 1302 and 1704 fig 17A)(Yu ¶0091, Chung ¶0040).
Examiner’s note: Yu is modified to include the silicide layer 240 of Chung between and adjacent to the metal contacts 1704 of Yu and the source/drain 1302 of Yu to reduce the contact resistance, therefore the source and drain contact layers are in electrical contact with the source and drain via the silicide first and second regions respectively.
Regarding claim 13, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, wherein the source (Yu 1302, bottom 1302 fig 17A), the gate (as best understood to mean “the gate contact layer”)(Yu 1406, 110a) and the drain (Yu 1302, top 1302 fig 17A) are vertically aligned and orthogonal to the plane (horizontally with regard to fig 17A)(Yu fig 17A).
Regarding claim 14, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, comprising a hollow core (Yu 1010, 1102) extending orthogonally through a central portion (vertical center with regard to Yu fig 10A, best shown by 304)(Yu fig 10B) of the device region (Yu VFET1), wherein the hollow core comprises one of air or dielectric material (Yu 1102, ¶0037, 0070 “silicon oxide”, ¶0073).
Regarding claim 15, Yu in view of Chung and Jacob teaches: The GAA transistor structure of claim 9, wherein the source contact layer (Yu 106a, 1704) is in electrical contact with the source (Yu 1302, bottom 1302 fig 17A) via a first silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of bottom 1302 and 1704 fig 17A) of the silicide regions () and the drain contact layer (Yu 106b, 1704) is in electrical contact with the drain (Yu 1302, top 1302 fig 17A) via a second silicide region (Yu as modified to include Chung 240 between 1302 and 1704, inclusive of top 1302 and 1704 fig 17A) of the silicide regions (Yu as modified to include Chung 240).
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818