DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
3. Applicant’s election without traverse of Group I Species A, identified as encompassing claims 1-17 and 21-24 is acknowledged.
Upon detailed consideration, the newly added claims 21-24 are directed towards non-elected species having at least “a first channel region comprising a plurality of horizontally stacked nanostructures” and “a second channel region comprising a plurality of horizontally stacked nanostructures” as seen in Species C and E.
Therefore, claims 21-24 are also withdrawn as directed towards non-elected species.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-2, 6-8, and 10-11 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lilak et al. (US 2020/0294998 A1), hereinafter as L1
5. Regarding Claim 1, L1 discloses a method (see in particular Fig. 1A), comprising:
forming a first transistor (first transistor of element 104 comprising elements 116A, 122A, 120A, see [0013]) of a first semiconductor device (lower device below element 106 comprising element 104, see [0013] “lower device region 104”), the forming the first transistor including:
forming a first channel region (region of element 116A and [0013] “the channel regions of the fin structure have been processed into nanowires”); and
forming a first gate electrode (element 120A, see [0013] “gate electrode 102A”) on the first channel region;
bonding a second semiconductor device (upper device above element 106 comprising element 108, see [0013] “upper device region 108”) to the first semiconductor device by forming a first bonding layer (element 106, see [0013] “isolation region” and see Fig. 1A) between the first and second semiconductor devices; and
forming a second transistor (second transistor of element 108, comprising elements 116B, 122B, 120B, see [0013]) of the second semiconductor device, the forming the second transistor including:
forming a second channel region (region of element 116B, see [0013]); and
forming a second gate electrode (region of element 120B, see [0013]) on the second channel region,
wherein the first bonding layer is disposed between the first gate electrode of the first transistor and the second gate electrode of the second transistor (see Fig. 1A).
6. Regarding Claim 2, L1 discloses the method of claim 1, wherein forming the first channel region includes forming the first channel region having a first electrical conductivity type (see [0015] “p-type devices in the upper fin portions and n-type devices in the lower fin portions, or vice-versa”), and wherein forming the second channel region includes forming the second channel region having a second electrical conductivity type that is different than the first electrically conductive type (see [0015]).
7. Regarding Claim 6, L1 discloses the method of claim 1,
further comprising:
forming a second bonding layer (see [0018] “Insulator 127A-B adjacent isolation 106 can be any suitable insulator material, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, a polymer, a porous version of any of these, or any combination of these (e.g., upper portion of silicon oxide and a lower portion of silicon nitride, or vice-versa). In some embodiments, isolation 106 and insulator 127A-B are the same material” Elements 106 and 127A-B are selected to be same material and a combination of at least first bonding layer silicon dioxide and second bonding layer silicon nitride) on the second transistor (on the bottom surface of the second transistor); and bonding the first bonding layer to the second bonding layer (both layers are bonded at element 106), wherein the forming the second transistor includes forming the second transistor subsequent to the bonding the first bonding layer to the second bonding layer (see [0027] “the stacked device layers can be formed through fabrication involving a single fin structure that includes an isolation region 106 between the upper device region 108 and the lower device region 104 (such as the examples shown in FIGS. 2A-F). In other examples, the stacked device layers can be formed through separate fabrication of device layers that are stacked and bonded together using a bonding material, to provide a monolithic structure”; note, the second transistor is not fully formed until at least the conductive interconnects are formed to complete the second transistor by forming the frontside contact region element 105, see [0029])
8. Regarding Claim 7, L1 discloses the method of claim 6, wherein forming the first bonding layer and forming the second bonding layer includes forming the first bonding layer and the second bonding layer including at least one of: SiO, SiOC, SiOCN, SiN, SION, AIN, BN, SiC, diamond, or BeO (see [0018] “Insulator 127A-B adjacent isolation 106 can be any suitable insulator material, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, a polymer, a porous version of any of these, or any combination of these (e.g., upper portion of silicon oxide and a lower portion of silicon nitride, or vice-versa). In some embodiments, isolation 106 and insulator 127A-B are the same material” Elements 106 and 127A-B are selected to be same material and a combination of at least first bonding layer silicon dioxide and second bonding layer silicon nitride).
9. Regarding Claim 8, L1 discloses the method of claim 6, wherein forming the first bonding layer and forming the second bonding layer includes forming at least one of the first bonding layer or the second bonding layer having a thickness that is less than 50 nm (see [0036] “The fin structures may have any number of geometries, but in some example cases are 50 nm to 250 nm tall” See Figs. 1A-2F The element 106 is much thinner than the height of the fin such that when the fin is for example 50 nm, the first and second bonding layers are at least less than 50 nm; See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
[Thomas et al. (US 2023/0037957 A1), hereinafter as T1 is utilized herein as evidence]
10. Regarding Claim 10, L1 discloses a method (see in particular Fig. 1A), comprising:
forming a first semiconductor device (lower device below element 106 comprising element 104, see [0013] “lower device region 104”) on or in a first substrate (semiconductor material of the lower device element; see evidentiary reference T1 Figs. 2-5 the semiconductor material of the stacked devices can be considered a substrate for which the Examiner is interpreting the portion of the lower device is a first substrate and the portion of the upper device is a second substrate in which the devices are formed), the forming the first semiconductor device including:
forming a first channel region (region of element 116A and [0013] “the channel regions of the fin structure have been processed into nanowires”);
forming a first gate electrode (element 120A, see [0013] “gate electrode 102A”) overlying the first channel region; and
forming a first source/drain region (element 124A, see [0013] “source and drain regions 124A”) in contact with the first channel region, the first source/drain region adjacent to the first channel region along a first direction (lateral direction in the cross-sectional view of Fig. 1A);
forming a first bonding layer (see [0018] “Insulator 127A-B adjacent isolation 106 can be any suitable insulator material, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, a polymer, a porous version of any of these, or any combination of these (e.g., upper portion of silicon oxide and a lower portion of silicon nitride, or vice-versa). In some embodiments, isolation 106 and insulator 127A-B are the same material” Elements 106 and 127A-B are selected to be same material and a combination of at least first bonding layer silicon dioxide and second bonding layer silicon nitride) on the first semiconductor device;
forming a second bonding layer (see [0018] “Insulator 127A-B adjacent isolation 106 can be any suitable insulator material, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, a polymer, a porous version of any of these, or any combination of these (e.g., upper portion of silicon oxide and a lower portion of silicon nitride, or vice-versa). In some embodiments, isolation 106 and insulator 127A-B are the same material” Elements 106 and 127A-B are selected to be same material and a combination of at least first bonding layer silicon dioxide and second bonding layer silicon nitride) on a second substrate (semiconductor material of the lower device element; see evidentiary reference T1 Figs. 2-5 the semiconductor material of the stacked devices can be considered a substrate for which the Examiner is interpreting the portion of the lower device is a first substrate and the portion of the upper device is a second substrate in which the devices are formed);
bonding the first bonding layer and the second bonding layer to one another (both layers are bonded at element 106); and
forming a second semiconductor device (upper device above element 106 comprising element 108, see [0013] “upper device region 108”) on or in the second substrate, the forming the second semiconductor device including:
forming a second channel region (region of element 116B, see [0013]);
forming a second gate electrode (region of element 120B, see [0013]) overlying the second channel region (see Fig. 1A); and
forming a second source/drain region (elements 124B, see [0013] “source/drain regions 124B”) in contact with the second channel region (see Fig. 1A), the second source/drain region adjacent to the second channel region along the first direction (see Fig. 1A).
11. Regarding Claim 11, L1 discloses the method of claim 10, wherein forming the first channel region includes forming the first channel region having a first electrically conductive type (see [0015] “p-type devices in the upper fin portions and n-type devices in the lower fin portions, or vice-versa”), and forming the second channel region includes forming the second channel region having a second electrically conductive type that is different than the first electrically conductive type (see [0015] “p-type devices in the upper fin portions and n-type devices in the lower fin portions, or vice-versa”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2020/0294998 A1), hereinafter as L1, in view of Ching et al. (US 2020/0091312 A1), hereinafter as C1
13. Regarding Claim 4, L1 discloses the method of claim 1, wherein forming one of the first transistor or the second transistor includes forming an epitaxial source/drain region by epitaxial growth (see [0022] “the source/drain regions are epitaxial source/drain regions”).
L1 does not explicitly disclose the epitaxial growth is from one of the first channel region or the second channel region, at least one void being disposed between the first bonding layer and the epitaxial source/drain region.
C1 discloses the epitaxial growth is from one of the first channel region or the second channel region (see [0003] “in FINFET fabrication processes, it is typical to epitaxially grow some semiconductor materials over semiconductor fins as S/D features, referred to as EPI S/D features”), at least one void being disposed at a bottom of the epitaxial source/drain region (see [0003] “When the spacing is large, cavities might be introduced at the bottom of an S/D contact that straddles over multiple EPI S/D features.”).
The epitaxial growth from the fin structure and at least one void as taught by C1 is incorporated as epitaxial growth from the fin structure and at least one void of L1, wherein the combination further discloses at least one void being disposed between the first bonding layer and the epitaxial source/drain region (see L1 Fig. 1A the bottom of the epitaxial source/drain region is above the first bonding layer).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of C1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known method of forming a source/drain region in a similar device to obtain predictable results (see C1 [0003]).
14. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2020/0294998 A1), hereinafter as L1, in view of Smith et al. (US 2019/0172751 A1), hereinafter as S1
15. Regarding Claim 5, L1 discloses the method of claim 1.
L1 does not explicitly disclose wherein forming the second channel region includes forming the second channel region of a different material than the first channel region, and wherein forming the first channel region includes forming a silicon germanium region, and forming the second channel region includes forming a silicon region.
S1 discloses (see Figs. 8-11) wherein forming the second channel region (region of element 809’, see [0051-0052] “channel material 809” “channel material 809’”) includes forming the second channel region of a different material than the first channel region (region of element 805, see [0052] “channel material 805”) (see Fig. 10 second channel is Si, silicon, and first channel region is SiGe, silicon germanium), and wherein forming the first channel region includes forming a silicon germanium region, and forming the second channel region includes forming a silicon region (see Fig. 10).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with L1 because the combination allows for adjusted channel material and associated electrical properties of the respective upper and lower devices which are different conductivity types; and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material of upper and lower device channel layers for another in a similar device for which the alternatives are provided as selectable (see S1 Fig. 6 versus Fig. 10).
16. Regarding Claim 14, L1 discloses the method of claim 10.
L1 does not disclose wherein forming the first channel region and forming the second channel region includes forming the first channel region and the second channel region of different materials.
S1 discloses (see Figs. 8-11) wherein forming the first channel region and forming the second channel region includes forming the first channel region and the second channel region of different materials (see Fig. 10 second channel is Si, silicon, and first channel region is SiGe, silicon germanium).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with L1 because the combination allows for adjusted channel material and associated electrical properties of the respective upper and lower devices which are different conductivity types; and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known material of upper and lower device channel layers for another in a similar device for which the alternatives are provided as selectable (see S1 Fig. 6 versus Fig. 10).
17. Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2020/0294998 A1), hereinafter as L1, in view of Yin et al. (CN 112687626 A1, see attached translation document), hereinafter as Y1
18. Regarding Claims 9, L1 discloses the method of claim 1.
L1 does not disclose wherein forming the first channel region includes forming the first channel region having a first lattice plane orientation, and forming the second channel region includes forming the second channel region having a second lattice plane orientation that is different than the first lattice plane orientation.
Y1 discloses wherein forming the first channel region includes forming the first channel region having a first lattice plane orientation, and forming the second channel region includes forming the second channel region having a second lattice plane orientation that is different than the first lattice plane orientation (see pg. 3 “the complementary surrounding gate device (Gate-All-Around, GAA) structure composed of n, p vertical stack, NFET and PFET can adopt different crystal orientation, different channel material, to optimize nFET and pFET carrier mobility” The different crystal orientation results in a different lattice plane orientation).
The different crystal orientation and resulting lattice plane orientation as taught by Y1 is incorporated as a different crystal orientation and resulting lattice plane orientation of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with L1 because the combination allows for carrier mobility optimization with respect to each of the n-type versus p-type channel transistors (see Y1 pgs. 2-3); furthermore the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known crystal orientation and plane orientation of one n-type and p-type gate-all-around FET device for another to obtain predictable results (see Y1 pgs. 2-3; furthermore, note that the lattice planes have only two options of being the same or being different).
19. Regarding Claim 15, L1 discloses the method of claim 10.
L1 does not disclose wherein forming the first channel region includes forming the first channel region having a first lattice plane orientation, and forming the second channel region includes forming the second channel region having a second lattice plane orientation that is different than the first lattice plane orientation.
Y1 discloses wherein forming the first channel region includes forming the first channel region having a first lattice plane orientation, and forming the second channel region includes forming the second channel region having a second lattice plane orientation that is different than the first lattice plane orientation (see pg. 3 “the complementary surrounding gate device (Gate-All-Around, GAA) structure composed of n, p vertical stack, NFET and PFET can adopt different crystal orientation, different channel material, to optimize nFET and pFET carrier mobility” The different crystal orientation results in a different lattice plane orientation).
The different crystal orientation and resulting lattice plane orientation as taught by Y1 is incorporated as a different crystal orientation and resulting lattice plane orientation of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with L1 because the combination allows for carrier mobility optimization with respect to each of the n-type versus p-type channel transistors (see Y1 pgs. 2-3); furthermore the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known crystal orientation and plane orientation of one n-type and p-type gate-all-around FET device for another to obtain predictable results (see Y1 pgs. 2-3; furthermore, note that the lattice planes have only two options of being the same or being different).
20. Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2020/0294998 A1), hereinafter as L1, in view of Huang et al. (US 2022/0199624 A1), hereinafter as H1
21. Regarding Claim 16, L1 discloses the method of claim 10.
L1 does not explicitly disclose further comprising: forming an electrically conductive via extending from the first source/drain region to the second source/drain region.
H1 discloses further comprising: forming an electrically conductive via extending from the first source/drain region to the second source/drain region (see [0082] “The second interconnect is coupled to the second of both the first and second pairs of source and drain regions in each memory cell of the column.”).
The source drain/drain region connection between the first source/drain and the second source/drain region as taught by H1 is incorporated as a source drain/drain region connection between the first source/drain and the second source/drain region of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known source/drain connection for another in a similar device for which alternatives are provided as selectable (see H1 [0076-0096] which provide alternative conductive connection to the source/drain regions of the stacked semiconductor devices are provided as alternatively selectable examples).
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818