DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the film stack" in line 16 of page 2. There is insufficient antecedent basis for this limitation in the claim.
With regards to claim 6, the limitation of “ wherein the first spacer sandwiched between the first free layer and the second free layer is removed and then the memory device further comprises a free layer pair structure is unclear. If the memory device requires the first spacer layer in the independent claim and claim 6 removes it appears the device is contradictory. Is the spacer layer required to make the device or isn’t it? Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3,8-10,12,13,& 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ying (US Pub no. 2021/0036055 A1) in view of Mihajkovic (US Patent 10,777,248 A1).
Regarding claim 1, Ying et al discloses A memory device, comprising:
a substrate(110)[0028]; a reference layer (250)disposed on the substrate(110)[0046-0047] fig. 4; a tunneling layer(260) disposed on the reference layer(250)[0046-0047]; a first film stack(270) formed over the tunneling layer (260)and on the substrate(110) [0046-0047] fig. 3h/fig. 4, wherein the first film stack(270) comprises a first free layer(270- Fe-B), a first spacer ( MgO of 270) and a second free layer(Co-Fe-B of 270)[0047], the first free layer (270- Fe-B)is in contact with the tunneling layer (260)and [0046-0047], the first spacer ( MgO or Mg of 270) is sandwiched between the first free layer(270- Fe-B) and the second free layer(Co-Fe-B of 270)[0047]; and a capping layer (280)disposed on and electrically connected to the film stack(170)[0047] fig. 4.
Ying et al fails to teach a second film stack formed over the first film stack, wherein the second film stack comprises a third free layer, a second spacer, and a fourth free layer, wherein the third free layer is sandwiched between the second free layer and the second spacer and each of the first spacer and the second spacer is a material comprising metal elements with relatively low atomic weight, selected from one of magnesium (Mg), aluminum (Al), silicon (Si), calcium (Ca), cobalt (Co) and nickel (Ni).
However, Mihajlovic et al discloses a MRAM memory cell comprising a second film stack(312/316/314) formed over the first film stack(302/306/304), wherein the second film stack comprises a third free layer(312), a second spacer(316), and a fourth free layer(314), wherein the third free layer(312) is sandwiched between the second free layer(304) and the second spacer(316) and each of the first spacer (306)(col. 10, lines 34-35)and the second spacer (316) is a material comprising metal elements with relatively low atomic weight, selected from one of magnesium (Mg), aluminum (Al), silicon (Si)(col, 8, lines 32-34). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify YIng et al with the teachings of Mihajkovic et al to provide a configuration that remains stable in the quiescent state and/or during a read operation at sufficiently low read current.
Regarding claim 2, Ying et al discloses wherein the first spacer is a material including Mg[0047].
Regarding claim 3, Ying et al discloses wherein the thickness of the first spacer(Mg or MgO) in the first film stack (270)is between 0.2 nm to 0.4 nm[0047].
Regarding claim 8, Mihajlovic et al discloses wherein the memory device further forms a repeated structure of the film stacks (302/306/304/268/312/314), wherein the thickness of the spacer is smaller than the thickness of the first free layer(col. 10, lines 38-45(col. 8, lines 32-39)).
Regarding claim 9, Mihajlovic et al discloses another film stack formed over the second film stack(312/316/314) (col. 10, lines 46-59)
Regarding claim 10, Ying et al discloses wherein the width of the first free
layer(270- Fe-B) is substantially larger than the width of the second free layer(Co-Fe-B of 270) fig. 4(Examine notes since the structure 270 has slanted sides , the second free layer width will have a smaller width than the first free layer).
Regarding claim 12, Ying et al discloses further comprises:
an auxiliary line(SHEL(n)) [0050], disposed on the capping layer(280); and
a selector(S(m.n)), disposed on the auxiliary line(SHEL(n) ) and electrically connected to a bit line(Bl(m)) and the film stack(270), wherein the selector(S(m.n)) is one of threshold-type selector and exponential type selector[0022] fig. 4.
Regarding claim 13, Ying et al discloses further comprising:
a buffer layer (210)located on top of the substrate(110)[0046]; and
a seed layer(220) located in between the buffer layer(210) and the reference layer(250)[0046].
Regarding claim 14, Ying et al discloses further comprising:
a buffer layer(210) located on top of the substrate(110) [0046] fig. 4/fig. 3h; and
a seed layer(220) located in between the buffer layer (210)and the spacer ( MgO or Mg of 270) [0047].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ying (US Pub no. 2021/0036055 A1) in view of Mihajkovic (US Patent 10,777,248 A1) as applied to claim 1 and further in view of Yamane (US Pub no. 2018/0123027 A1)
Regarding claim 4, Ying et al as modified by Mihajkovic et al discloses all the claim limitations of claim 1 but fails to teach wherein the thickness of the first free layer in the first film stack is between 0.2 nm to 0.5 nm.
Yamane et al teaches a thickness of a metal coupling layer (spacer)between 0.05 nm to 1 [0067] but fails to teach between 0.2 nm to 0.5 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a thickness between 0.2 nm to 0.4 nm through routine experimentation. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ying (US Pub no. 2021/0036055 A1) in view of Mihajkovic (US Patent 10,777,248 A1) and Yamane (US Pub no. 2018/0123027 A1)as applied to claim 4 and further in view of Smith (US Pub no. 2019/0386209 A1).
Regarding claim 5, Ying et al as modified by Mihajkovic and Yamane et al discloses the first film stack(270-Ying et al ) but fails to teach the thickness of the film stack is smaller than or equal to 1 nm.
Smith et al discloses a thickness of free magnetic layer (105) intervening metal
coupling layer (202) and second free magnetic layer (205) having a thickness [0035]but fails to teach smaller than or equal to 1 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve a
thickness smaller than or equal to 1 nm through routine experimentation. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art"
a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ying et al , Mihajkovic and Yamane et al with the teaching of Smith et al to increase the overall interfacial perpendicular
anisotropy.
Claim(s) 6, 7, & 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ying (US Pub no. 2021/0036055 A1) in view of Mihajkovic (US Patent 10,777,248 A1) as applied to claim 1 and further in view of Gosavi (US Pub no. 2019/0386205 A1).
Regarding claim 6, Ying et al as modified by Mihajkovic et al discloses all the claim limitations of claim 1 but fails to teach wherein the spacer sandwiched between the first free layer and the second free layer is removed and then the memory device further comprises a free layer pair structure.
Gosavi et al teaches removing the spacer sandwiched between the first free
layer and the second free layer[0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Ying et al and Mihajkovic et al with the teachings of Gosavi et al since a particular known technique was recognized as part of the ordinary capabilities of one skilled in the
art. One of ordinary skill in the art would have been capable of applying this known
technique to a known device (method, or product) that was ready for improvement and
the results would have been predictable to one of ordinary skill in the art. In re
Nilssen, 851 F.2d 1401, 7 USPQ2d 1500 (Fed. Cir. 1988)
Regarding claim 7, Gosavi et al discloses wherein the memory device forms a repeated free layer pair structure(221a/c), and wherein the thickness of the first free layer is substantially the same as the thickness of the second free layer[0066][0114]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Ying et al and Mihajkovic et al with the teachings of Gosavi et al to optimize magnetization direction to the plane of the magnetic layer.
Regarding claim 11, Gosavi et al discloses wherein both the first free
layer (821aa)and the second free layer (821ab)have a plurality of monolayers[0114].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Pub no. 2020/0006425 A1) in view of Mihajkovic (US Patent 10,777,248 A1).
Regarding claim 15, Lin et al discloses A method of fabricating a memory device, comprising: providing a plurality of transistors(410) disposed on a substrate(406)[0039] ;
forming a plurality of conductive vias (446)electrically coupled to the plurality of transistors(410) [0040]; forming a buffer layer(108), a seed layer(110) and a hard-biasing layer (111)sequentially on a substrate(1406) [0017][0039][0041]; forming a reference layer(113) disposed on the hard-biasing layer(111) [0017][0041], wherein the seed layer(110) and the reference layer (113)are in physical contact with opposing surfaces of the hard-biasing layer(111)[0017] [0041](APC layer is optional therefore physical contact results) , respectively; forming a tunneling layer(114) disposed on the reference layer(113)[0041];
forming a free layer (115) formed over the tunneling layer(114) and on the substrate(406) fig. 4[0017][0041], forming a capping layer(117) disposed on and electrically connected to the free layer (115); and forming a connecting via (442)disposed on and electrically connected to the free layer (115) fig. 4.
Lin et al fails to teach forming a film stack formed over the tunneling layer and on the substrate, wherein the film stack comprises a first free layer, a spacer and a
second free layer, the first free layer is in contact with the tunneling layer the spacer is sandwiched between the first free layer and the second free layer.
However, Mihajkovic et al discloses forming a film stack formed over the tunneling layer (264)and on the substrate, wherein the film stack comprises a first free layer(262), a spacer (268)and a second free layer,(266) the first free layer(262) is in contact with the tunneling layer (264)the spacer(268) is sandwiched between the first free layer (262)and the second free layer(266) (col. 8, lines 32-39). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lin et al with the teachings of Mihajkovic et al to provide a configuration that remains stable in the quiescent state and/or during a read operation at sufficiently low read current.
Regarding claim 18, Mihajkovic et al discloses further comprising: forming a repeated film stack structure(302/306/304/268/312/314), wherein the thickness of the spacer is smaller than the thickness of the first free layer(col. 10, lines 38-45(col. 8, lines 32-39)).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Pub no. 2020/0006425 A1) in view of Gosavi (US Pub no. 2019/0386205 A1).
Regarding claim 15, Lin et al discloses A method of fabricating a memory device, comprising: providing a plurality of transistors(410) disposed on a substrate(406)[0039] ;
forming a plurality of conductive vias (446)electrically coupled to the plurality of transistors(410) [0040]; forming a buffer layer(108), a seed layer(110) and a hard-biasing layer (111)sequentially on a substrate(1406) [0017][0039][0041]; forming a reference layer(113) disposed on the hard-biasing layer(111) [0017][0041], wherein the seed layer(110) and the reference layer (113)are in physical contact with opposing surfaces of the hard-biasing layer(111)[0017] [0041](APC layer is optional therefore physical contact results) , respectively; forming a tunneling layer(114) disposed on the reference layer(113)[0041];
forming a free layer (115) formed over the tunneling layer(114) and on the substrate(406) fig. 4[0017][0041], forming a capping layer(117) disposed on and electrically connected to the free layer (115); and forming a connecting via (442)disposed on and electrically connected to the free layer (115) fig. 4.
Lin et al fails to teach forming a film stack formed over the tunneling layer and on the substrate, wherein the film stack comprises a first free layer, a spacer and a
second free layer, the first free layer is in contact with the tunneling layer the spacer is sandwiched between the first free layer and the second free layer.
However, Gosavi et al discloses a memory device comprising a film stack comprises a first free layer(321aa), a spacer (321ab)and a second free layer(321ac)[0078]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lin et al with the teachings of Gosavi et al such that forming a film stack formed over the tunneling layer and on the substrate, wherein the film stack comprises a first free layer, a spacer and a second free layer, the first free layer is in contact with the tunneling layer the spacer is sandwiched between the first free layer and the second free layer results in order to provide magnetization.
Regarding claim 16, Lin et al discloses (fig. 9) further comprising: wherein forming the free layer (115)is in contact with the tunneling layer (114)and the free layer(115), and wherein the free layer i(115)s patterned together as a pillar structure standing on the tunneling layer(114) so that sidewalls of the free layer are aligned[0040][0047-0048]; Gosavi et al discloses removing the spacer sandwiched between the first free layer and the second free layer, and providing a free layer pair structure[0031].
Regarding claim 17, Gosavi et al forming a repeated structure of a repeated free
layer pair structure, wherein the thickness of the first free layer and second free layer pair structure [0031] [(821aa/821ab)0114|bu fails to teach is smaller than or equal to 1
nm. It would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to achieve thickness smaller than or equal to 1 nm through routine experimentation. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In
re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d
1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 19-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the limitations of claim 19 including wherein the buffer layer, the seed layer, the film stack, the tunneling layer, the reference layer and the capping layer are sequentially stacked from bottom to top was not found in the prior art of record.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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