Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al., US 2013/0279234 in view of Shepard, US 2014/321190.
Shin et al. shows the invention substantially as claimed including a one-time programmable memory cell, comprising:
At least one first conductive gate element (for example, G) arranged in a semiconductor substrate (see, for example, paragraph 0039); and
At least a first channel portion in the semiconductor substrate and extending in parallel with at least one first lateral surface of the at least one first conductive gate element (see paragraph 0039 and note that it is a property of a channel that it will extend in parallel with the lateral surface of the gate element); and a capacitive element ANT_FS forming a memory element (see paragraph 0040); wherein said at least one first channel portion is coupled to an electrode of the capacitive element (see fig. 8, for example).
Shin et al. does not expressly disclose the conductive gate element arranged in a trench in the semiconductor substrate. Shepard discloses a conductive gate element 800 arranged in a trench 600 in a semiconductor substrate (see, for example, figs. 7-8 and paragraphs 0060-0061). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Shin et al. so as to have a conductive gate element arranged in a trench as disclosed by Shepard because forming gates in such a way reduces the overall amount of area on the chip and thereby improves integration.
Concerning dependent claim 2, note that by definition the at least one first channel portion is doped with a first doping type.
With respect to dependent claim 3, note that the device of Shin et al. modified by Shepard discloses at least one first channel portion is separated from the at least one first conductive gate element by a first insulator layer (see gate oxide 700 of Shepard).
With respect to dependent claim 11, note that the memory cell of Shin et al. modified by Shepard comprises wherein the at least one first conductive gate element is further arranged in at least one second trench formed in the semiconductor substrate; and, wherein the at least one first channel portion extends at least between the first and second trenches.
Concerning dependent claim 12, note that the memory cell of Shin et al. modified by Shepard disclose wherein at least one first channel portion further extends at a level of at least one second lateral surface of the at least one first conducive gate element (see, for example, fig. 8 of Shepard).
Regarding dependent claim 13, note that the memory cell of Shin et al. modified by Shepard comprises wherein the coupling of said at least one first channel portion to the electrode of the capacitive element is made by a portion of the semiconductor substrate since the channel will be in the semiconductor substrate.
Claim(s) 4 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al., US 2013/0279234 in view of Shepard, US 2014/321190 as applied to claims 1-3 and 11-13 above, and further in view of Kim et al., U.S. Patent 5,066,608.
Shin et al. and Shepard are applied as above but do not expressly disclose the claimed capacitive element. Kim et al. discloses a capacitor comprising: a second insulator 11 arranged on a first surface of the semiconductor substrate 100; at least one second conductive element 15 formed on the second insulator; and an electrode 13 formed according to the first doping type in the semiconductor substrate, wherein the second insulator layer is arranged, at least partly, between the electrode and the at least one second conductor element (see fig. 3J and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the memory cell of Shin et al. modified by Shepard so as to form the capacitor of Kim et al. because this is shown to form an effective capacitor for use in microelectronic applications.
With respect to dependent claim 8, Shin et al. and Shepard are applied as above but do not expressly disclose a third conductive element that is electrically insulated from the at least one first conductive gate element and the semiconductor substrate and at least partly arranged in said at least one first trench. Kim et al. discloses a third conductive element 15 that is electrically insulated from a first conductive gate element 2 and the semiconductor substrate 100 and at least partly arranged in a trench (see fig. 3J and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the memory cell of Shin et al. modified by Shepard so as to comprise the claimed third conductive layer because such a layer will form an effective electrode for a capacitor.
Additionally, regarding dependent claim 9, note that the third conductive element as shown in Shepard is arranged in the trench in the semiconductor substrate and surrounds at least one assembly (gate electrode 6) formed by the transistor and capacitive element.
With respect to dependent claim 10, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to connect the third conductive element to ground in the memory cell of Shin et al. modified by Shepard and Kim in order to, for example, prevent charge-up on the capacitor which can lead to floating voltage values.
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, fails to anticipate or render obvious, the limitations of: wherein the second portion is doped with a second doping type having a dopant concentration greater than a dopant concentration of the semiconductor substrate, as required by dependent claim 5.
Claims 14-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, fails to anticipate or render obvious, the limitations of: a control circuit configured to apply a first voltage in a range from 5 to 15 Volts to the at least one first conductive gate element and to apply a second voltage in the range from 5 to 15 Volts between the at least one first conductive gate element and the channel biasing portion, as required by independent claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD A BOOTH/Primary Examiner, Art Unit 2812
January 27, 2026