Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on 05/15/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, US 20210202498, hereafter ‘Liaw’ in view of Chae et al, US 20210151426, hereafter ‘Chae’.
Regarding claim 1, Liaw discloses : A semiconductor device, comprising : an active region extending along a first direction(Fig. 8, #208 extending in the y direction) : at least one gate structure having a first side and a second side opposite to each other(#230A), across the active region and extending along a second direction different from the first direction(#230A extending in the x-direction) ; a first metal-to-drain/source (MD) contact disposed on the first S/D feature(Fig. 10, #220E disposed on #214N) ; and a second MD contact disposed on the second S/D feature(Fig. 10, #220A disposed on #214P), wherein a contact area between the first MD contact and the first S/D feature is greater than a contact area between the second MD contact and the second S/D feature(Fig. 10, #220E shown to have a greater contact area than #220A and S/D contacts #220A-E can vary in length in the x-direction[0044]).
Liaw does not disclose : a first source/drain (S/D) feature disposed on the active region at the first side of the at least one gate structure; a second S/D feature disposed on the active region at the second side of the at least one gate structure.
However, in the same field of endeavor, Chae teaches : a first source/drain (S/D) feature disposed on the active region at the first side of the at least one gate structure(Fig. 10B, #CNT_c2 disposed on #SD_a of region #ACT_a); a second S/D feature disposed on the active region at the second side of the at least one gate structure(#CNT_c1 disposed on #SD_a of region #ACT_a).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Chae to Liaw to have MD contacts in the same active region having different contact area to improve reliability and integration density of semiconductors (Chae [0167]).
Regarding claim 4, Liaw as modified by Chae teaches : The semiconductor device of claim 1.
Liaw teaches: wherein a first space between the first MD contact and the at least one gate structure is substantially equal to a second space between the second MD contact and the at least one gate structure (Fig. 8, MD contacts #220E and #220A have a space substantially equal to #230C).
Regarding claim 5, Liaw as modified by Chae discloses : The semiconductor device of claim 1.
Liaw, in the above embodiment, does not teach : wherein a first space between the first MD contact and the at least one gate structure is less than a second space between the second MDcontact and the at least one gate structure.
However, in another embodiment, Liaw teaches : wherein a first space between the first MD contact and the at least one gate structure is less than a second space between the second MD contact and the at least one gate structure (Fig. 18, #220E is shown to be closer to #230C compared to #220C and #230C).
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Regarding claim 6, Liaw as modified by Chae discloses : The semiconductor device of claim 1.
Liaw teaches : further comprising: a first via-to-MD (VD) structure(Fig. 10, #226B) disposed on the first MD contact(#220E); a second VD structure(#226A) disposed on the second MD contact(#220A), wherein the second VD structure has an area less than an area of the first VD structure; and a metal line disposed on the first VD structure, wherein the metal line is electrically connected to the first S/D feature through the first VD structure and the first MD contact. (MLI structure discuss to be configured to connect to S/D contacts through a via[0037,0044].
Regarding claim 7, Liaw as modified by Chae discloses : The semiconductor device of claim 1.
Chae teaches : wherein the active region comprises a semiconductor fin on a substrate(Fig. 10B, #ACT_a shown as fins).
Regarding claim 14, Liaw discloses : A semiconductor device, comprising : a semiconductor fin disposed on a substrate and extending along a first direction(Fig. 8, #208 disposed in a y-direction);a conductive gate structure having a first side and a second side opposite to each other(#230C), across the semiconductor fin and extending along a second direction different from the first direction(#230C extending in a x-direction) ; a first dielectric gate structure disposed at the first side of the conductive gate structure(#240a top, may include structures known as continuous poly on diffusion edge[0040]); a second dielectric gate structure disposed at the second side of the conductive gate structure(#240a bottom);
Liaw does not disclose : a first source/drain (S/D) feature disposed on the semiconductor fin between the conductive gate structure and the first dielectric gate structure ; a second S/D feature disposed on the semiconductor fin between the conductive gate structure and the second dielectric gate structure ; a first MD contact disposed on the first S/D feature; and a second MD contact disposed on the second S/D feature, wherein a contact area between the first MD contact and the first S/D feature is different from a contact area between the second MD contact and the second S/D feature.
However, in the same field of endeavor, Chae teaches : a first source/drain (S/D) feature disposed on the semiconductor fin between the conductive gate structure and the first dielectric gate structure (Fig. 10a, #SD_a disposed in #ACT’ to the left of #GATE) ; a second S/D feature disposed on the semiconductor fin between the conductive gate structure and the second dielectric gate structure(Fig. 10a, #SD_a disposed in #ACT’ to the right of #GATE) ; a first MD contact disposed on the first S/D feature(Fig. 10B, #CNT_c1 disposed on #SD_a1); and a second MD contact disposed on the second S/D feature(#CNT_c2 disposed on #SD_a2), wherein a contact area between the first MD contact and the first S/D feature is different from a contact area between the second MD contact and the second S/D feature(#CNT_c1 shown to have a different contact area compared to #CNT_c2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Chae to Liaw to have MD contacts in the same active region having different contact area to improve reliability and integration density of semiconductors (Chae [0167]).
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Liaw, Fig.8 annotated, top right configuration
Claims 2, 3, and 15-18 are rejected under 35 U.S.C. 103 as being anticipated by Liaw, US 20210202498, hereafter ‘Liaw’ in view Chae et al, US 20210151426, hereafter ‘Chae’, in further view of Pei et al, US 20210280488, hereafter ‘Pei’
Regarding claim 2, Liaw as modified by Chae discloses : The semiconductor device of claim 1.
Liaw as modified by Chae does not explicitly teach : wherein the first MD contact has a first width greater than a second width of the second MD contact.
However, Pei teaches wherein the first MD contact(Fig. 4, #13) has a first width greater than a second width of the second MD contact(#14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Pei to Liaw and Chae to have a first MD contact having a greater width than the second MD contact to reduce inductance and parasitic capacitance [0060].
Regarding claim 3, Liaw as modified by Chae discloses : The semiconductor device of claim 1.
Liaw as modified by Chae does not explicitly teach : wherein a ratio of a first width of the first MD contact to a second width of the second MD contact is in a range of 1 to 2.
Pei teaches : wherein a ratio of a first width of the first MD contact(#13, #d1) to a second width of the second MD contact(#14, #d2) is in a range of 1 to 2(Fig. 4, the pitch from that gate #12 needs to satisfy d2≤d1≤3d2 [0060].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Pei to Liaw to MD contact widths in the range of 1 to 2 in order to reduce device loss and effectively balance the heat [0060].
Regarding claim 15, Liaw as modified by Chae discloses : The semiconductor device of claim 14.
Liaw as modified by Chae does not explicitly teach : wherein the first MD contact has a first width greater than a second width of the second MD contact.
However, in the same field of endeavor, Pei teaches : wherein the first MD contact(#13) has a first width(#d1) greater than a second width(#d2) of the second MD contact(#14, given by the formula d2≤d1≤3d2 [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Pei to Liaw to have a width of an MD contact be greater than then a second width of an MD contact to reduce inductance and parasitic capacitance [Pei, 0060].
Regarding claim 16, Liaw as modified by Chae and Pei discloses : The semiconductor device of claim 15.
Liaw teaches : wherein a first pitch between the conductive gate structure(Fig. 8, #230C) and the first dielectric gate structure(#240A) is substantially equal to a second pitch between the conductive gate structure and the second dielectric gate structure(#240A).
Liaw does not explicitly teach : a first space between the first MD contact and the conductive gate structure is less than a second space between the second MD contact and the conductive gate structure.
Pei teaches : a first space(Fig. 4, #d2) between the first MD contact(#14) and the conductive gate structure is less than a second space(#d1) between the second MD contact(#13) and the conductive gate structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Pei to Liaw to include a first MD contact that is has a space less than a second MD contact from a conductive gate to reduce inductance and parasitic capacitance[Pei, 0060].
Regarding claim 17, Liaw as modified by Chae and Pei discloses : The semiconductor device of claim 15.
Liaw teaches : wherein a first space between the first MD contact(#220D) and the conductive gate structure(#230C) is substantially equal to a second space between the second MD contact(#220D) and the conductive gate structure,
Liaw further teaches : a first pitch between the conductive gate structure(Fig. 8, #230A) and the first dielectric gate structure(#240A, top) is greater than a second pitch between the conductive gate structure and the second dielectric gate structure(#240A bottom).
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Liaw, Fig. 8 annotated, bottom right configuration
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Pei to Liaw to have two MD contact between a conductive gate have the same space and to have different pitches between two dielectric gate structures from a conductive gate, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). See MPEP 2144.04.
Regarding claim 18, Liaw as modified by Chae and Pei discloses : The semiconductor device of claim 15.
Liaw teaches : a first VD structure(Fig. 10, #226A) disposed on the first MD contact(#220A); a second VD structure(#226B) disposed on the second MD contact(#220E), wherein the second VD structure has an area less than an area of the first VD structure(Fig. 10, area of #226B is larger than the area of #226A); and a metal line disposed on the first VD structure, wherein the metal line(M1) is electrically connected to the first MD contact through the first VD structure(Configuration of vias similar to cell #101 [0044] where a via is connected to a S/D level contact through M1[0037]).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being anticipated by Liaw, US 20210202498, hereafter ‘Liaw’ in view of Chae et al, US 20210151426, hereafter ‘Chae’, in further view of Pei et al, US 20210280488, hereafter ‘Pei’, and in further view of Yang et al, US 20220237358, hereafter ‘Yang’.
Regarding claim 19, Liaw as modified by Chae and Pei discloses : The semiconductor device of claim 18.
Liaw teaches : comprising: a third MD contact(Fig. 8, #220) disposed between the conductive gate structure(#230) and the first dielectric gate structure(#240); and a fourth MD contact(#220) disposed between the conductive gate structure and the second dielectric gate structure(#240).
Liaw as modified by Chae and Pei does not teach : a first cut-MD (CMD) structure separating the first MD contact from the third MD contact; and a second CMD structure separating the second MD contact from the fourth MD contact.
However, in the same field of endeavor, Yang teaches : a first cut-MD (CMD) structure(Fig. 3A, #CMD) separating the first MD contact(#MD1) from the third MD contact(#MD1); and a second CMD structure(#CMD) separating the second MD contact(#MD2) from the fourth MD contact(#MD2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yang and Pei to Liaw to include cut-MD structures that signifies the separation of MD contacts.
Regarding claim 20, Liaw as modified by Chae, Pei, and Yang discloses : The semiconductor device of claim 19.
Pei teaches : wherein the first MD contact and the third MD contact have different widths, while second MD contact and the fourth MD contact have different widths.
Pei discloses a number a plurality of source(#13) and drains(#12) with varying widths for the purpose of reducing parasitic inductance, reduce device loss, and effectively balance heat distribution[0060] shown in embodiment 2(Fig. 4) and embodiment 5(Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Pei and Yang to Liaw to include an arrangement of MD contacts where the first and third MD contacts have different widths and the second and fourth contacts have different widths for the purpose of reducing parasitic inductance, reduce device loss, and effectively balance heat distribution[0060].
Response to Amendment/Arguments
Response to Amendments
Acknowledgment is made of the amendment filed 10/17/2025, in which: claims 1, 7, 8 and 14 are amended. Claims 1-7 and 14-20 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1, 7 and 14 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897