DETAILED ACTION
Response to Arguments
In light of applicant’s amendment to the claims, the rejection under 35 U.S.C. 112(b) is withdrawn.
Applicant’s arguments with respect to claims 11, 19, 21 and 27 have been considered but are moot based on the new grounds of rejection detailed below.
Furthermore, the claims have been amended sufficiently so as to no longer warrant the obviousness-type double patenting rejection over claims 1-20 of U.S. Patent No. 11,862,637. Therefore, the rejection is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 recites the limitation "the third poly gate includes" in line 22. There is insufficient antecedent basis for this limitation in the claim. The claim discloses “a third gate” in line 11 and then seems to refer to said “third gate” as “the third poly gate” which lacks proper antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-30 are rejected under 35 U.S.C. 103 as being unpatentable over HSIEH et al. (20160078164, cited in previous office action), hereinafter “Hsieh,” in view of ZHU et al. (US 20140264629 A1), hereinafter “Zhu.”
Re: Independent Claim 11, Hsieh discloses an integrated circuit device (Figs 1A-1C and 2-5; paragraphs 15-62), comprising:
a first active area (Fig. 1A: OD layout pattern 102; para 19,25; layout pattern 106 in Fig 1B, para 25) on a substrate (e.g. 410 in Fig 4A), the first active area including a first threshold voltage (VT) region and a second VT region (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a first gate (Fig. 1A: 123; para 21 for p-type transistor located at top and left in Figs 1A-1B; cell 172) contacting the first VT region of the first active area to form a first transistor having a first VT (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a second gate (Fig. 1A: 127; para 21 for p-type transistor located at top and right in Figs 1A-1B; cell 174) contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a third gate (Fig. 1A: 125; para 21 for p-type transistor located at top and middle in Figs 1A-1B) contacting the first active area at a boundary of the first VT region and the second VT region (as shown in Fig 1A, the third gate 125 is positioned at the boundary between the first and second regions) between the first gate and the second gate to form a tie-off transistor (Figs 1A-1B, para 23-24,27) positioned between the first transistor and the second transistor, the boundary being a VT boundary of mixed VT structure, wherein the tie-off transistor electrically isolates the first transistor with the first VT from the second transistor with the second VT (paragraphs 23 and 27 for dummy tie-off transistors 182 and 184 being turned off in order to isolate the cells 172 and 174, wherein the cell 172 comprises the first transistor having the first VT, and the cell 174 comprises the second transistor having the second VT);
However, Hsieh does not specifically show a metal strip perpendicular to the first active area including a first via connected to a power rail and a second via; and
a metal layer parallel to the first active area and connected to the metal strip through the second via, the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state.
In a similar field of endeavor, Zhu discloses a metal strip perpendicular to the first active area (Fig. 4A: gate-directed local interconnect 435, i.e., metal strip, perpendicular to active area, i.e., OD) including a first via (Fig. 4A: via V0) connected to a power rail and a second via (¶0034: gate-directed local interconnect 435 is biased to the power supply voltage VDD through via V0 to an appropriate lead in a first metal layer (not illustrated) or higher-level metal layers.); and
a metal layer parallel to the first active area (Fig. 4A: diffusion-directed local interconnect 445 which is parallel to active area OD) and connected to the metal strip through the second via (Fig. 4A: 445 is connected to 435), the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state (Fig. 4A: 445 metal layer is connected to gate 425, i.e., third gate; ¶0034: diffusion-directed local interconnect 445 thus couples between gate layer 425, i.e., third gate, and gate-directed local interconnect 435 to provide the bias to gate layer 425 to turn blocking transistor 430 fully off).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included structural interconnects as disclosed above in order to achieve enhanced density through an arrangement of gate-directed and diffusion-directed local interconnects (See Zhu, ¶0032). Furthermore, Zhu expressly teaches using orthogonal (perpendicular and parallel) local metal interconnects, including a via to power, in order to bias a blocking transistor gate on a continuous active region while improving density and reducing cell height (See Zhu, ¶¶0034-0035).
Re: Claim 12, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 11.
Hsieh further discloses wherein the tie-off transistor is a PMOS transistor (182 in Figs 1A-1B, para 23-24,27) and wherein the third gate is connected to a VDD power rail (paragraph 18 for Vdd as a power supply voltage).
Re: Claim 13, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 12.
Hsieh further discloses further comprising a conductive via (as shown in Figs 1A,1B, para 16) extending between the third gate and the VDD power rail (paragraph 18 for Vdd as a power supply voltage).
Re: Claim 14, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 12.
Hsieh further discloses wherein the first and second transistors (Figs 1A-1B, paragraph 21-22 for P-type transistors located on the top side) and the tie-off transistor are PMOS transistors, the device further comprising:
a second active area (at 104 in Fig 1A, para 19,25;108 in Fig 1B, para 25) on the substrate, the second active area including the first VT region and the second VT region (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
the first gate further contacting the second active area to form a first NMOS transistor (Figs 1A-1B, paragraph 21-22 for N-type transistors located at the bottom side) having the first VT;
the second gate further contacting the second active area to form a second NMOS transistor (Figs 1A-1B, paragraph 21-22 for N-type transistors located at the bottom side) having the second VT;
the third gate further contacting the second active area at the boundary of the first VT region and the second VT region (as shown in Fig 1A, the third gate 125 is positioned at the boundary between the first and second regions) between the first gate and the second gate to form an NMOS tie-off transistor (184 in Figs 1A-1B, para 23-24,27) positioned between the first NMOS transistor and the second NMOS transistor; and
wherein the third gate is connected to a second power rail (164 in Figs 1A-1B, para 18-19) to maintain the NMOS tie-off transistor in an off state.
Re: Claim 15, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 11.
Hsieh further discloses wherein the first active area includes a fin (106 in Fig 1B, para 25).
Re: Claim 16, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 14.
Hsieh further discloses wherein the first and second active areas include respective first and second fins (106,108 in Fig 1B, respectively, para 25).
Re: Claim 17, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 11.
Hsieh further discloses wherein the first, second and third gates (123,125,127 in Figs 1A-1B) include respective first, second and third poly gates (paragraphs 60-61 for using polysilicon to form gate structures 121-129, Figs 5A-5B).
Re: Claim 18, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 17.
Hsieh further discloses wherein the third poly gate (Figs 1A-1B) is connected to a VSS power rail by a conductive via (as shown in Figs 1A,1B, para 16).
Re: Claim 19, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 17.
Hsieh already teaches the third poly gate connected to the VSS power rail by a second conductive via, but lacks connecting the gate to the VSS power rail by a metal layer and a third conductive via.
Zhu further discloses connecting the gate to the VSS power rail by a metal layer and a third conductive via (¶0034: gate-directed local interconnect 435 is biased to the power supply voltage VDD through via V0 to an appropriate lead in a first metal layer (not illustrated) or higher-level metal layers.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included structural interconnects as disclosed above in order to achieve enhanced density through an arrangement of gate-directed and diffusion-directed local interconnects (See Zhu, ¶0032). Furthermore, Zhu expressly teaches using orthogonal (perpendicular and parallel) local metal interconnects, including a via to power, in order to bias a blocking transistor gate on a continuous active region while improving density and reducing cell height (See Zhu, ¶¶0034-0035).
Re: Claim 20, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 17.
Hsieh further discloses wherein the third poly gate includes a cut poly (Figs 1A-1B, para 16) between the first and second active areas.
Re: Independent Claim 21, Hsieh discloses an integrated circuit device (at Figs 1A-1C,2-5; paragraphs 15-62), comprising:
a first active area (at 102 in Fig 1A, para 19,25; 106 in Fig 1B, para 25) on a substrate (e.g. 410 in Fig 4A), the first active area including a first threshold voltage (VT) region and a second VT region (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a first PMOS transistor (Fig 1A, para 21 for p-type transistor of PMOS located at top and left in Figs 1A-1B; cell 172) including a first region having a first VT;
a second PMOS transistor (Fig 1A, para 21 for p-type transistor of PMOS located at top and right in Figs 1A-1B; cell 174) including a second region having a second VT different than the first VT (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a PMOS tie-off transistor (182 in Figs 1A-1B, para 23-24,27) positioned at a boundary of the first region and the second region such that the first PMOS transistor is on a first side of the boundary and the second PMOS transistor is on a second side of the boundary opposite the first PMOS transistor (as shown in Fig 1A, the PMOS tie-off dummy transistor 182 is positioned at the boundary between the first and second regions), the boundary being a VT boundary, wherein the tie-off transistor electrically isolates the first transistor with the first VT from the second transistor with the second VT (paragraphs 23 and 27 for dummy tie-off transistors 182 and 184 being turned off in order to isolate the cells 172 and 174, wherein the cell 172 comprises the first transistor having the first VT, and the cell 174 comprises the second transistor having the second VT);
However, Hsieh does not specifically show a metal strip perpendicular to the first active area including a first via connected to a power rail and a second via; and
a metal layer parallel to the first active area and connected to the metal strip through the second via, the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state.
In a similar field of endeavor, Zhu discloses a metal strip perpendicular to the first active area (Fig. 4A: gate-directed local interconnect 435, i.e., metal strip, perpendicular to active area, i.e., OD) including a first via (Fig. 4A: via V0) connected to a power rail and a second via (¶0034: gate-directed local interconnect 435 is biased to the power supply voltage VDD through via V0 to an appropriate lead in a first metal layer (not illustrated) or higher-level metal layers.); and
a metal layer parallel to the first active area (Fig. 4A: diffusion-directed local interconnect 445 which is parallel to active area OD) and connected to the metal strip through the second via (Fig. 4A: 445 is connected to 435), the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state (Fig. 4A: 445 metal layer is connected to gate 425, i.e., third gate; ¶0034: diffusion-directed local interconnect 445 thus couples between gate layer 425, i.e., third gate, and gate-directed local interconnect 435 to provide the bias to gate layer 425 to turn blocking transistor 430 fully off).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included structural interconnects as disclosed above in order to achieve enhanced density through an arrangement of gate-directed and diffusion-directed local interconnects (See Zhu, ¶0032). Furthermore, Zhu expressly teaches using orthogonal (perpendicular and parallel) local metal interconnects, including a via to power, in order to bias a blocking transistor gate on a continuous active region while improving density and reducing cell height (See Zhu, ¶¶0034-0035).
Re: Claim 22, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 21.
Hsieh also discloses further comprising:
a first NMOS transistor (Figs 1A-1B, paragraph 21-22 for N-type transistor of NMOS located at the bottom and left side) having the first VT;
a second NMOS transistor (Figs 1A-1B, paragraph 21-22 for N-type transistor of NMOS located at the bottom and right side) having the second VT;
an NMOS tie-off transistor (184 in Figs 1A-1B, para 23-24,27) positioned between the first NMOS transistor and the second NMOS transistor, the NMOS tie-off transistor including the gate of the PMOS tie-off transistor; and
wherein the gate of the NMOS tie-off transistor is connected to a second power rail (164 in Figs 1A-1B; paragraph 23,18) to maintain the NMOS tie-off transistor in an off state (paragraphs 23 and 27 the dummy tie-off transistors 182 and 184 in an off state).
Re: Claim 23, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 22.
Hsieh further discloses wherein the first PMOS transistor and the second PMOS transistor include a respective fin (106 in Fig 1B, para 25).
Re: Claim 24, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 22.
Hsieh further discloses wherein the first NMOS transistor and the second NMOS transistor include a respective fin (108 in Fig 1B, para 25).
Re: Claim 25, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 22.
Hsieh further discloses wherein the gate of the PMOS tie-off transistor and the NMOS tie-off transistor includes a cut poly (166 in Figs 1A-1B, para 16) between the PMOS tie-off transistor and the NMOS tie-off transistor.
Re: Claim 26, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 25.
Hsieh further discloses wherein the power rail is a VDD rail (162 in Figs 1A-1B; paragraph 23,18), and the gate of the NMOS tie-off transistor connects to a second rail, which is a VSS rail (164 in Figs 1A-1B; paragraph 23,18).
Re: Independent Claim 27, Hsieh discloses an integrated circuit device (at Figs 1A-1C,2-5; paragraphs 15-62), comprising:
a first active area (at 102 in Fig 1A, para 19,25; 106 in Fig 1B, para 25) on a substrate (e.g. 410 in Fig 4A), the first active area including a first threshold voltage (VT) region and a second VT region (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a second active area (104 in Fig 1A, para 19,25; 106 in Fig 1B, para 25) on the substrate, the second active area including the first VT region and the second VT region (paragraphs 1,54,27,31,55-61 for disclosing the transistors having different threshold voltages; Figs 5A-5B, 3A-5B);
a first gate (123 in Fig 1A) contacting the first VT region of the first active area to form a first transistor (Fig 1A, para 21 for p-type transistor located at top and left in Figs 1A-1B; in cell 172) having a first VT, and contacting the first VT region of the second active area to form a second transistor (Fig 1A, para 21 for n-type transistor located at bottom and left in Figs 1A-1B; in cell 172);
a second gate (127 in Fig 1A) contacting the second VT region of the first active area to form a third transistor (Fig 1A, para 21 for p-type transistor located at top and right in Figs 1A-1B; in cell 174) having a second VT different than the first VT, and the second gate contacting the second VT region of the second active area to form a fourth transistor (Fig 1A, para 21 for n-type transistor located at bottom and right in Figs 1A-1B; in cell 174);
a third gate (125 in Fig 1A, para 21 for p-type transistor located at top and middle in Figs 1A-1B) contacting the first active area at a boundary of the first VT region and the second VT region between the first gate and the second gate to form a tie-off transistor (182 in Figs 1A-1B, para 23-24,27) positioned between the first transistor and the third transistor, and form a second tie-off transistor (184 in Figs 1A-1B, para 23-24,27) positioned between the second transistor and the fourth transistor, the boundary being a VT boundary, wherein the tie-off transistor electrically isolates the first transistor with the first VT from the second transistor with the second VT (paragraphs 23 and 27 for dummy tie-off transistors 182 and 184 being turned off in order to isolate the cells 172 and 174, wherein the cell 172 comprises the first transistor having the first VT, and the cell 174 comprises the second transistor having the second VT); and
…
wherein the third poly gate includes a cut poly (166 in Figs 1A-1B, para 16) between the first and second active areas, and the third gate is connected to a second power rail (164 in Figs 1A-1B; paragraph 23,18) to maintain the second tie-off transistor in an off state (Paragraphs 23 and 27 the dummy tie-off transistors 182 and 184 in an off state).
However, Hsieh does not specifically show a metal strip perpendicular to the first active area including a first via connected to a power rail and a second via; and
a metal layer parallel to the first active area and connected to the metal strip through the second via, the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state.
In a similar field of endeavor, Zhu discloses a metal strip perpendicular to the first active area (Fig. 4A: gate-directed local interconnect 435, i.e., metal strip, perpendicular to active area, i.e., OD) including a first via (Fig. 4A: via V0) connected to a power rail and a second via (¶0034: gate-directed local interconnect 435 is biased to the power supply voltage VDD through via V0 to an appropriate lead in a first metal layer (not illustrated) or higher-level metal layers.); and
a metal layer parallel to the first active area (Fig. 4A: diffusion-directed local interconnect 445 which is parallel to active area OD) and connected to the metal strip through the second via (Fig. 4A: 445 is connected to 435), the metal layer also including a third via connected to the third gate to maintain the tie-off transistor in an off state (Fig. 4A: 445 metal layer is connected to gate 425, i.e., third gate; ¶0034: diffusion-directed local interconnect 445 thus couples between gate layer 425, i.e., third gate, and gate-directed local interconnect 435 to provide the bias to gate layer 425 to turn blocking transistor 430 fully off).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have included structural interconnects as disclosed above in order to achieve enhanced density through an arrangement of gate-directed and diffusion-directed local interconnects (See Zhu, ¶0032). Furthermore, Zhu expressly teaches using orthogonal (perpendicular and parallel) local metal interconnects, including a via to power, in order to bias a blocking transistor gate on a continuous active region while improving density and reducing cell height (See Zhu, ¶¶0034-0035).
Re: Claim 28, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 27.
Hsieh further discloses wherein the first transistor, the second transistor, the third transistor, and the fourth transistor include a respective fin (106 or 108 in Fig 1B, para 25).
Re: Claim 29, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 27.
Hsieh further discloses wherein the first power rail is a VDD rail (162 in Figs 1A-1B; paragraph 23,18), and the second power rail is a VSS rail (164 in Figs 1A-1B; paragraph 23,18).
Re: Claim 30, the combination of Hsieh in view of Zhu discloses the integrated circuit device of claim 27.
Hsieh further discloses wherein the first transistor and the third transistor are PMOS transistors (Figs 1A-1B, paragraph 21-22 for P-type transistors of PMOS located at the top side), and the second transistor and the fourth transistor are NMOS transistors (Figs 1A-1B, paragraph 21-22 for N-type transistors of NMOS located at the bottom side).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
LIM et al. (US 20170133365 A1) – Figs. 2, 3, 5, 6A/B, 7, 10A/B and 14 disclose structure relevant to the currently amended claims.
RASHED et al. (US 20140001563 A1) – Figs. 3B, 7A-D disclose structure relevant to the currently amended claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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