DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s cancelation of Claims 1 – 8 in the response filed on 4 December 2025 is acknowledged.
Applicant’s amendment of Claims 9 & 16 in the response filed on 4 December 2025 is acknowledged.
Applicant’s addition of Claims 21 – 27 in the response filed on 4 December 2025 is acknowledged.
Regarding Applicant’s arguments about the prior art rejections of Claims 9 – 20 on pages 6 – 7 of the response filed on 4 December 2025, the Examiner has considered Applicant’s arguments, but said arguments are moot because they do not apply to the new grounds of rejection presented in this Office Action, necessitated by Applicant’s amendment.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Regarding Claim 19, this claim recites the limitation “the first dielectric layer is formed to a thickness of 1-10 nm thereby forming a recess between a surface of the first bonding layer and a surface of the first interconnect structure”.
Regarding Claim 22, this claim recites the limitation “a minimum distance of the gaps is defined according to a thickness of the bonding layer at an interface between the first interconnect structure and the first dielectric layer”.
These limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Par. 17 teaches “The first dielectric layer is formed to a thickness of 1-10 nm thereby forming a
recess between a surface of the first bonding layer and a surface of the first interconnect structure”. However, this is not portrayed in any of the instant figures and is in conflict with Par. 31. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 – 15 & 21 – 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “selectively forming the first bonding layer” on Pag. 3 Lin. 5. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “selectively depositing the first bonding layer”.
Claim 14 recites the limitation “selectively forming the first bonding layer” on Pag. 3 Lin. 15. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “selectively depositing the first bonding layer”.
Claim 15 recites the limitation “selectively forming the first bonding layer” on Pag. 3 Lin. 20. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “selectively depositing the first bonding layer”.
Claim 21 recites the limitation “the bonding layer of the first substrate” on Pag. 4 Lin. 25. However, the meaning of this limitation is unclear, as this claim also regards “the bonding layer” and “the first substrate” as separate elements.
For the purposes of examination, this limitation will be interpreted as “the bonding layer”.
Claim 21 recites the limitation “the first interconnect” on Pag. 4 Lin. 30. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the first interconnect structure”.
Claim 21 recites the limitation “the second interconnect” on Pag. 4 Lin. 30. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the second interconnect structure”.
Claim 22 recites the limitation “wherein a minimum distance of the gaps is defined according to a thickness of the bonding layer at an interface between the first interconnect structure and the first dielectric layer” on Pag. 5 Lin. 1. However, the meaning of this limitation is unclear, as it fails to meet the metes and bounds of the invention. That is, the claim appears to require a non-zero thickness of the bonding layer at an interface between the first interconnect structure and the first dielectric layer. However, the bonding layer is not shown to be present at this interface in the instant figures.
For the purposes of examination, this limitation will be interpreted as “wherein a minimum distance of the gaps is defined according to a thickness of the bonding layer at an interface between the bonding layer and the second substrate”, which reflects Fig. 4B of the instant specification.
Claim 26 recites the limitation “the first interconnect” on Pag. 5 Lin. 20. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the first interconnect structure”.
Claim 26 recites the limitation “the second interconnect” on Pag. 5 Lin. 20. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the second interconnect structure”.
Claim 27 recites the limitation “the bonding layer of the first substrate” on Pag. 5. Lin. 25. However, the meaning of this limitation is unclear, as Claim 21—upon which Claim 27 depends—also regards “the bonding layer” and “the first substrate” as separate elements.
For the purposes of examination, this limitation will be interpreted as “the bonding layer”.
Claim 27 recites the limitation “the first bonding layer” on Pag. 5 Lin. 25. However, there is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the bonding layer”.
Claims 22 – 27 are rejected due to their dependence on Claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Regarding Independent Claim 9 and its dependent claims, Claims 10 – 13:
Claims 9, 10, 12, & 13 are rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 (US 8802538 B1) in view of KRISHTAB (US 20190198391 A1).
Regarding Claim 9,
LIU’538 discloses:
A method for fabricating semiconductor packages (Abstract), comprising:
providing a first substrate (Fig. 2A: 200; Col. 4 Lin. 15) including a first dielectric layer (Fig. 2A: 203; Col. 4 Lin. 15) and a first interconnect structure (Fig. 2A: 205; Col. 4 Lin. 15);
selectively [forming] a first bonding layer (Fig. 2A: 207; Col. 4 Lin. 20) only on the first dielectric layer;
(Fig. 2A: 207 is formed only on 203. Thus, 207 is selectively formed only on 203.)
providing a second substrate (Fig. 2B: 300; Col. 4 Lin. 15) including a second dielectric layer (Fig. 2B: 303; Col. 4 Lin 25) and a second interconnect structure (Fig. 2B: 305; Col. 4 Lin. 25);
and coupling the first substrate to the second substrate based on physically contacting the first interconnect structure and the first bonding layer with the second interconnect structure and the second dielectric layer, respectively.
(Fig. 6: 200 is coupled to 300 based on physically contacting 205 and 207 with 305 and 303—via 307—respectively.)
LIU’538, however, does not disclose:
selectively depositing, according to a process selective to the first dielectric layer relative to the first interconnect structure, a first bonding layer only on the first dielectric layer;
KRISHTAB, though, discloses:
selectively depositing, according to a process selective to the first dielectric layer (Fig. 1: 130; Par. 57) relative to the first interconnect structure (Fig. 1: 120; Par. 58), a first bonding layer (Fig. 1: 110; Par. 58) only on the first dielectric layer;
(Fig. 1: 110 is selectively deposited only on 130, according to “an area-selective deposition (ASD) process”, which is selective to 130, relative to 120, Par. 58.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable the selective deposition, according to a process selective to the first dielectric layer relative to the first interconnect structure, of the first bonding layer only on the first dielectric layer in LIU’538 according to the teachings of KRISHTAB, as LIU’538 does not provide a method of forming its first bonding layer. Therefore, a person having ordinary skill in the art would look to the prior art for a method of forming the first bonding layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the method of forming the first bonding layer of KRISHTAB meets these criteria, as the first bonding layer of LIU’538 and KRISHTAB are similar in that both comprise a dielectric material (KRISHTAB 110; Par. 16 – 17 & LIU’538 207; Col. 2 Lin. 65), which is selectively formed on another dielectric material (KRISHTAB 130; Par. 57 & LIU’538 203; Col. 4 Lin. 15) relative to a metal material (KRISHTAB 120; Par. 58 & LIU’538 205; Col. 4 Lin. 15).
Regarding Claim 10,
LIU’538 discloses:
The method of claim 9, wherein the step of coupling the first substrate to the second substrate further comprises:
selectively forming a second bonding layer (Fig. 2B: 307; Col. 4 Lin. 25) only on the second dielectric layer;
(Fig. 3B: 307 is formed only on 303. Thus, 307 is selectively formed only on 303.)
and coupling the first substrate to the second substrate based on physically contacting the first interconnect structure and the first bonding layer with the second interconnect structure and the second bonding layer, respectively,
(Fig. 6: 200 is coupled to 300 based on physically contacting 205 and 207 with 305 and 307, respectively.)
and wherein the first bonding layer and the second bonding layer each include a material selected from a group consisting of: silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (A12O3), hafnium oxide (HfO2), and combinations thereof.
(207 and 307 each may include “SiO2, nitrides such as SiN, silicon oxynitride (SiON), and/or high-k dielectrics used in semiconductor devices”, Col. 2 Lin. 65)
KRISHTAB also discloses:
and wherein the first bonding layer…include[s] a material selected from a group consisting of: silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (A12O3), hafnium oxide (HfO2), and combinations thereof.
(“[110] may for example comprise one or more of the following elements: AlO.sub.x, ZrO.sub.x, HfO.sub.x, ZnO, CoO.sub.x, or any other oxide of a metal of the group consisting of Zn, Fe, In, Co, Cu, Mn, Li, B, Cd, Hg, Mg, Al, Zr, Hf, Ti, Ta, and Pr”, Par. 17, which includes aluminum oxide (Al2O3) and hafnium oxide (HfO2).)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable the first bonding layer to include aluminum oxide (Al2O3) and/or hafnium oxide (HfO2) in LIU’538 according to the teachings of KRISHTAB, as LIU’538 teaches the first bonding layer may comprise “high-k dielectrics used in semiconductor devices” (LIU’538 Col. 2 Lin. 65), KRISHTAB teaches the first bonding layer may comprise aluminum oxide (Al2O3) and/or hafnium oxide (HfO2) (KRISHTAB Par. 17), and both aluminum oxide (Al2O3) and hafnium oxide (HfO2) are high-k dielectrics, which are known in the art to be used in semiconductor devices (KRISHTAB Par. 17).
Regarding Claim 12,
LIU’538 discloses:
The method of claim 9, wherein the step of coupling the first substrate to the second substrate further comprises:
aligning the first interconnect structure with the second interconnect structure;
(Fig. 5: 205 is aligned with 305.)
physically contacting the first bonding layer with the second dielectric layer;
(Fig. 5: 207 is physically contacted with 303—via 307.)
and annealing the first substrate and the second substrate to physically contact the first interconnect structure with the second interconnect structure.
(Fig. 6: 200 and 300 are annealed, Col. 5 Lin. 5, to physically contact 205 with 305.)
Regarding Claim 13,
LIU’538 does not disclose:
The method of claim 9,
wherein the step of selectively depositing the first bonding layer comprises
performing at least one atomic layer deposition process.
KRISHTAB, though, discloses:
wherein the step of selectively depositing the first bonding layer comprises
performing at least one atomic layer deposition process.
(The step of selectively depositing 110 comprises performing an area-selective deposition (ASD) process, Par. 58, which may be a type of atomic layer deposition process, Par. 14.)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB and in further view of LIU’004 (US 20200212004 A1).
Regarding Claim 11,
LIU’538 and KRISHTAB do not disclose:
The method of claim 9, further comprising:
rinsing the first substrate with DI water to hydrophilize the first bonding layer.
LIU’004, though, discloses:
rinsing the first substrate (Fig. 2C: 202; Par. 55) with DI water to hydrophilize the first bonding layer (Fig. 2C: front surface of 202; Par. 55).
(202 is rinsed with DI water to “increase the amount of hydroxyl groups” on the front surface of 202, Par. 55, which inherently hydrophilizes the front surface of 202.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of LIU’004 to enable rinsing the first substrate with DI water to hydrophilize the first bonding layer in LIU’538 according to the teachings of LIU’004 for the further advantage of “increase[ing] the amount of hydroxyl groups” on the first boding layer (LIU’004 Par. 55), which increases the “hydrogen bonding in the hydroxyl groups” between the first bonding layer and the second dielectric layer (LIU’004 Par. 27), which then improves the ability to couple the first substrate to the second substrate based on physically contacting the first bonding layer and the second dielectric layer (LIU’004 Par. 27).
Regarding Independent Claim 9 and its dependent claims, Claims 14 & 15:
Claims 9, 14, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over SADAKA (US 20130020704 A1) in view of KRISHTAB.
Regarding Claim 9,
SADAKA discloses:
A method for fabricating semiconductor packages (Fig. 2A – 2K), comprising:
providing a first substrate (Fig. 2E: 202/205; Par. 50) including a first dielectric layer (Fig. 2E: 202; Par. 50) and a first interconnect structure (Fig. 2E: 205; Par. 205);
selectively [forming], according to a process selective to the first dielectric layer relative to the first interconnect structure, a first bonding layer (Fig. 2I: 212; Par. 59) only on the first dielectric layer;
(Fig. 2I: 212 is formed only on 202. Therefore, 212 is selectively formed only on 202, according to a process selective to 202, relative to 205.)
providing a second substrate (Fig. 2D: 102/105; Par. 48) including a second dielectric layer (Fig. 2D: 102; Par. 48) and a second interconnect structure (Fig. 2D: 105; Par. 39);
and coupling the first substrate to the second substrate based on physically contacting the first interconnect structure and the first bonding layer with the second interconnect structure and the second dielectric layer, respectively.
(Fig. 2K: 202/205 is coupled to 102/105 based on physically contacting 205 and 212 with 105 and 102, respectively)
SADAKA, however, does not disclose:
selectively depositing, according to a process selective to the first dielectric layer relative to the first interconnect structure, a first bonding layer only on the first dielectric layer;
KRISHTAB, though, discloses:
selectively depositing, according to a process selective to the first dielectric layer relative to the first interconnect structure, a first bonding layer only on the first dielectric layer;
selectively depositing, according to a process selective to the first dielectric layer (Fig. 1: 130; Par. 57) relative to the first interconnect structure (Fig. 1: 120; Par. 58), a first bonding layer (Fig. 1: 110; Par. 58) only on the first dielectric layer;
(Fig. 1: 110 is selectively deposited only on 130, according to “an area-selective deposition (ASD) process”, which is selective to 130, relative to 120, Par. 58.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of SADAKA with those of KRISHTAB to enable the selective deposition, according to a process selective to the first dielectric layer relative to the first interconnect structure, of the first bonding layer only on the first dielectric layer in SADAKA according to the teachings of KRISHTAB for the further advantage of eliminating the overlayer error (KRISHTAB Par. 3) inherently present in the lithographic step (SADAKA Fig. 2H; Par. 57 – 58).
Regarding Claim 14,
SADAKA discloses:
The method of claim 9, further comprising: prior to selectively [forming] the first bonding layer,
performing a first polishing process (Par. 51: a chemical mechanical polishing (CMP) process) on the first substrate to form a first coplanar surface (Fig. 2E: 203; Par. 51) shared by the first dielectric layer and the first interconnect structure.
(Fig. 2E: a CMP process is performed on 202/205 to form 203 shared by 202 and 205, Par. 51.)
SADAKA, however, does not disclose:
…selectively depositing the first bonding layer…
KRISHTAB, though, discloses:
…selectively depositing the first bonding layer…
(As stated for Claim 9.)
Regarding Claim 15,
SADAKA discloses:
The method of claim 14, wherein following selectively [forming] the first bonding layer,
a top surface (Fig. 2E/2I: 207; Par. 51) of the first interconnect structure is recessed from a top surface (Fig. 2I: 214; Par. 54) of the first bonding layer.
(Fig. 2I: 207 of 205 is recessed from 214 of 212.)
SADAKA, however, does not disclose:
…selectively depositing the first bonding layer…
KRISHTAB, though, discloses:
…selectively depositing the first bonding layer…
(As stated for Claim 9.)
Regarding Independent Claim 16 and its dependent claims, Claims 17 – 20:
Claims 16, 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB.
Regarding Claim 16,
LIU’538 discloses:
A method for fabricating semiconductor packages (Abstract), comprising:
providing a first substrate (Fig. 4A: 200; Col. 4 Lin. 15) including a first dielectric layer (Fig. 4A: 203; Col. 4 Lin. 15) and a first interconnect structure (Fig. 4A: 205; Col. 4 Lin. 15) exposed at a surface of the first dielectric layer;
(Fig. 4A: 200 includes 203 and 205 where 205 is exposed at the top surface of 203)
forming a first bonding layer (Fig. 4A: 207; Col. 4 Lin. 20) on the first dielectric layer, according to a process selective to the first dielectric layer relative to the exposed portions of the first interconnect structure, to elevate a surface of the first substrate above the first interconnect structure;
(Fig. 4A: 207 is formed on 203, according to a process that yields 207 on 203 and not on the exposed portions of 205. Therefore, this process is selective to 203, relative to the exposed portions of 205. Further, 207 is formed on 203 such that the top surface of 200 is above 205. Therefore, 207 is formed on 203 to elevate the top surface of 200 above 205.)
providing a second substrate (Fig. 4B: 300; Col. 4 Lin. 15) including a second dielectric layer (Fig. 4B: 303/307; Col. 4 Lin. 25) and a second interconnect structure (Fig. 4B: 305; Col. 4 Lin. 25);
bonding the first bonding layer with the second substrate at a bonding interface (Fig. 5: 215; Col. 4 Lin. 65) between the first bonding layer and the second dielectric layer;
(Fig. 5: 207 is bonded with 300 at 215, Col. 4 Lin. 65, which is between 207 and 303/307)
and physically contacting the first interconnect structure with the second interconnect structure.
(Fig. 6: 205 physically contacts 305.)
LIU’538, however, does not disclose:
forming a first bonding layer on the first dielectric layer…using an atomic deposition process;
KRISHTAB, though, discloses:
forming a first bonding layer (Fig. 1: 110; Par. 58) on the first dielectric layer (Fig. 1: 130; Par. 57)…using an atomic deposition process;
(Fig. 1: 110 is formed on 130 using “an area-selective deposition (ASD) process”, Par. 58, which may be an atomic deposition process, Par. 14.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable forming a first bonding layer on the first dielectric layer using an atomic deposition process in LIU’538 according to the teachings of KRISHTAB, as LIU’538 does not provide a method for forming its first bonding layer. Therefore, a person having ordinary skill in the art would look to the prior art for a method of forming the first bonding layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the method of forming the first bonding layer of KRISHTAB meets these criteria, as the first bonding layer of LIU’538 and KRISHTAB are similar in that both comprise a dielectric material (KRISHTAB 110; Par. 16 – 17 & LIU’538 207; Col. 2 Lin. 65), which is selectively formed on another dielectric material (KRISHTAB 130; Par. 57 & LIU’538 203; Col. 4 Lin. 15) relative to a metal material (KRISHTAB 120; Par. 58 & LIU’538 205; Col. 4 Lin. 15).
Regarding Claim 17,
LIU’538 discloses:
The method of claim 16,
wherein the first bonding layer include a material selected from a group consisting of: silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (A12O3), hafnium oxide (HfO2), and combinations thereof.
(207 may include “SiO2, nitrides such as SiN, silicon oxynitride (SiON), and/or high-k dielectrics used in semiconductor devices”, Col. 2 Lin. 65)
KRISHTAB also discloses:
wherein the first bonding layer include a material selected from a group consisting of: silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (A12O3), hafnium oxide (HfO2), and combinations thereof.
(“[110] may for example comprise one or more of the following elements: AlO.sub.x, ZrO.sub.x, HfO.sub.x, ZnO, CoO.sub.x, or any other oxide of a metal of the group consisting of Zn, Fe, In, Co, Cu, Mn, Li, B, Cd, Hg, Mg, Al, Zr, Hf, Ti, Ta, and Pr”, Par. 17, which includes aluminum oxide (Al2O3) and hafnium oxide (HfO2).)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable the first bonding layer to include aluminum oxide (Al2O3) and/or hafnium oxide (HfO2) in LIU’538 according to the teachings of KRISHTAB, as LIU’538 teaches the first bonding layer may comprise “high-k dielectrics used in semiconductor devices” (LIU’538 Col. 2 Lin. 65), KRISHTAB teaches the first bonding layer may comprise aluminum oxide (Al2O3) and/or hafnium oxide (HfO2) (KRISHTAB Par. 17), and both aluminum oxide (Al2O3) and hafnium oxide (HfO2) are high-k dielectrics, which are known in the art to be used in semiconductor devices (KRISHTAB Par. 17).
Regarding Claim 20,
LIU’538 discloses:
The method of claim 16, wherein following forming the first bonding layer,
a top surface of the first interconnect structure is recessed from a top surface of the first bonding layer.
(Fig. 4A: the top surface of 205 is recessed by TD from the top surface of 207.)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB and in further view of LIU’004.
Regarding Claim 18,
LIU’538 and KRISHTAB do not disclose:
The method of claim 16, prior to physically contacting the first bonding layer with second bonding layer, further comprising:
rinsing the first substrate with DI water to hydrophilize the first bonding layer.
LIU’004, though, discloses:
rinsing the first substrate (Fig. 2C: 202; Par. 55) with DI water to hydrophilize the first bonding layer (Fig. 2C: front surface of 202; Par. 55).
(202 is rinsed with DI water to “increase the amount of hydroxyl groups” on the front surface of 202, Par. 55, which inherently hydrophilizes the front surface of 202.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of LIU’004 to enable rinsing the first substrate with DI water to hydrophilize the first bonding layer in LIU’538 according to the teachings of LIU’004 for the further advantage of “increase[ing] the amount of hydroxyl groups” on the first boding layer (LIU’004 Par. 55), which increases the “hydrogen bonding in the hydroxyl groups” between the first bonding layer and the second dielectric layer (LIU’004 Par. 27), which then improves the ability to couple the first substrate to the second substrate based on physically contacting the first bonding layer and the second dielectric layer (LIU’004 Par. 27).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB and in further view of CHEN (US 20200006284 A1).
Regarding Claim 19,
LIU’538 discloses,
The method of claim 16,
wherein the first dielectric layer is formed…thereby forming a recess (Fig. 4A: TD; Col. 5 Lin. 30) between a surface of the first bonding layer and a surface of the first interconnect structure,
(Fig. 4A: 203 is formed, which results in—and thereby—forms TD between the top surface of 207 and the top surface of 205.)
and wherein after bonding the first bonding layer with the second substrate
(As described in Claim 16)
an anneal is performed to physical contact the first interconnect structure with the second interconnect structure through the recess.
(Fig. 6: an anneal is performed, Col. 5 Lin. 5, to physically contact 205 with 305 through TD.)
LIU’538 and KRISHTAB, however, do not disclose:
wherein the first dielectric layer is formed to a thickness of 1-10 nm
CHEN, though, discloses:
wherein the first dielectric layer (Fig. 5: 202; Par. 42) is formed to a thickness great than 1 nm
(Fig. 5: 202 is formed to a thickness greater than 1 nm, CHEN ¶ [0050].)
CHEN, however, does not disclose:
wherein the first dielectric layer is formed to a thickness of 1-10 nm
Regardless, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the first dielectric layer of CHEN to be formed to a thickness of 1 – 10 nm. As one would have chosen the thickness of the first dielectric layer according to a result effective variable, balancing the need to provide an appropriate amount of space for a sufficient thickness of the first bonding layer for bonding to the second substrate by making the first dielectric layer thinner, (CHEN Par. 50), and the need to provide an appropriate amount of recess between the surface of the first bonding layer and the surface of the first interconnect structure by making the first dielectric layer thicker (MPEP 2144.05 II B).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of CHEN to enable the first dielectric layer to be formed to a thickness of 1-10 nm in LIU’538 according to the teachings of CHEN, as LIU’538 does not provide a thickness for its first dielectric layer. Therefore, a person having ordinary skill in the art would look to the prior art for a thickness of the first dielectric layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the thickness of the first dielectric layer of CHEN meets these criteria, as such thicknesses of the first dielectric layer facilitate providing an appropriate amount of space for a sufficient thickness of the first bonding layer for bonding to the second substrate, (CHEN Par. 50).
Regarding Independent Claim 21 and its dependent claims, Claims 22 – 27:
Claims 21 – 26 are rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB.
Regarding Claim 21,
LIU’538 discloses:
A method of fabricating semiconductor packages (Abstract), comprising:
providing a first substrate (Fig. 4A: 203/205; Col. 4 Lin. 15) including a first dielectric layer (Fig. 4A: 203; Col. 4 Lin. 15) and exposed portions of a first interconnect structure (Fig. 4A: exposed portions of 205; Col. 4 Lin. 15);
[forming] a bonding layer (Fig. 4A: 207; Col. 4 Lin. 20) over the first substrate according to a process selective to the first dielectric layer, relative to the exposed portions of the first interconnect structure;
(Fig. 4A: 207 is formed over 203 of 203/205 according to a process that yields 207 on 203 and not on the exposed portions of 205. Therefore, this process is selective to 203, relative to the exposed portions of 205.)
providing a second substrate (Fig. 4B: 300; Col. 4 Lin. 15) including a second dielectric layer (Fig. 4B: 303; Col. 4 Lin. 25) and a second interconnect structure (Fig. 4B: 305; Col. 4 Lin. 25);
and bonding the bonding layer with the second substrate to form gaps between the first interconnect structure and the second interconnect structure;
(Fig. 5: 207 is bonded with 300, Col. 4 Lin. 65, which forms gaps vertically between 205 and 305.)
and expanding at least one of the first interconnect structure and the second interconnect structure across the gaps to physically contact the first interconnect structure with the second interconnect structure.
(Fig. 6: 205 and 305 expand across the gaps, Col. 5 Lin. 10, resulting in physical contact between 205 and 305.)
LIU’538, however, does not disclose:
depositing a bonding layer over the first substrate according to a process selective to the first dielectric layer, relative to the exposed portions of the first interconnect structure;
KRISHTAB, though, discloses:
depositing a bonding layer (Fig. 1: 110; Par. 58) over the first substrate (Fig. 1: 130/120; Par. 57) according to a process selective to the first dielectric layer, relative to the exposed portions of the first interconnect structure;
(Fig. 1: 110 is deposited over 130/120 according to “an area-selective deposition (ASD) process”, which is selective to 130, relative to the exposed portions of 120, Par. 58.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable depositing a bonding layer over the first substrate according to a process selective to the first dielectric layer, relative to the exposed portions of the first interconnect structure in LIU’538 according to the teachings of KRISHTAB, as LIU’538 does not provide a method for forming its bonding layer. Therefore, a person having ordinary skill in the art would look to the prior art for a method of forming the bonding layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the method of forming the bonding layer of KRISHTAB meets these criteria, as the bonding layer of LIU’538 and KRISHTAB are similar in that both comprise a dielectric material (KRISHTAB 110; Par. 16 – 17 & LIU’538 207; Col. 2 Lin. 65), which is selectively formed on another dielectric material (KRISHTAB 130; Par. 57 & LIU’538 203; Col. 4 Lin. 15) relative to a metal material (KRISHTAB 120; Par. 58 & LIU’538 205; Col. 4 Lin. 15).
Regarding Claim 22,
LIU’538 discloses:
The method of claim 21,
wherein a minimum distance (Fig. 5: the sum of TD and BD; Col. 5 Lin. 30) of the gaps is defined according to a thickness of the bonding layer at an interface (Fig. 5: 215; Col. 4 Lin. 65) between the bonding layer and the second substrate.
(Fig. 5: the sum of TD and BD of the gaps is defined—in part—according to the thickness of 207 at 215 between 207 and 300. Further, TD is “the distance from the upper surface of [200] to the top surface of [205]”, and BD is “similar” with regard to the upper surface of 300 and the top surface of 305, Col. 4 Lin. 55, making the sum of TD and BD the minimum distance of the gaps, as this sum does not account for any surfaces below the top surface of 205 and/or 305, such as those that would occur from dishing.)
Regarding Claim 23,
LIU’538 discloses:
The method of claim 22,
wherein a maximum distance of the gaps is defined according to a thickness of the bonding layer and dishing of at least one of the first interconnect structure or the second interconnect structure.
(As stated for Claim 22, the minimum distance of the gaps is the sum of TD and BD, which does not include any added distance due to dishing, and is defined—in part—according to the thickness of 207. Further, while not portrayed in Fig. 5, dishing may occur in 205 and/or 305, Col. 5 Lin. 45. Therefore, the maximum distance of the gaps may be defined as the sum of the minimum distance of the gaps—which is defined, in part, according to the thickness of 207—and any added distance due to said dishing of 205 and/or 305.)
Regarding Claim 24,
LIU’538 discloses:
The method of claim 21,
wherein a second bonding layer (Fig. 4B: 307; Col. 4 Lin. 25) is selectively [formed] over the second dielectric layer of the second substrate,
(Fig. 4B: 307 is formed only over 303 of 300. Thus, 307 selectively formed over 303 of 300.)
such that a minimum distance (Fig. 5: the sum of TD and BD; Col. 5 Lin. 30) of the gaps is defined according to a sum of the thicknesses of the bonding layer and the second bonding layer.
(Fig. 5: the sum of TD and BD of the gaps is defined—in part—according to the sum of the thicknesses of 207 and 307.)
LIU’538, however, does not disclose:
wherein a second bonding layer is selectively deposited over the second dielectric layer of the second substrate…
KRISHTAB, though, discloses:
wherein a second bonding layer (Fig. 1: 110; Par. 58) is selectively deposited over the second dielectric layer (Fig. 1: 130; Par. 57) of the second substrate (Fig. 1: 130/120; Par. 57)…
(Fig. 1: 110 is selectively deposited over 130 of 130/120, Par. 58.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable a second bonding layer to be selectively deposited over the second dielectric layer of the second substrate in LIU’538 according to the teachings of KRISHTAB, as LIU’538 does not provide a method for forming its second bonding layer. Therefore, a person having ordinary skill in the art would look to the prior art for a method of forming the second bonding layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the method of forming the second bonding layer of KRISHTAB meets these criteria, as the second bonding layer of LIU’538 and KRISHTAB are similar in that both comprise a dielectric material (KRISHTAB 110; Par. 16 – 17 & LIU’538 207; Col. 2 Lin. 65), which is selectively formed on another dielectric material (KRISHTAB 130; Par. 57 & LIU’538 203; Col. 4 Lin. 15) relative to a metal material (KRISHTAB 120; Par. 58 & LIU’538 205; Col. 4 Lin. 15).
Regarding Claim 25,
LIU’538 discloses:
The method of claim 21,
wherein the process is [a forming] process for at least one [high-k dielectric used in semiconductor devices].
(The process—of forming 207—is a forming process, which may form any high-k dielectric used in semiconductor devices, Col. 2 Lin. 65.)
LIU’538, however, does not disclose:
wherein the process is an atomic layer deposition process for at least one of aluminum oxide (A1203) or hafnium oxide (HfO2).
KRISHTAB, though, discloses:
wherein the process is an atomic layer deposition process for at least one of aluminum oxide (A1203) or hafnium oxide (HfO2).
(The process—of forming 101—may be an atomic layer deposition process, Par. 14, for “one or more of the following elements: AlO.sub.x, ZrO.sub.x, HfO.sub.x, ZnO, CoO.sub.x, or any other oxide of a metal of the group consisting of Zn, Fe, In, Co, Cu, Mn, Li, B, Cd, Hg, Mg, Al, Zr, Hf, Ti, Ta, and Pr”, Par. 17, which includes aluminum oxide (Al2O3) and hafnium oxide (HfO2).)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable the process—of forming the bonding layer—to be an atomic layer deposition process in LIU’538 according to the teachings of KRISHTAB, as LIU’538 does not provide a method for forming its bonding layer. Therefore, a person having ordinary skill in the art would look to the prior art for a method of forming the bonding layer recognized for its suitability and intended purpose (MPEP 2144.07). Further, the method of forming the bonding layer of KRISHTAB meets these criteria, as the bonding layer of LIU’538 and KRISHTAB are similar in that both comprise a dielectric material (KRISHTAB 110; Par. 16 – 17 & LIU’538 207; Col. 2 Lin. 65), which is selectively formed on another dielectric material (KRISHTAB 130; Par. 57 & LIU’538 203; Col. 4 Lin. 15) relative to a metal material (KRISHTAB 120; Par. 58 & LIU’538 205; Col. 4 Lin. 15).
Further still, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of KRISHTAB to enable the process—of forming the bonding layer—to be for at least one of aluminum oxide (A1203) or hafnium oxide (HfO2) in LIU’538 according to the teachings of KRISHTAB, as LIU’538 teaches the bonding layer may comprise “high-k dielectrics used in semiconductor devices” (LIU’538 Col. 2 Lin. 65), KRISHTAB teaches the bonding layer may comprise aluminum oxide (Al2O3) and/or hafnium oxide (HfO2) (KRISHTAB Par. 17), and both aluminum oxide (Al2O3) and hafnium oxide (HfO2) are high-k dielectrics, which are known in the art to be used in semiconductor devices (KRISHTAB Par. 17).
Regarding Claim 26,
LIU’538 discloses:
The method of claim 21, further comprising:
annealing the first substrate, as bonded with the second substrate by the bonding layer, to expand the first interconnect structure and the second interconnect structure across the gaps.
(Fig. 6: 203/205 is annealed, Col. 5 Lin. 5, as bonded with 300 by 207, Col. 4 Lin. 65, to expand 205 and 305 across the gaps, Col. 5 Lin. 10.)
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over LIU’538 in view of KRISHTAB and in further view of LIU’004.
Regarding Claim 27,
LIU’538 and KRISHTAB do not disclose:
The method of claim 21, further comprising:
rinsing the first substrate with DI water to hydrophilize the bonding layer prior to bonding the bonding layer with the second substrate.
LIU’004, though, discloses:
rinsing the first substrate (Fig. 2C: 202; Par. 55) with DI water to hydrophilize the bonding layer (Fig. 2C: front surface of 202; Par. 55) prior to bonding the bonding layer with the second substrate (Fig. 2C: 204; Par. 55).
(202 is rinsed with DI water to “increase the amount of hydroxyl groups” on the front surface of 202, Par. 55, which inherently hydrophilizes the front surface of 202, and this is done prior to bonding the front surface of 202 with 204, Par. 56.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LIU’538 with those of LIU’004 to enable rinsing the first substrate with DI water to hydrophilize the bonding layer prior to bonding the bonding layer with the second substrate in LIU’538 according to the teachings of LIU’004 for the further advantage of “increase[ing] the amount of hydroxyl groups” on the boding layer (LIU’004 Par. 55), which increases the “hydrogen bonding in the hydroxyl groups” between the bonding layer and the second substrate (LIU’004 Par. 27), which then improves the ability to bond the bonding layer with the second substrate (LIU’004 Par. 27).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898