Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 2/4/2026 has been entered. Claims 1, 7, 10 are previously presented. Claim 2 – 6, 8 – 9, 11 – 15 are canceled. Claims 1, 7, 10 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
( Previously Presented ) Claims 1, 7, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hong ( Pub. No. US 20030059959 A1 ), hereinafter Hong; in view of Cabral ( Pat. No. US 5828131 A ), hereinafter Cabral.
Regarding ( Previously Presented ) Independent Claim 1, Hong teaches a method of forming a contact ( Hong, claim 1, contact ), the method comprising:
depositing a work function ( Hong, [0023], work functions ) layer on an exposed region of a transistor ( Hong, [0002], consists of a set of a transistor and a capacitor ) on a substate, the work function layer ( Hong, [0023], work functions ) comprising titanium and a metal ( Hong, [0013], titanium silicide ), the titanium and the metal ( Hong, [0013], titanium silicide ) forming a conductive silicide ( Hong, [0013], titanium silicide ) having a general formula of VxTiySiz ( Hong, [0013], titanium silicide ) or a general formula of MnxTiySiz ( Hong, [0013], titanium silicide ) on the region.
Hong fails to specifically disclose:
depositing a work function layer on an exposed source/drain region of the transistor on a substate.
a metal selected from vanadium or manganese.
However, Cabral teaches:
depositing a work function layer on an exposed source/drain region of a transistor on a substate ( Cabral, column 11, line 38, The process of the present invention may be readily integrated into present semiconductor fabrication techniques employing titanium silicide layers formed from pure titanium. For example, in reference to FIG. 16, a CMOS transistor is shown employing titanium silicide layers 150 of the present invention as the source 152, drain 154 and gate contacts 156 on both N-MOSFET and P-MOSFET devices ).
a metal selected from vanadium ( Cabral, Abstract, The titanium alloy may further comprise silicon and the refractory metal may be …, V, …; column 2, line 45, In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr ) or manganese.
Hong and Cabral are both considered to be analogous to the claimed invention because they are forming low contact resistivity titanium silicide for semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hong ( work function layer comprising titanium silicide ), to incorporate the teachings of Cabral ( employing titanium silicide layers 150 of the present invention as the source 152, drain 154 and gate contacts 156 on both N-MOSFET and P-MOSFET devices ), to implement that depositing a work function layer on an exposed source/drain region of a transistor. Doing so would form a titanium silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the titanium silicide has been reduced by the use of a refractory metal, and therefore low contact resistance can be implemented.
Regarding ( Previously Presented ) Independent Claim 7, Hong and Cabral teach a method of forming a contact ( Hong, claim 1, contact ), the method comprising:
pre-cleaning an exposed surface of a source/drain region of a transistor on a substrate ( Cabral, column 11, line 38, The process of the present invention may be readily integrated into present semiconductor fabrication techniques employing titanium silicide layers formed from pure titanium. For example, in reference to FIG. 16, a CMOS transistor is shown employing titanium silicide layers 150 of the present invention as the source 152, drain 154 and gate contacts 156 on both N-MOSFET and P-MOSFET devices ); and
depositing a work function ( Hong, [0023], work functions ) layer on the source/drain region ( Cabral, column 11, line 38, source 152, drain 154 ), the work function ( Hong, [0023], work functions ) layer comprising titanium and a metal ( Hong, [0013], titanium silicide ) selected from vanadium ( Cabral, Abstract, The titanium alloy may further comprise silicon and the refractory metal may be …, V, …; column 2, line 45, In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr ) or manganese, the titanium and the metal ( Hong, [0013], titanium silicide ) forming a conductive silicide ( Hong, [0013], titanium silicide ) having a general formula of VxTiySiz ( Hong, [0013], titanium silicide ) ( Cabral, Abstract, The titanium alloy may further comprise silicon and the refractory metal may be …, V, …; column 2, line 45, In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr ) or a general formula of MnxTiySiz ( Hong, [0013], titanium silicide )
Regarding ( Previously Presented ) Independent Claim 10, Hong and Cabral teach a semiconductor device comprising:
a source/drain region on a substrate, the source/drain region comprising silicon ( Cabral, column 11, line 38, The process of the present invention may be readily integrated into present semiconductor fabrication techniques employing titanium silicide layers formed from pure titanium. For example, in reference to FIG. 16, a CMOS transistor is shown employing titanium silicide layers 150 of the present invention as the source 152, drain 154 and gate contacts 156 on both N-MOSFET and P-MOSFET devices );
a work function ( Hong, [0023], work functions ) layer on the source/drain region, the work function ( Hong, [0023], work functions ) layer having a general formula of VxTiySiz ( Hong, [0013], titanium silicide ) ( Cabral, Abstract, The titanium alloy may further comprise silicon and the refractory metal may be …, V, …; column 2, line 45, In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr ) or a general formula of MnxTiySiz ( Hong, [0013], titanium silicide ); and
a metal contact ( Hong, claim 1, contact ) on the work function ( Hong, [0023], work functions ) layer.
Response to Arguments
Applicant's arguments filed 2/4/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding Hong: applicant’s remarks, page 8, line 11 from bottom, cited “ Hong does not disclose, teach, or suggest depositing work function layers comprising titanium and a metal selected from vanadium or manganese, where the titanium and the metal form an alloy or intermetallic on the source/drain region on a source/drain region of a transistor. If anything, Hong teaches away from titanium silicide and tri-element barrier metal layers. ”.
Examiner’s response: please refer to claim 1 of Claim Rejections - 35 USC § 103 in this office action, cited “ depositing a work function ( Hong, [0023], work functions ) layer on an exposed region of a transistor ( Hong, [0002], consists of a set of a transistor and a capacitor ) on a substrate, the work function layer ( Hong, [0023], work functions ) comprising titanium and a metal ( Hong, [0013], titanium silicide ) …
Hong fails to specifically disclose:
…
a metal selected from vanadium or manganese.
However, Cabral teaches:
…
a metal selected from vanadium ( Cabral, Abstract, The titanium alloy may further comprise silicon and the refractory metal may be …, V, …; column 2, line 45, In one application of the above method the titanium alloy may comprise from 1 to 15 atomic percent refractory metal and the refractory metal may comprise one or more of the group consisting of Ta, Nb, Mo, W, V and Cr ) or manganese.
Hong and Cabral are both considered to be analogous to the claimed invention because they are forming low contact resistivity titanium silicide for semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hong ( work function layer comprising titanium silicide ), to incorporate the teachings of Cabral ( employing titanium silicide layers 150 of the present invention as the source 152, drain 154 and gate contacts 156 on both N-MOSFET and P-MOSFET devices ), to implement that depositing a work function layer on an exposed source/drain region of a transistor. Doing so would form a titanium silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the titanium silicide has been reduced by the use of a refractory metal, and therefore low contact resistance can be implemented. ”.
Besides, Hong does not teach away from titanium silicide and tri-element barrier metal layers, because “ Hong and Cabral are both considered to be analogous to the claimed invention because they are forming low contact resistivity titanium silicide for semiconductor devices ”, as shown in Hong, [0009] cited “ Also, when the bottom electrode is contacted to the polysilicon plug, a reaction between the bottom electrode and the polysilicon plug is caused at a temperature of over 250
°
C, so that a resistance of the boundary between the bottom electrode and the polysilicon plug increases. To solve the above problem, a diffusion barrier layer is formed … ” and [0013] cited “ The titanium silicide layer, which has been used as a conventional diffusion barrier layer, can function as the diffusion barrier by a temperature of about 450
°
C. ”, therefore, Hong teaches titanium silicide layer as a conventional diffusion barrier layer to achieve low contact resistivity.
Finally, “ a metal selected from vanadium ” ( i.e. the 3rd element in tri-element barrier metal layers ) is taught by Cabral, not Hong.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817