DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 01/16/2026. Claim 7 is amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5, 9, 12, 13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023).
Regarding claim 1, Yu, in at least one embodiment, teaches: A method of forming a semiconductor structure (Yu 200, fig 2, ¶0049), the method comprising:
selectively depositing a blocking layer (Yu 230, ¶0050) on a first surface (Yu 222) of a substrate (Yu 205) by exposing the substrate to a first precursor (Yu R′≡R″, “unsaturated hydrocarbon”, ¶0050, under a broadest reasonable interpretation (BRI), and wherein the applicant discloses a precursor is: “a substance with a species capable of reacting with the substrate surface or material on the substrate surface in a surface reaction”, spec ¶0016, R′≡R″ is used in a surface reaction to form blocking layer 230)(Yu 260, fig 2), wherein the substrate has at least one feature (Yu 206) comprising the first surface (Yu 222) and a second surface (Yu 207, 208)(Yu fig 2);
selectively depositing a liner (Yu 240, under a BRI of a “liner”, Yu 240 at least lines a portion of 206, further, applicant discloses that suitable materials for a liner include “TaN” and “the liner 260 has the same properties as the barrier layer 215”, spec ¶0054, and similar to Yu 140 ¶0044, “140 comprises … tantalum nitride”) on the second surface (Yu fig 2) by exposing the substrate to a second precursor (Yu ¶0051, “metal precursor”)(Yu 270, fig 2); and
removing the blocking layer (Yu 280, fig 2, ¶0052),
wherein the first surface (Yu 222) comprises a metal (Yu 220, “metallic material”, ¶0028-0029, 0022), and the second surface comprises a dielectric material (Yu 210, “non-metallic material” and “dielectric material” are interchangeable, ¶0022, 0031).
Yu does not teach: a self-assembled monolayer (SAM), the first precursor comprising a metal-carbonyl bond; removing the self-assembled monolayer (SAM).
Gracias, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a method of forming a self-assembled monolayer (SAM)(Gracias 410)(Gracias fig 4a, 4b) comprising a metal-carbonyl bond (Gracias Col 3, Lines 28-37); and removing the self-assembled monolayer (SAM)(Gracias 605, fig 6a, 6b, Col 4, Lines 25-33).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the blocking layer of Yu to comprise a SAM, formed by a precursor comprising a metal-carbonyl bond, as taught by Gracias, in order to prevent formation of the blocking layer on the second surface (Gracias Col 3, Lines 28-37), thereby allowing further treatment of the second surface without requiring a removal step (Gracias Col 3, Lines 28-37), and/or in order to protect the first surface during subsequent processing (Gracias Col 4, Lines 53-65).
Regarding claim 2, Yu in view of Gracias teaches: The method of claim 1, wherein selectively depositing the self-assembled monolayer (SAM)(Yu 230 as modified by Gracias 410) comprises forming the SAM on the first surface (Yu 222) and not on the second surface (Yu 207, 208)(Yu 260, fig 2, ¶0050, similar to Gracias fig 4b, Col 3, Lines 28-37).
Regarding claim 3, Yu in view of Gracias teaches: The method of claim 1, wherein selectively depositing the liner (Yu 240) comprises forming the liner on the second surface (Yu 207, 208) and not on the first surface (Yu 222)(Yu 270, fig 2, ¶0051).
Regarding claim 5, Yu in view of Gracias teaches: The method of claim 1, wherein the first surface (Yu 222) comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), and molybdenum (Mo)(Yu ¶0028-0029, “… copper, … cobalt, tungsten, ruthenium, molybdenum …”).
Regarding claim 9, Yu in view of Gracias teaches: The method of claim 1, wherein the at least one feature (Yu 206) comprises one or more of a trench and a via (Yu ¶0049, “circular via … a trench”).
Regarding claim 12, Yu in view of Gracias teaches: The method of claim 1, wherein the first precursor (Yu R′≡R″ as modified by Gracias 410) comprises at least one unsaturated group (Yu, “unsaturated hydrocarbon”, ¶0050).
Regarding claim 13, Yu in view of Gracias teaches: The method of claim 1, wherein the first precursor (Yu R′≡R″ as modified by Gracias 410) comprises at least one alcohol group (Gracias Col 3, Lines 28-37, “alcohols”).
Regarding claim 16, Yu in view of Gracias teaches: The method of claim 1, wherein the first precursor (Yu R′≡R″ as modified by Gracias 410) comprises at least one amine group (Gracias Col 3, Lines 28-37, “amines”).
Regarding claim 17, Yu teaches: A method of forming a semiconductor structure (Yu 200, fig 2, ¶0049), the method comprising:
selectively depositing a blocking layer (Yu 230, ¶0050) on a first surface (Yu 222) of a substrate (Yu 205) by exposing the substrate to a first precursor (Yu R′≡R″, “unsaturated hydrocarbon”, ¶0050, under a broadest reasonable interpretation (BRI), and wherein the applicant discloses a precursor is: “a substance with a species capable of reacting with the substrate surface or material on the substrate surface in a surface reaction”, spec ¶0016, R′≡R″ is used in a surface reaction to form blocking layer 230)(Yu 260, fig 2), wherein the substrate has at least one feature (Yu 206) comprising the first surface (Yu 222) and a second surface (Yu 207, 208)(Yu fig 2);
selectively depositing a liner (Yu 240, under a BRI of a “liner”, Yu 240 at least lines a portion of 206, further, applicant discloses that suitable materials for a liner include “TaN” and “the liner 260 has the same properties as the barrier layer 215”, spec ¶0054, and similar to Yu 140 ¶0044, “140 comprises … tantalum nitride”) on the second surface (Yu fig 2) by exposing the substrate to a second precursor (Yu ¶0051, “metal precursor”)(Yu 270, fig 2); and
removing the blocking layer (Yu 280, fig 2, ¶0052),
wherein the first surface (Yu 222) comprises one or more of copper, cobalt, ruthenium, tungsten or molybdenum (Yu 220, ¶0029, “copper, … cobalt, tungsten, ruthenium, molybdenum …”), and the second surface comprises a dielectric material (Yu 210, “non-metallic material” and “dielectric material” are interchangeable, ¶0022, 0031).
Yu does not teach: a self-assembled monolayer (SAM), the first precursor comprising a metal-carbonyl bond and at least one amine group; removing the self-assembled monolayer (SAM).
Gracias, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a method of forming a self-assembled monolayer (SAM)(Gracias 410)(Gracias fig 4a, 4b) comprising a metal-carbonyl bond (Gracias Col 3, Lines 28-37) and at least one amine group (Gracias Col 3, Lines 28-37, “amines”); and removing the self-assembled monolayer (SAM)(Gracias 605, fig 6a, 6b, Col 4, Lines 25-33).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the blocking layer of Yu to comprise a SAM, formed by a precursor comprising a metal-carbonyl bond and at least one amine group, as taught by Gracias, in order to prevent formation of the blocking layer on the second surface (Gracias Col 3, Lines 28-37), thereby allowing further treatment of the second surface without requiring a removal step (Gracias Col 3, Lines 28-37), and/or in order to protect the first surface during subsequent processing (Gracias Col 4, Lines 53-65).
Regarding claim 18, Yu in view of Gracias teaches: The method of claim 17, wherein selectively depositing the self-assembled monolayer (SAM)(Yu 230 as modified by Gracias 410) comprises forming the SAM on the first surface (Yu 222) and not on the second surface (Yu 207, 208)(Yu 260, fig 2, ¶0050, similar to Gracias fig 4b, Col 3, Lines 28-37).
Regarding claim 19, Yu in view of Gracias teaches: The method of claim 17, wherein selectively depositing the liner (Yu 240) comprises forming the liner on the second surface (Yu 207, 208) and not on the first surface (Yu 222)(Yu 270, fig 2, ¶0051).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Clark et al (US 20190295903 A1, hereafter Clark).
Regarding claim 4, Yu in view of Gracias teaches: The method of claim 1.
Yu in view of Gracias does not explicitly teach: cleaning the substrate before depositing the self-assembled monolayer (SAM) to form a substrate surface substantially free of oxide.
Clark, in the same field of endeavor of semiconductor device manufacturing, teaches: cleaning (Clark ¶0049, 0058) a substrate (Clark 210, 304)(Clark fig 2A, 2B) before depositing a self-assembled monolayer (SAM)(Clark 240) to form a substrate surface (Clark 230) substantially free of oxide (Clark ¶0049, 0050, 0058, “oxide-free metal surface”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Yu in view of Gracias to include a cleaning step before depositing the SAM, such that a surface is substantially free of oxide, in order to improve surface selectivity of the SAM (Clark ¶0049).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Zhang et al (US 20150325467 A1, hereafter Zhang).
Regarding claim 6, Yu in view of Gracias teaches: The method of claim 1.
Yu in view of Gracias does not teach: further comprising densifying the liner.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: densifying a liner (Zhang 45, ¶0021, under a BRI of a “liner”, comprising “TaN”, similar to Yu 240, 140).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Yu in view of Gracias to include densifying the liner, as taught by Zhang, in order to reduce susceptibility to damage during subsequent processing (Zhang ¶0021).
Regarding claim 7, Yu in view of Gracias and Zhang teaches: The method of claim 6, wherein densifying the liner (Yu 240 as modified by Zhang 45) comprises physical vapor deposition (PVD)(Zhang ¶0021).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Suzuki et al (US 20060110530 A1, hereafter Suzuki) and Whelan et al (US 20060128142 A1, hereafter Whelan).
Regarding claim 8, Yu in view of Gracias teaches: The method of claim 1.
Yu in view of Gracias does not teach: depositing an adhesion layer on the first surface and on the liner after removing the self-assembled monolayer (SAM).
Yu, in at least one embodiment, further teaches: a first conductive fill (Yu 220); and forming a second conductive fill (Yu 250) on a first surface (Yu 222) and on a liner (Yu 240) after removing a barrier layer (Yu230)(Yu fig 2).
Suzuki, in the same field of endeavor of semiconductor device manufacturing, teaches: depositing an adhesion layer (Suzuki 460, ¶0055, “Ru metal”, ¶0005, “good adhesion between the Cu and the Ru layers”, under a BRI of “an adhesion layer”, 460 is at least capable of providing adhesion between 450 and 470) on a liner (Suzuki 450, ¶0055, under a BRI of a “liner”, comprising “TaN”, similar to Yu 240)(Suzuki fig 4B, ¶0055).
Whelan, in the same field of endeavor of semiconductor device manufacturing, teaches: depositing a seed layer (Whelan 7) on a first surface (Whelan 4) and on a second self-assembled monolayer (SAM)(Whelan 8) after removing a first SAM(Whelan 13)(Whelan fig 3D, ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Yu in view of Gracias, such that an adhesion layer is deposited on the first surface and on the liner after removing the self-assembled monolayer (SAM), in order to improve adhesion between the liner and a second conductive fill (Suzuki ¶0005), while preventing increased electrical resistance between the first and second conductive fills (Whelan ¶0010, 0050).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Tsai et al (US 20200006230 A1, hereafter Tsai).
Regarding claim 10, Yu in view of Gracias teaches: The method of claim 1, further comprising depositing a conductive material (Yu 250) in the at least one feature (Yu 206).
Yu in view of Gracias does not explicitly teach: by exposing the substrate to a third precursor, the third precursor comprising a metal.
Yu, in at least one embodiment, further teaches: depositing a conductive material (Yu 355) in an at least one feature (Yu 306) by chemical vapor deposition (CVD)(Yu ¶0062).
Tsai, in the same field of endeavor of semiconductor device manufacturing, teaches: depositing a conductive material (Tsai 132, ¶0032, 0019) in the at least one feature (Tsai 122)(Tsai fig 3B, 3C) by exposing a substrate (Tsai 10, 12) to a third precursor, the third precursor comprising a metal (Tsai ¶0032, “deposition precursors (for example, metal precursors and/or reactants)”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the deposition step of Yu in view of Gracias to include a third precursor, and for the third precursor to comprise a metal, in order to selectively deposit the conductive material within the first feature, thereby preventing growth on dielectric surfaces (Tsai ¶0032).
Regarding claim 11, Yu in view of Gracias and Tsai teaches: The method of claim 10, wherein depositing the conductive material (Yu 250, similar to Tsai 132) comprises one or more of a bottom-up gap fill (Tsai ¶0032) and a conformal gap fill.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Abelson et al (US 11584986 B1, hereafter Abelson).
Regarding claim 14, Yu in view of Gracias teaches: The method of claim 1.
Yu in view of Gracias does not explicitly teach: wherein the first precursor comprises at least one ketone group.
Abelson, in the same field of endeavor of semiconductor device manufacturing, teaches: selectively forming a layer using an inhibitor agent comprising a ketone group (Abelson Col 2, Lines 4-20).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first precursor of Yu in view of Gracias to include a ketone group, in order to reduce nucleation sites available during subsequent processing (Abelson Col 2, Lines 44-46).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable functional groups, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 1 above, and further in view of Rachmady et al (US 20090272965 A1, hereafter Rachmady).
Regarding claim 15, Yu in view of Gracias teaches: The method of claim 1.
Yu in view of Gracias does not explicitly teach: wherein the first precursor comprises at least one ester group.
Rachmady, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting hydrophobicity of a layer (Rachmady 471, ¶0031-0033) with a functional group (Rachmady 471, ¶0031-0033, “organo esters”) to prevent dielectric nucleation.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first precursor of Yu in view of Gracias to include an ester group, in order to adjust a hydrophobicity of the SAM, thereby preventing the liner from forming on the SAM (Rachmady ¶0031-0033).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to choose any number of suitable functional groups, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (MPEP 2144.07).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 20200350204 A1, hereafter Yu, disclosed in IDS dated 01/23/2023) in view of Gracias et al (US 6905958 B2, hereafter Gracias, disclosed in IDS dated 01/23/2023) as applied to claim 17 above, further in view of Zhang et al (US 20150325467 A1, hereafter Zhang), Suzuki et al (US 20060110530 A1, hereafter Suzuki), and Whelan et al (US 20060128142 A1, hereafter Whelan).
Regarding claim 20, Yu in view of Gracias teaches: The method of claim 17.
Yu in view of Gracias does not teach: further comprising densifying the liner by physical vapor deposition.
Zhang, in the same field of endeavor of semiconductor device manufacturing, teaches: densifying a liner (Zhang 45, ¶0021, under a BRI of a “liner”, comprising “TaN”, similar to Yu 240, 140) by physical vapor deposition (Zhang ¶0021, “PVD”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Yu in view of Gracias to include densifying the liner by PVD, as taught by Zhang, in order to reduce susceptibility to damage during subsequent processing (Zhang ¶0021).
Yu in view of Gracias and Zhang does not teach: depositing an adhesion layer on the first surface and on the liner.
Yu, in at least one embodiment, further teaches: a first conductive fill (Yu 220); and forming a second conductive fill (Yu 250) on a first surface (Yu 222) and on a liner (Yu 240) after removing a barrier layer (Yu230)(Yu fig 2).
Suzuki, in the same field of endeavor of semiconductor device manufacturing, teaches: depositing an adhesion layer (Suzuki 460, ¶0055, “Ru metal”, ¶0005, “good adhesion between the Cu and the Ru layers”, under a BRI of “an adhesion layer”, 460 is at least capable of providing adhesion between 450 and 470) on a liner (Suzuki 450, ¶0055, under a BRI of a “liner”, comprising “TaN”, similar to Yu 240)(Suzuki fig 4B, ¶0055).
Whelan, in the same field of endeavor of semiconductor device manufacturing, teaches: depositing a seed layer (Whelan 7) on a first surface (Whelan 4) and on a second self-assembled monolayer (SAM)(Whelan 8) after removing a first SAM(Whelan 13)(Whelan fig 3D, ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Yu in view of Gracias, such that an adhesion layer is deposited on the first surface and on the liner, in order to improve adhesion between the liner and a second conductive fill (Suzuki ¶0005), while preventing increased electrical resistance between the first and second conductive fills (Whelan ¶0010, 0050).
Response to Arguments
Applicant's arguments filed 01/16/2026 have been fully considered but they are not persuasive.
Regarding claims 1-20, the applicant argues at page 8:
As recognized by one of skill in the art, none of these species disclosed by Gracias comprises a metal or suggests a metal- carbonyl bond. … Gracias does not disclose, teach, or suggest any use of a precursor comprising a metal, let alone a metal-carbonyl bond to selectively deposit a self- assembled monolayer (SAM) on a first surface of a substrate. Thus, Gracias does not remedy the deficiencies of Yu in this regard.
Examiner’s response:
The Examiner respectfully disagrees. It appears that the applicant is arguing that the first precursor must contain a metal atom within the molecule.
However, claim 1 requires only that the first precursor to comprise “a metal-carbonyl bond” – this does not restrict the compound class or molecular context, but instead is only requires there exists a bond between a metal and a carbonyl group. Under a broadest reasonable interpretation, Garcias teaches the claimed limitation. Specifically, Garcias lists “carbonyls” as suitable molecules used for forming SAMs on metals such as copper or gold (Garcias Col 3, Lines 28-34), and teaches that the SAM is formed by chemisorption on a coper conductor surface (Garcias 210, Col 2, Lines 43-46, Col 3, Lines 49-52). Chemisorption between the carbonyl-containing precursor and the copper surface forms a bond between a metal and a carbonyl group, and is therefore a “metal-carbonyl bond”. Therefore, the limitation of “the first precursor comprising a metal-carbonyl bond” is met. (See MPEP 2111.01I and 2111.01II)
Additionally, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818