DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Species III (claims 1-2, 5-17, and 21-23 - Fig. 18) in the reply filed on 01/20/2026 is acknowledged. The reply from applicant is incomplete because applicant is silent to elect the Species with traverse or without traverse, and the arguing search burden is not a valid argument either, thus the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bitz et al. (U.S 2018/0130773 A1).
As to claim 1, Bitz et al. disclose in Fig. 4B a package structure, comprising:
a circuit substrate (“package substrate” 108) (Fig. 4B, para. [0018]-[0019]);
a package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d, Fig. 4B, para. [0017]), disposed on and electrically connected with the circuit substrate (“package substrate” 108) (Fig. 4B, para. [0017]-[0021]); and
a molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404), disposed over the circuit substrate (“package substrate” 108) and covering at least a top surface of the circuit substrate (“package substrate” 108) (Fig. 4B, para. [0024], [0032]),
wherein the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) includes a first portion (“first molded peripheral structure” 138) wrapping around sidewalls of the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and having a first thickness (Fig. 4B, para. [0024]-[0025]) and
a second portion (“second molded peripheral structure” 140) surrounding the first portion (“first molded peripheral structure” 138) and connected with the first portion (“first molded peripheral structure” 138) (Fig. 4B, para. [0024], [0026]),
the first thickness of the first portion (“first molded peripheral structure” 138) is larger than a second thickness of the second portion (“second molded peripheral structure” 140) (see Fig. 4B),
and a top surface of the first portion (“first molded peripheral structure” 138) of the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) is higher than a top surface of the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) (see Fig. 4B).
As to claim 2, as applied to claim 1 above, Bitz et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) includes a third portion (“first molded overlay” 402) disposed on the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and connected with the first portion (“first molded peripheral structure” 138), the third portion (“first molded overlay” 402) has a third thickness smaller than the first thickness (the first thickness of 138) (see Fig. 4B).
As to claim 5, as applied to claims 1 and 2 above, Bitz et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein a top surface of the third portion (“first molded overlay” 402) is higher than a top surface of the second portion (“second molded peripheral structure” 140) (see Fig. 4B).
As to claim 6, as applied to claim 1 above, Bitz et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein a top surface of the second portion (“second molded peripheral structure” 140) is lower than the top surface of the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) (Fig. 4B).
As to claim 7, as applied to claim 1 above, Bitz et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) includes a first semiconductor die (“semiconductor dies” 104/104a-104d are memory dies, para. [0020]) and a second semiconductor die (“semiconductor die” 106 is a logic die, para. [0020]), the first and second semiconductor dies (104/(104a-104d), 106) perform different functions (Fig. 4B, para. [0020]).
As to claim 10, as applied to claim 1 above, Bitz et al. disclose in Fig. 4B all claimed limitations including the structure further comprising a thermal dissipating module (“heat spreader” 126) disposed on the package element (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and exposed from the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) (Fig. 4B, para. [0022], [0025]-[0026]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bitz et al. (U.S 2018/0130773 A1) in view of Tsai et al. (U.S 2021/0066211 A1).
As to claims 8 and 9, as applied to claims 1 and 7 above, Bitz et al. disclose in Fig. 4B all claimed limitations except for the limitation: wherein the molding layer has an opening exposing the first semiconductor die of the package element; and wherein the molding layer has an opening exposing the first semiconductor die and the second semiconductor die of the package element.
Tsai et al. disclose in Fig. 14 a package structure comprising: the molding layer (“first underfill” 112) has an opening exposing the first semiconductor die (22) of the package element (comprising “semiconductor dies” 22, 21), or exposing the first semiconductor die (22) and the second semiconductor die (21) of the package element (comprising “semiconductor dies” 22, 21) (Fig. 14, para. [0029]).
Therefore, it would have been obvious to a person having ordinary in the art at the time the invention was made to modify reference of Bitz et al. by having the molding layer which has an opening exposing the first semiconductor die of the package element or exposing the first semiconductor die and the second semiconductor die of the package element, as taught by Tsai et al., in order to directly connect the semiconductor dies of the package with a thermal dissipating module for releasing heat from the package so as to maintain performance, reliability, and longevity of electronic structure.
Claims 11-14, 17, and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bitz et al. (U.S 2018/0130773 A1) in view of PATIL et al. (U.S 2022/0328417 A1).
As to claim 11, Bitz et al. disclose in Fig. 4B a package structure, comprising: a circuit substrate (“package substrate” 108) (Fig. 4B, para. [0018]-[0019]); a package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d, Fig. 4B, para. [0017]), disposed on and electrically connected with the circuit substrate (“package substrate” 108) (Fig. 4B, para. [0017]-[0021]), wherein the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) includes a first semiconductor die (“semiconductor dies” 104/104a-104d are memory dies, para. [0020]) and a second semiconductor die (“semiconductor die” 106 is a logic die, para. [0020]) (Fig. 4B, para. [0020]);
a molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404), disposed over the circuit substrate (“package substrate” 108) and covering the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d), and at least a top surface of the circuit substrate (“package substrate” 108) (Fig. 4B, para. [0024]-[0026], [0031]-[0032]), wherein the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) includes
a first portion (“first molded peripheral structure” 138) wrapping around sidewalls of the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and having a first thickness (Fig. 4B, para. [0024]-[0025]), and
a second portion (“second molded peripheral structure” 140) surrounding the first portion (“first molded peripheral structure” 138) and connected with the first portion (“first molded peripheral structure” 138) (Fig. 4B, para. [0024], [0026]), the first thickness of the first portion is larger than a second thickness of the second portion (“second molded peripheral structure” 140) (see Fig. 4B), and
the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) has a fourth thickness (a thickness of 106 & stack of 104a-104d) smaller than the first thickness of the first portion (“first molded peripheral structure” 138) of the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) but larger than the second thickness (the second thickness of 140) (see Fig. 4B).
Bitz et al. do not disclose the structure comprising: at least one passive component, disposed on and electrically connected with the circuit substrate; and a molding layer, disposed over the circuit substrate, covering the passive component.
PATIL et al. disclose in Fig. 2 a structure comprising: at least one passive component (211), disposed on and electrically connected with the circuit substrate (202) (Fig. 2, para. [0023]-[0024]); and a molding layer (“encapsulation layer” 208), disposed over the circuit substrate (202), covering the passive component (211) (Fig. 2, para. [0023], [0027]).
Therefore, it would have been obvious to a person having ordinary in the art at the time the invention was made to modify reference of Bitz et al. by having at least one passive component, disposed on and electrically connected with the circuit substrate; and a molding layer, disposed over the circuit substrate, covering the passive component, as taught by PATIL et al., in order to improve power distribution network (PDN) performance of the package (see para. [0023] in PATIL et al.).
As to claim 12, as applied to claim 11 above, Bitz et al. and PATIL et al. disclose all claimed limitations including the package structure further comprising a thermal dissipating module (comprising “thermal interface features” 124 & “heat spreader” 126) disposed on the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and exposed from the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) (Fig. 4B, para. [0022], [0025]-[0026], [0030] in Bitz).
As to claim 13, as applied to claims 11 and 12 above, Bitz et al. and PATIL et al. disclose all claimed limitations including the limitation: wherein the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) includes a third portion (“first molded overlay” 402) disposed on the thermal dissipating module (comprising “thermal interface features” 124 & “heat spreader” 126) and connected with the first portion (“first molded peripheral structure” 138), the third portion (“first molded overlay” 402) has a third thickness smaller than the first thickness (the first thickness of 138) (see Fig. 4B, para. [0022] in Bitz).
As to claim 14, as applied to claims 11-13 above, Bitz et al. and PATIL et al. disclose all claimed limitations including the limitation: wherein a top surface of the first and third portions (138, 402) is coplanar and flushes with a top surface of the heat dissipating module (comprising “thermal interface features” 124 & “heat spreader” 126) (Fig. 4B in Bitz).
As to claim 17, as applied to claims 11 and 12 above, Bitz et al. and PATIL et al. disclose all claimed limitations including the limitation: wherein a top surface of the first portion (138) is coplanar and flushes with a top surface of the heat dissipating module (comprising “thermal interface features” 124 & “heat spreader” 126), and a top surface of the second portion (140) is lower than the top surface of the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) (Fig. 4B in Bitz).
As to claim 21, Bitz et al. disclose in Fig. 4B a structure, comprising:
a wiring substrate (“package substrate” 108) (Fig. 4B, para. [0018]-[0019]);
a package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d, Fig. 4B, para. [0017]), disposed on and electrically connected with the wiring substrate (“package substrate” 108) (Fig. 4B, para. [0017]-[0021]),
wherein the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) includes a first die (“semiconductor dies” 104/104a-104d are memory dies, para. [0020]) and a second die (“semiconductor die” 106 is a logic die, para. [0020]) different from the first die (“semiconductor dies” 104/104a-104d are memory dies) (Fig. 4B, para. [0020]);
an underfill (“MUF material “ 136) disposed between the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and the wiring substrate (“package substrate” 108) (Fig. 4B, para. [0014], [0023], [0028]);
a molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404), disposed over the wiring substrate (“package substrate” 108) and covering the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d), the underfill (“MUF material “ 136), and at least a top surface of the wiring substrate (“package substrate” 108) (Fig. 4B, para. [0024]-[0026], [0031]-[0032]),
wherein the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) includes a first portion (“first molded peripheral structure” 138) with a first thickness wrapping around sidewalls of the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) (Fig. 4B, para. [0024]-[0025]), and
a second portion (“second molded peripheral structure” 140) with a second thickness surrounding the first portion (“first molded peripheral structure” 138) and connected with the first portion (“first molded peripheral structure” 138) (Fig. 4B, para. [0024], [0026]), the first thickness is larger than the second thickness of the second portion (“second molded peripheral structure” 140) (see Fig. 4B), and
the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) has a third thickness (a thickness of 106 & stack of 104a-104d) smaller than the first thickness of the first portion (“first molded peripheral structure” 138) of the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) (see Fig. 4B).
Bitz et al. do not disclose the structure comprising: at least one passive component, disposed on and electrically connected with the wiring substrate; and a molding layer, disposed over the wiring substrate, covering the passive component.
PATIL et al. disclose in Fig. 2 a structure comprising: at least one passive component (211), disposed on and electrically connected with the wiring substrate (202) (Fig. 2, para. [0023]-[0024]); and a molding layer (“encapsulation layer” 208), disposed over the wiring substrate (202), covering the passive component (211) (Fig. 2, para. [0023], [0027]).
Therefore, it would have been obvious to a person having ordinary in the art at the time the invention was made to modify reference of Bitz et al. by having at least one passive component, disposed on and electrically connected with the wiring substrate; and a molding layer, disposed over the wiring substrate, covering the passive component, as taught by PATIL et al., in order to improve power distribution network (PDN) performance of the package (see para. [0023] in PATIL et al.).
As to claim 22, as applied to claim 21 above, Bitz et al. and PATIL et al. disclose all claimed limitations including the structure further comprising: a thermal dissipating module (“heat spreader” 126) disposed on the package (comprising “semiconductor die” 106 and “stack” 102 including “semiconductor dies” 104a-104d) and exposed from the molding layer (comprising “first and second molded peripheral structures” 138, 140 & “first and second molded overlays” 402, 404) (Fig. 4B, para. [0022], [0030] in Bitz et al.).
Claim(s) 15-16 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bitz et al. (U.S 2018/0130773 A1) in view of PATIL et al. (U.S 2022/0328417 A1) as applied to claim 21 above, and further in view of KANG et al. (U.S 2019/0371731 A1).
As to claims 15 and 16, as applied to claims 11 and 12 above, Bitz et al. and PATIL et al. disclose all claimed limitations except for the structure further comprising: a shielding layer covering the molding layer and sidewalls of the circuit substrate and the heat dissipating module, wherein the shielding layer has an opening, exposing the heat dissipating module.
KANG et al. disclose in Fig. 21 a structure comprising: a shielding layer (149) covering the molding layer (“encapsulant” 150) and sidewalls of the circuit substrate (comprising 145a, 145b) and the heat dissipating module (“heat sink” 195), wherein the shielding layer (149) has an opening, exposing the heat dissipating module (195) (Fig. 21, para. [0073]-[0074], [0084], [0086], [0132]-[0134]).
Therefore, it would have been obvious to a person having ordinary in the art at the time the invention was made to modify reference of Bitz et al. with PATIL et al. by having a shielding layer covering the molding layer and sidewalls of the circuit substrate and the heat dissipating module, wherein the shielding layer has an opening, exposing the heat dissipating module, as taught by KANG et al., in order to prevent external interferences (noises), so as to improve stable signals for the package.
As to claim 23, as applied to claims 21 and 22 above, Bitz et al. and PATIL et al. disclose all claimed limitations except for the structure further comprising: a shielding layer covering the molding layer and sidewalls of the wiring substrate and the heat dissipating module.
KANG et al. disclose in Fig. 21 a structure comprising: a shielding layer (149) covering the molding layer (“encapsulant” 150) and sidewalls of the wiring substrate (comprising 145a, 145b) and the heat dissipating module (“heat sink” 195) (Fig. 21, para. [0073]-[0074], [0084], [0086], [0132]-[0134]).
Therefore, it would have been obvious to a person having ordinary in the art at the time the invention was made to modify reference of Bitz et al. with PATIL et al. by having a shielding layer covering the molding layer and sidewalls of the wiring substrate and the heat dissipating module, as taught by KANG et al., in order to prevent external interferences (noises), so as to improve stable signals for the package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Hou et al. (U.S 2021/0242100 A1), Chen et al. (U.S 2021/0082894 A1), and Shen et al. (US 2021/0225806 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 14, 2026
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