Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed 2/9/2026 has been entered. Claims 1, 10, 15 are amended. Claim 6 is canceled. Claims 1 – 5, 7 – 20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 7 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang ( Pub. No. US 20180374750 A1 ), hereinafter Zhang.
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Regarding Independent Claim 1 (Currently Amended), Zhang teaches a method of fabricating fully self-aligned vias ( Zhang, [0006], One or more embodiments of the disclosure are directed to methods to provide a self-aligned via ), the method comprising:
filling openings of a first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) and first vias ( Zhang, [0061], trenches 104; FIG. 8A / 8B, 801; [0095], a gap 801 ) within a first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103; FIG. 6A / 6B to FIG. 8A / 8B, 601; [0084], self-aligned selective growth pillars 601 )
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) is formed underneath the first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) and on a first dielectric layer ( Zhang, FIB. 1B, 102; [0061], insulating layer 102, the part at the bottom ) formed of the low-k dielectric material ( Zhang, [0064], low-k dielectric ), and
the first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) comprises a lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) deposited on the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) and an upper hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) deposited on the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 );
planarizing ( Zhang, [0074], chemical-mechanical polishing (“CMP”) technique; FIG. 5A / 5B ) the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 ) and the lower hardmask ( Zhang, FIG. 5A / 5B, 301 planarized with 102 ), removing the upper hardmask ( Zhang, FIG. 4, 301 on 102 ) ( Zhang, [0074], portions of the conductive layer and the base layer are removed to even out top portions of the conductive lines 103 with top portions of the insulating layer 102 using a chemical-mechanical polishing (“CMP”) technique );
selectively removing ( Zhang, [0049], plasma system ) the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) and forming second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) within the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 );
depositing ( Zhang, [0067], deposition techniques ) an etch stop layer ( Zhang, FIG. 3, 301; [0079], liner 301 ) in the second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) and on the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 );
filling ( Zhang, [0067], deposition techniques ) the second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) over the etch stop layer ( Zhang, FIG. 3, 301; [0079], liner 301 ) with the low-k dielectric material ( Zhang, [0064], low-k dielectric ), forming a third dielectric layer ( Zhang, FIG. 4, 401 );
planarizing ( Zhang, [0074], chemical-mechanical polishing (“CMP”) technique ) the third dielectric layer ( Zhang, FIG. 4, 401 );
forming ( Zhang, [0054], litho-etch sequence ) third vias ( Zhang, FIG. 8A, via between 701; FIG. 10 A, via between 601 ) in the third dielectric layer ( Zhang, FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 );
filling ( Zhang, [0067], deposition techniques ) the third vias ( Zhang, FIG. 8A, via between 701; FIG. 10 A, via between 601 ) with second metal forming a second metal layer ( Zhang, FIG. 10A, 1001 ) in the third vias ( Zhang, FIG. 8A, via between 701; FIG. 10 A, via between 601 ) and on the third dielectric layer (Zhang, FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601);
planarizing ( Zhang, FIG. 10A to FIG. 11A; [0074], chemical-mechanical polishing (“CMP”) technique ) the second metal layer ( Zhang, FIG. 10A, 1001 ) and the third dielectric layer ( Zhang, FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 ) and removing portions of the second metal layer ( Zhang, FIG. 10A, 1001 ) outside the third vias ( Zhang, FIG. 8A, via between 701; FIG. 10 A, via between 601 );
forming ( Zhang, [0067], deposition techniques ) a third metal layer ( Zhang, FIG. 17A, 1701) of third metal on the second metal layer ( Zhang, FIG. 17A, 1301 ) and the third dielectric layer ( Zhang, FIG. 17A, 1001 );
forming ( Zhang, [0067], deposition techniques ) a second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ) on the third metal layer ( Zhang, FIG. 17A, 1701);
forming ( Zhang, [0054], litho-etch sequence ) fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 ) in the third metal layer ( Zhang, FIG. 17A, 1701);
partially etching ( Zhang, FIG. 17A to FIG. 18A ) the second metal layer ( Zhang, FIG. 17A, 1301 ) in the fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 );
filling ( Zhang, [0067], deposition techniques ) the fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 ) with the low-k dielectric material ( Zhang, [0064], low-k dielectric ), forming a fourth dielectric layer ( Zhang, FIG. 20A, 1801, 2001 ); and
planarizing ( Zhang, [0074], chemical-mechanical polishing (“CMP”) technique ) the fourth dielectric layer ( Zhang, FIG. 20A, 1801, 2001 ), and partially removing the second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ).
Zhang does not explicitly disclose:
subsequent to filling the openings and the first vias, planarizing the second dielectric layer and the lower hardmask, removing the upper hardmask;
However, Zhang teaches:
the processes of FIG. 3 – FIG. 5A/5B;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the processes of FIG. 3 – FIG. 5A/5B in Zhang, to create that subsequent to filling the openings and the first vias ( i.e. filling 401 in FIG. 4 ), planarizing the second dielectric layer and the lower hardmask ( i.e. chemical-mechanical polishing (CMP) planarizing the top surface of 102 and 301 and 401 in FIG. 5A/5B ), removing the upper hardmask ( i.e. removing the 301 on 102 in FIG. 5A/5B ); such that an alternative process for implementing self-aligned vias could be implemented, since this is within the skill level of one in the art.
Regarding Claim 2 (Previously Presented), Zhang teaches the method as claimed in claim 1, wherein
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the second metal layer ( Zhang, FIG. 10A, 1001 ) comprises tungsten (W) ( Zhang, [0072], tungsten (W) ), and
the third metal layer ( Zhang, FIG. 17A, 1701) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 3 (Previously Presented), Zhang teaches the method as claimed in claim 1, wherein
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the second metal layer ( Zhang, FIG. 10A, 1001 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ), and
the third metal layer ( Zhang, FIG. 17A, 1701) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 4 (Original), Zhang teaches the method as claimed in claim 1, wherein
the low-k dielectric material ( Zhang, [0064], low-k dielectric ) comprises silicon containing flowable dielectric material ( Zhang, [0090], flowable silicon oxide (FSiOx) layer ).
Regarding Claim 5 (Previously Presented), Zhang teaches the method as claimed in claim 1, wherein
the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) comprises silicon nitride (Si3N4) ( Zhang, [0065], silicon nitride ), and
the upper hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) comprises tetra-ethyl-orthosilicate (TEOS) ( Zhang, [0065], phosphosilicate glass, Fluorosilicate (SiOF) glass, organosilicate glass (SiOCH) ).
Regarding Claim 7 (Original), Zhang teaches the method as claimed in claim 1, wherein
the second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ) comprises a lower hardmask ( conductive lines 103 ) , and an upper hardmask ( Zhang, FIG. 17A, 20A, 1503 ) deposited on the lower hardmask ( Zhang, FIG. 17A, 20A, 1501 ),
the lower hardmask ( Zhang, FIG. 17A, 20A, 1501 ) comprises silicon nitride (Si3N4) ( Zhang, [0065], silicon nitride ), and
the upper hardmask ( Zhang, FIG. 17A, 20A, 1503 ) comprises tetra-ethyl-orthosilicate (TEOS) ( Zhang, [0065], phosphosilicate glass, Fluorosilicate (SiOF) glass, organosilicate glass (SiOCH) ).
Regarding Claim 8 (Original), Zhang teaches the method as claimed in claim 1, wherein
the first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) and the second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ) each comprise amorphous silicon (a- Si) ( Zhang, [0059], amorphous silicon ).
Regarding Claim 9 (Original), Zhang teaches the method as claimed in claim 1, wherein
the etch stop layer ( Zhang, FIG. 3, 301; [0079], liner 301 ) comprises a layer comprising aluminum oxynitride (ALON) and a layer comprising silicon carbon nitride (SiCN) ( Zhang, [0080], liner 301 is an oxide, e.g., aluminum oxide (AlO); [0064], silicon nitride; [0092], silicon carbide ).
Regarding Independent Claim 10 (Currently Amended), Zhang teaches a nanostructure formed on a substrate, comprising:
a first dielectric layer ( Zhang, FIB. 1B, 102; [0061], insulating layer 102, the part at the bottom ) formed on a substrate;
a second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 ) disposed on the first dielectric layer ( Zhang, FIB. 1B, 102; [0061], insulating layer 102, the part at the bottom ), the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 ) having a plurality of first interconnect structures ( FIG. 2A, 202, via between 102 ) formed therein;
a third dielectric layer ( Zhang, FIG. 4, 401) disposed on the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 ), the third dielectric layer ( Zhang, FIG. 4, 401; FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 ) having a plurality of second interconnect structures ( FIG. 6A / 6B to 9A / 9B, 601; [0085], self-aligned selective growth pillars 601 are formed using the seed gap fill layer 401; [0086], In more specific embodiment, pillars 601 include tungsten oxide ) formed therein, wherein each of the plurality of second interconnect structures ( FIG. 6A / 6B to 9A / 9B, 601; [0085], self-aligned selective growth pillars 601 ) is self-aligned with a corresponding one of the plurality of first interconnect structures ( FIG. 2A, 202, via between 102; FIG. 8A, 801, via between 102 ), and a bottom surface of each of the plurality of second interconnect structures ( FIG. 6A / 6B to 9A / 9B, 601; [0085], self-aligned selective growth pillars 601) has width that is the same or narrower ( FIG. 8B, FIG. 9B, by viewing Y-Z plane or X-Z plane ) than a top surface of the corresponding one of the plurality of first interconnect structures ( FIG. 2A, 202, via between 102; FIG. 8A, 801, via between 102 ); and
a fourth dielectric layer disposed on the third dielectric layer ( Zhang, FIG. 20A, 1001 ), the fourth dielectric layer having a plurality of third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) formed therein, wherein each of the plurality of third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) is self-aligned with one of the plurality of second interconnect structures ( Zhang, FIG. 20A, via 1801 between 102 ), and isolated from a neighboring third interconnect structure of the plurality of the third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) by the fourth dielectric layer ( Zhang, FIG. 20A, 1001 ).
Regarding Claim 11 (Original), Zhang teaches the nanostructure as claimed in claim 10, wherein:
the plurality of first interconnect structures ( FIG. 8A, 801, via between 102 ) comprise ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the plurality of second interconnect structures ( FIG. 8A, via between 701; FIG. 10A, via between 601 )comprise tungsten (W) ( Zhang, [0072], tungsten (W) ), and
the plurality of third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) comprise ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 12 (Original), Zhang teaches the nanostructure as claimed in claim 10, wherein:
the plurality of first interconnect structures ( FIG. 2A, 202, via between 102 ) comprise ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the plurality of second interconnect structures ( FIG. 8A, via between 701; FIG. 10A, via between 601 ) comprise ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ), and
the plurality of third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) comprise ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 13 (Original), Zhang teaches the nanostructure as claimed in claim 10, wherein:
the first, second, third, and fourth dielectric ( Zhang, FIG. 20A, 1801, 2001 ) layers each comprise silicon containing flowable dielectric material ( Zhang, [0090], flowable silicon oxide (FSiOx) layer ).
Regarding Claim 14 (Original), Zhang teaches the nanostructure as claimed in claim 10, further comprising:
a first barrier layer ( Zhang, FIG. 7A, 720; [0089], first mask 720 ) between the first dielectric layer ( Zhang, FIG. 7A, 710 ) and the plurality of first interconnect structures ( Zhang, FIG. 7A, via between 730 ); and
a second barrier layer ( Zhang, FIG. 15A, 1501; [0110], third insulating layer 1501) between the plurality of second interconnect structures ( Zhang, FIG. 15A, 1502; [0110], stack 1502 ) and the plurality of third interconnect structures ( Zhang, FIG. 15A, 1301 ).
Regarding Independent Claim 15 (Currently Amended), Zhang teaches a method of fabricating fully self-aligned vias ( Zhang, [0006], One or more embodiments of the disclosure are directed to methods to provide a self-aligned via ), the method comprising:
filling openings of a first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) and first vias ( Zhang, [0061], trenches 104; FIG. 8A / 8B, 801; [0095], a gap 801 ) within a first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103; FIG. 6A / 6B to FIG. 8A / 8B, 601; [0084], self-aligned selective growth pillars 601 ), with a low-k dielectric material ( Zhang, [0064], In some embodiments, insulating layer 102 is a low-k dielectric), forming a second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103; FIG. 10A, 1001; [0099], second insulating layer 1001 ), wherein:
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) is formed underneath the first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) and on a first dielectric layer ( Zhang, FIB. 1B, 102; [0061], insulating layer 102, the part at the bottom ) formed of the low-k dielectric material ( Zhang, [0064], low-k dielectric ), and
the first hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) comprises a lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) deposited on the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) and an upper hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) deposited on the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 );
planarizing ( Zhang, [0074], chemical-mechanical polishing (“CMP”) technique ) the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 ) and the lower hardmask ( Zhang, FIG. 5A / 5B, 301 planarized with 102 ), removing the upper hardmask ( Zhang, FIG. 4, 301 on 102 ) ( Zhang, [0074], portions of the conductive layer and the base layer are removed to even out top portions of the conductive lines 103 with top portions of the insulating layer 102 using a chemical-mechanical polishing (“CMP”) technique );
selectively removing ( Zhang, [0049], plasma system ) the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) and forming second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) within the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 );
depositing ( Zhang, [0067], deposition techniques ) an etch stop layer ( Zhang, FIG. 3, 301; [0079], liner 301 ) in the second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) and on the second dielectric layer ( Zhang, FIG. 1B, 102; [0061], insulating layer 102, the part between conductive lines 103 );
filling ( Zhang, [0067], deposition techniques ) the second vias ( Zhang, FIG. 2A, 202; [0077], trenches 202 are formed in the insulating layer 102 ) over the etch stop layer ( Zhang, FIG. 3, 301; [0079], liner 301 ) with the low-k dielectric material ( Zhang, [0064], low-k dielectric ), forming a third dielectric layer ( Zhang, FIG. 4, 401);
planarizing the third dielectric layer ( Zhang, FIG. 4, 401).
Zhang does not explicitly disclose:
subsequent to filling the openings and the first vias, planarizing the second dielectric layer and the lower hardmask, removing the upper hardmask;
However, Zhang teaches:
the processes of FIG. 3 – FIG. 5A/5B;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the processes of FIG. 3 – FIG. 5A/5B in Zhang, to create that subsequent to filling the openings and the first vias ( i.e. filling 401 in FIG. 4 ), planarizing the second dielectric layer and the lower hardmask ( i.e. chemical-mechanical polishing (CMP) planarizing the top surface of 102 and 301 and 401 in FIG. 5A/5B ), removing the upper hardmask ( i.e. removing the 301 on 102 in FIG. 5A/5B ); such that an alternative process for implementing self-aligned vias could be implemented, since this is within the skill level of one in the art.
Regarding Claim 16 (Previously Presented), Zhang teaches the method as claimed in claim 15, wherein
the low-k dielectric material ( Zhang, [0064], low-k dielectric ) comprises silicon containing flowable dielectric material ( Zhang, [0090], flowable silicon oxide (FSiOx) layer ),
the lower hardmask ( Zhang, FIG. 8A, 720; [0089], first mask 720 ) comprises silicon nitride (Si3N4) ( Zhang, [0065], silicon nitride ),
the upper hardmask ( Zhang, FIG. 7A, 730; [0089], second mask 730 ) comprises tetra-ethyl-orthosilicate (TEOS) ( Zhang, [0065], phosphosilicate glass, Fluorosilicate (SiOF) glass, organosilicate glass (SiOCH) ).
Regarding Claim 17 (Previously Presented), Zhang teaches the method as claimed in claim 15, further comprising:
forming ( Zhang, [0054], litho-etch sequence ) third vias ( Zhang, FIG. 8A, via between 701; FIG. 10A, via between 601 ) in the third dielectric layer ( Zhang, FIG. 4, 401; FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 );
filling ( Zhang, [0067], deposition techniques ) the third vias ( Zhang, FIG. 8A, via between 701; FIG. 10A, via between 601 ) with second metal forming a second metal layer ( Zhang, FIG. 10A, 1001 ) in the third vias ( Zhang, FIG. 8A, via between 701; FIG. 10A, via between 601 ) and on the third dielectric layer ( Zhang, FIG. 4, 401; FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 );
planarizing ( Zhang, FIG. 10A to FIG. 11A; [0074], chemical-mechanical polishing (“CMP”) technique ) the second metal layer ( Zhang, FIG. 10A, 1001 ) and the third dielectric layer ( Zhang, FIG. 4, 401; FIG. 7A, 701; [0089], an insulating layer 701; FIG. 10A, 601 ) and removing portions of the second metal layer ( Zhang, FIG. 10A, 1001 ) outside the third vias;
forming ( Zhang, [0067], deposition techniques ) a third metal layer (Zhang, FIG. 17A, 1701) of third metal on the second metal layer ( Zhang, FIG. 17A, 1301 ) and the third dielectric layer ( Zhang, FIG. 17A, 1001 );
forming ( Zhang, [0067], deposition techniques ) a second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ) on the third metal layer ( Zhang, FIG. 17A, 1701);
forming ( Zhang, [0054], litho-etch sequence ) fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 ) in the third metal layer ( Zhang, FIG. 17A, 1701) ;
partially etching ( Zhang, FIG. 17A to FIG. 18A ) the second metal layer ( Zhang, FIG. 17A, 1301 ) in the fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 );
filling ( Zhang, [0067], deposition techniques ) the fourth vias ( Zhang, FIG. 18A, via between (1503, 1502, 1501) and (1701, 1702); FIG. 19A, via between 1501 ) with the low-k dielectric material ( Zhang, [0064], low-k dielectric ), forming a fourth dielectric layer ( Zhang, FIG. 20A, 1801, 2001 ); and
planarizing ( Zhang, [0074], chemical-mechanical polishing (“CMP”) the fourth dielectric layer ( Zhang, FIG. 20A, 1801, 2001 ) and partially removing the second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ).
Regarding Claim 18 (Previously Presented), Zhang teaches the method as claimed in claim 17 wherein
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the second metal layer ( Zhang, FIG. 10A, 1001 ) comprises tungsten (W) ( Zhang, [0072], tungsten (W) ), and
the third metal layer ( Zhang, FIG. 17A, 1701) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 19 (Previously Presented), Zhang teaches the method as claimed in claim 17 wherein
the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ),
the second metal layer ( Zhang, FIG. 10A, 1001 ) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ), and
the third metal layer ( Zhang, FIG. 17A, 1701) comprises ruthenium (Ru) ( Zhang, [0072], ruthenium (Ru) ).
Regarding Claim 20 (Original), Zhang teaches the method as claimed in claim 17 wherein
the second hardmask ( Zhang, FIG. 17A, 20A, 1503, 1702 ) comprises a lower hardmask ( Zhang, FIG. 17A, 20A, 1501 ) deposited on the first metal layer ( Zhang, FIG. 1B, 103; [0061], conductive lines 103 ) , and an upper hardmask ( Zhang, FIG. 17A, 20A, 1503 ) deposited on the lower hardmask ( Zhang, FIG. 17A, 20A, 1501 ),
the lower hardmask ( Zhang, FIG. 17A, 20A, 1501 ) comprises silicon nitride (Si3N4) ( Zhang, [0065], silicon nitride ), and
the upper hardmask ( Zhang, FIG. 17A, 20A, 1503 ) comprises tetra-ethyl-orthosilicate (TEOS) ( Zhang, [0065], phosphosilicate glass, Fluorosilicate (SiOF) glass, organosilicate glass (SiOCH) ).
Response to Arguments
Applicant's arguments filed 2/9/2026 have been fully considered but they are not persuasive.
Applicant's remarks regarding Claims 1, 15 ( currently amended ): page 9, line 1, cited “ Thus, Zhang teaches planarizing the second dielectric layer and the lower hardmask (mask 720) prior to, rather than subsequent to, filling the openings and the first vias (gap 801). Therefore, Zhang fails to anticipate claims 1 and 15 and claims dependent thereon for at least the above reasons. ”.
Examiners’ response: Please refer to claims 1, 15 in Claim Rejections - 35 USC § 103 of this office action, cited “ Zhang does not explicitly disclose:
subsequent to filling the openings and the first vias, planarizing the second dielectric layer and the lower hardmask, removing the upper hardmask;
However, Zhang teaches:
the processes of FIG. 3 – FIG. 5A/5B;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the processes of FIG. 3 – FIG. 5A/5B in Zhang, to create that subsequent to filling the openings and the first vias ( i.e. filling 401 in FIG. 4 ), planarizing the second dielectric layer and the lower hardmask ( i.e. chemical-mechanical polishing (CMP) planarizing the top surface of 102 and 301 and 401 in FIG. 5A/5B ), removing the upper hardmask ( i.e. removing the 301 on 102 in FIG. 5A/5B ); such that an alternative process for implementing self-aligned vias could be implemented, since this is within the skill level of one in the art. ”.
Applicant's remarks regarding Claim 10 ( currently amended ): page 10, line 1, cited “ Thus, Zhang teaches a plurality of third interconnect structures being connected with each other, rather than being isolated from each other as recited in the claim. Therefore, Zhang fails to anticipate claim 10 and claims dependent thereon for at least the above reasons. ”.
Examiners’ response: First, the new limitations added into amended claims 10 still read on Zhang, as shown claims 10 in Claim Rejections - 35 USC § 103 of this office action, cited “ wherein each of the plurality of third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) is self-aligned with one of the plurality of second interconnect structures ( Zhang, FIG. 20A, via 1801 between 102 ), and isolated from a neighboring third interconnect structure of the plurality of the third interconnect structures ( Zhang, FIG. 20A, via 1801 between 1001 ) by the fourth dielectric layer ( Zhang, FIG. 20A, 1001 ). ”. Second, even if the “ isolated ” is amended to “ electrically isolated ”, it still would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the interconnection structure of FIG. 20A/20B in Zhang, using the dielectric-separation arrangement taught by FIG. 11A/11B in Zhang, so that each of the plurality of third interconnect structures is electrically isolated from a neighboring third interconnect structure of the plurality of the third interconnect structures by the fourth dielectric layer, because Zhang teaches adjacent interconnect structures 601 separated by dielectric layer 1001, as shown in FIG. 11A/11B.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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