DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on July 31, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9, 11 and 13-14, 21, 23, and 35 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2015/0200149 A1 to Zhao et al. (“Zhao”). As to claim 8, Zhao discloses a semiconductor device, comprising: a first integrated circuit die (102); a plurality of heat dissipation patterns (208) on an outermost surface of the first integrated circuit die (102), wherein at least one of the heat dissipation patterns (208) having a curved sidewall is in direct contact with the outermost surface of the first integrated circuit die (102); and an encapsulant (112), encapsulating the first integrated circuit die (102), wherein the encapsulant (112) is disposed between the heat dissipation patterns (208), and the curved sidewall is continuously extended from the outermost surface of the first integrated circuit die (102) to a surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). As to claim 9, Zhao further discloses wherein the heat dissipation patterns (208) each include a conductive paste, a conductive pattern (208) or combinations thereof (See ¶ 0062). As to claim 11, Zhao further discloses wherein the heat dissipation patterns (208) are arranged in an array (See Fig. 2). As to claim 13, Zhao further discloses wherein the surface of the encapsulant (112) is substantially coplanar with surfaces (252) of the heat dissipation patterns (208) (See Fig. 2, ¶ 0060). As to claim 14, Zhao further discloses wherein in a top view, a shape of the heat dissipation patterns (208) includes circle, rectangular, fusiform or combinations thereof, or the heat dissipation patterns are connected to form a net (See Fig. 2). As to claim 21, Zhao discloses a semiconductor device, comprising: a first die (102), comprising a first interconnect structure (114); a plurality of heat dissipation patterns (208) disposed at an outermost surface of the first die (102) and electrically isolated from the first interconnect structure (114), wherein at least one of the heat dissipation patterns (208) having a hemispherical shaped surface is in direct contact with the outermost surface of the first die (102); and an encapsulant (112), encapsulating the first die (102), wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die (102) to a first surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). As to claim 23, Zhao further discloses wherein the encapsulant (112) is disposed between the heat dissipation patterns (208) (See Fig. 2). As to claim 35, Zhao further discloses wherein the hemispherical shaped surface interfaces with the encapsulant (112) (See Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2015/0200149 A1 to Zhao et al. (“Zhao”) as applied to claims 8 and 21 above, and further in view of U.S. Patent Application Publication No. 2017/0162531 A1 to Ko et al. (“Ko”). The teaching of Zhao has been discussed above. As to claim 10, although Zhao discloses wherein the heat dissipation patterns (208) each include solder (See ¶ 0062), Zhao does not further disclose wherein the heat dissipation patterns each include silver powder. However, Ko does disclose wherein the heat dissipation patterns (3) each include silver powder (See Fig. 1, ¶ 0081, ¶ 0114). In view of the teaching of Ko, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Zhao to have wherein the heat dissipation patterns each include silver powder because silver powder along with solder are known thermal conductive materials to provide satisfactory heat dissipation (See Zhao and Ko). As to claim 27, although Zhao discloses wherein a material of the heat dissipation patterns (208) comprises a solder (See ¶ 0062), Zhao does not further disclose wherein the material of the heat dissipation patterns comprises a silver paste, a copper paste, a graphite paste or combinations thereof. However, Ko does disclose wherein the material of the heat dissipation patterns (3) comprises solder, a silver paste, a copper paste, a graphite paste or combinations thereof (See Fig. 1, ¶ 0081, ¶ 0114). In view of the teaching of Ko, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Zhao to have wherein a material of the heat dissipation patterns comprises a silver paste, a copper paste, a graphite paste or combinations thereof because silver paste, a copper paste, a graphite paste or combinations thereof along with solder are known thermal conductive materials to provide satisfactory heat dissipation (See Zhao and Ko).
Claim(s) 8, 12, 21, 23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0125955 A1 to Suh et al. (“Suh”) in view of U.S. Patent Application Publication No. 2015/0200149 A1 to Zhao et al. (“Zhao”). As to claim 8, although Suh discloses a semiconductor device, comprising: a first integrated circuit die (700); and an encapsulant (600), encapsulating the first integrated circuit die (700) (See Fig. 6, ¶ 0078, ¶ 0079, ¶ 0081) Suh does not further disclose a plurality of heat dissipation patterns on an outermost surface of the first integrated circuit die, wherein at least one of the heat dissipation patterns having a curved sidewall is in direct contact with the outermost surface of the first integrated circuit die; and wherein the encapsulant is disposed between the heat dissipation patterns, and the curved sidewall is continuously extended from the outermost surface of the first integrated circuit die to a surface of the encapsulant. However, Zhao does disclose a plurality of heat dissipation patterns (208) on an outermost surface of the first integrated circuit die (102), wherein at least one of the heat dissipation patterns (208) having a curved sidewall is in direct contact with the outermost surface of the first integrated circuit die (102); and wherein the encapsulant (112) is disposed between the heat dissipation patterns (208), and the curved sidewall is continuously extended from the outermost surface of the first integrated circuit die (102) to a surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). In view of the teaching of Zhao, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Suh to have a plurality of heat dissipation patterns on an outermost surface of the first integrated circuit die, wherein at least one of the heat dissipation patterns having a curved sidewall is in direct contact with the outermost surface of the first integrated circuit die; and wherein the encapsulant is disposed between the heat dissipation patterns, and the curved sidewall is continuously extended from the outermost surface of the first integrated circuit die to a surface of the encapsulant because the heat dissipation patterns improve thermal performance by the displacement of the encapsulant (See ¶ 0061). As to claim 12, Suh in view of Zhao further discloses wherein the encapsulant (600/112) further encapsulates a second integrated circuit die (500), and surfaces (252) of the heat dissipation patterns (208) are substantially coplanar with the second integrated circuit die (500) (See Suh Fig. 6 and Zhao ¶ 0060). As to claim 21, although Suh discloses a semiconductor device, comprising: a first die (700), comprising a first interconnect structure (720); and an encapsulant (600), encapsulating the first die (700) (See Fig. 6, ¶ 0078, ¶ 0079, ¶ 0080, ¶ 0081), Suh does not further disclose a plurality of heat dissipation patterns disposed at an outermost surface of the first die and electrically isolated from the first interconnect structure, wherein at least one of the heat dissipation patterns having a hemispherical shaped surface is in direct contact with the outermost surface of the first die; wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die to a first surface of the encapsulant. However, Zhao does disclose a plurality of heat dissipation patterns (208) disposed at an outermost surface of the first die (102) and electrically isolated from the first interconnect structure (114), wherein at least one of the heat dissipation patterns (208) having a hemispherical shaped surface is in direct contact with the outermost surface of the first die (102); wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die (102) to a first surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). In view of the teaching of Zhao, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Suh to have a plurality of heat dissipation patterns disposed at an outermost surface of the first die and electrically isolated from the first interconnect structure, wherein at least one of the heat dissipation patterns having a hemispherical shaped surface is in direct contact with the outermost surface of the first die; wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die to a first surface of the encapsulant because the heat dissipation patterns improve thermal performance by the displacement of the encapsulant (See ¶ 0061). As to claim 23, Suh in view of Zhao further discloses wherein the encapsulant (600/112) is disposed between the heat dissipation patterns (208) (See Suh Fig. 6 and Zhao Fig. 2). As to claim 25, Suh in view of Zhao discloses further comprising a second die (500) encapsulated by the encapsulant (600/112), wherein the first surface of the encapsulant (600/112) is substantially coplanar with a first surface of the second die (500) (See Suh Fig. 6).
Claim(s) 21-23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0293580 A1 to Park et al. (“Park”) in view of U.S. Patent Application Publication No. 2015/0200149 A1 to Zhao et al. (“Zhao”). As to claim 21, although Park discloses a semiconductor device, comprising: a first die (200), comprising a first interconnect structure (above 210); and an encapsulant (900), encapsulating the first die (200) (See Fig. 1, Fig. 4, ¶ 0022, ¶ 0023, ¶ 0024, ¶ 0026, ¶ 0028, ¶ 0094, ¶ 0100, ¶ 0101, ¶ 0102) (Notes: the first interconnect structure comprises elements providing interconnections), Park does not further disclose a plurality of heat dissipation patterns disposed at an outermost surface of the first die and electrically isolated from the first interconnect structure, wherein at least one of the heat dissipation patterns having a hemispherical shaped surface is in direct contact with the outermost surface of the first die; wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die to a first surface of the encapsulant. However, Zhao does disclose a plurality of heat dissipation patterns (208) disposed at an outermost surface of the first die (102) and electrically isolated from the first interconnect structure (114), wherein at least one of the heat dissipation patterns (208) having a hemispherical shaped surface is in direct contact with the outermost surface of the first die (102); wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die (102) to a first surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). In view of the teaching of Zhao, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Park to have a plurality of heat dissipation patterns disposed at an outermost surface of the first die and electrically isolated from the first interconnect structure, wherein at least one of the heat dissipation patterns having a hemispherical shaped surface is in direct contact with the outermost surface of the first die; wherein a portion of the hemispherical shaped surface is continuously extended from the outermost surface of the first die to a first surface of the encapsulant because the heat dissipation patterns improve thermal performance by the displacement of the encapsulant (See ¶ 0061). As to claim 22, Park in view of Zhao further discloses wherein the first die (200/102) further comprises a semiconductor substrate (210), and the first interconnect structure (above 210) is disposed between the semiconductor substrate (210) and the heat dissipation patterns (208) (See Park Fig. 1, Fig. 4, ¶ 0026 and Zhao Fig. 2). As to claim 23, Park in view of Zhao further discloses wherein the encapsulant (900/112) is disposed between the heat dissipation patterns (208) (See Park Fig. 1, Fig. 4 and Zhao Fig. 2). As to claim 26, Park in view of Zhao further discloses wherein the heat dissipation patterns (208) are in direct contact with the first interconnect structure (above 210) and disposed within a periphery of the first die (200/102) (See Park Fig. 1, Fig. 4 and Zhao Fig. 2).
Claim(s) 28 and 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0254260 A1 to Wei et al. (“Wei”) in view of U.S. Patent Application Publication No. 2015/0200149 A1 to Zhao et al. (“Zhao”). As to claim 28, although Wei discloses a semiconductor device, comprising: a first die (202 of 20), comprising a first semiconductor substrate (200) and having a first surface and a second surface; an interconnect substrate (180), wherein the first die (202 of 20) is electrically connected to the interconnect substrate (180) through the second surface; and a first encapsulant (110) encapsulating the first die (202 of 20) (See Fig. 1, ¶ 0022-¶ 0033, ¶ 0036-¶ 0044), Wei does not further disclose a plurality of heat dissipation patterns on the first surface, wherein at least one of the heat dissipation patterns having a curved sidewall is in direct contact with the first surface; wherein the curved sidewall is continuously extended from the first surface to a surface of the encapsulant. However, Zhao does disclose a plurality of heat dissipation patterns (208) on the first surface, wherein at least one of the heat dissipation patterns (208) having a curved sidewall is in direct contact with the first surface; wherein the curved sidewall is continuously extended from the first surface to a surface of the encapsulant (112) (See Fig. 2, ¶ 0058-¶ 0062). In view of the teaching of Zhao, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Wei to have a plurality of heat dissipation patterns on the first surface, wherein at least one of the heat dissipation patterns having a curved sidewall is in direct contact with the first surface; wherein the curved sidewall is continuously extended from the first surface to a surface of the encapsulant because the heat dissipation patterns improve thermal performance by the displacement of the encapsulant (See ¶ 0061). As to claim 30, Wei in view of Zhao further discloses wherein the first encapsulant (110/112) is further disposed between the heat dissipation patterns (208) (See Wei Fig. 1 and Zhao Fig. 2). As to claim 31, Wei discloses further comprising a second die (10, 202 of 30) and an underfill (108), wherein the second die (10, 202 of 30) is encapsulated by the first encapsulant (110) and electrically connected to the interconnect substrate (180), the underfill (108) is continuously disposed between the interconnect substrate (180) and the first die (202 of 20), between the interconnect substrate (180) and the second die (10, 202 of 30) and between the first die (202 of 20) and the second die (10, 202 of 30), and the first encapsulant (110) is overlapped with the underfill (108) between the first die (202 of 20) and the second die (10, 202 of 30) (See Fig. 1). As to claim 32, Wei discloses further comprising a second encapsulant (210) different from the first encapsulant (110), wherein the second encapsulant (210) is disposed between the second die (10, 202 of 30) and the first encapsulant (110) and between the second die (10, 202 of 30) and the underfill (108) (See Fig. 1). As to claim 33, Wei further discloses wherein the interconnect substrate (180) comprises a second semiconductor substrate (180), a plurality of through vias (182) penetrating through the second semiconductor substrate (180), an interconnect layer (106) at a first side of the second semiconductor substrate (180) and facing the first die (202 of 20) and a plurality of electrical connectors (114) electrically connected to the through vias (182) and at a second side opposite to the first side of the second semiconductor substrate (180) (See Fig. 1). As to claim 34, Wei further discloses wherein the first encapsulant (110) is continuously disposed between a sidewall of the first die (202H of 20) and a sidewall of the second die (10, 202H of 30), the underfill (108) is continuously disposed between the sidewall of the first die (202H of 20) and the sidewall of the second die (10, 202H of 30), and the first encapsulant (110) between the sidewall of the first die (202H of 20) and the sidewall of the second die (10, 202H of 30) is physically connected to the underfill (108) between the sidewall of the first die (202H of 20) and the sidewall of the second die (10, 202H of 30) (See Fig. 1).
Response to Arguments
Applicant's arguments with respect to claims 8, 21, and 28 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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