DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 22 September 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “wherein the filament formation bias is applied greater than a breakdown voltage of the first filament via and not for a memory device utilizing a switching mechanism.” It is unclear and indefinite as to how the filament formation bias is not for a memory device utilizing a switching mechanism. For example, does the recitation exclude the application of the filament formation bias to a periphery circuit of a memory device utilizing a switching mechanism? Further, it is unclear and indefinite as to what range of voltage would be not for a memory device utilizing a switching mechanism.
For compact prosecution, it will be interpreted as the filament formation bias can be applied to anywhere in a memory device that does not have a switching mechanism.
Claim 15 recites a similar recitation and is therefore rejected under 35 U.S.C. 112(b) for the same reason and is similarly interpreted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamauchi et al. (U.S. Pub. 2012/0205608).
Claim 11: Yamauchi et al. discloses a method of forming an integrated chip including an interconnect structure, in in Figs. 1-2D, 11A and 11B (orientation is inverted) and in paragraphs 28-32, 41-43 and 123, the method comprising:
forming a first metal layer (1), a first filament dielectric layer (2 and 3) stacked on the first metal layer (1) and a second metal layer (4 and/or 31) stacked on the first filament dielectric layer (2 and 3); and
applying a first bias (D1) between the second metal layer (4) and the first metal layer (1) to form a first filament via (F) through the first filament dielectric layer (2 and 3), wherein the first filament via (F) is formed with a selected width (width of F) by applying the first bias (D1), the selected width (width of F) determining a resistance (resistance of F) of the first filament via (F) such that the resistance (resistance of F) is adjusted to achieve resistance-capacitance optimization in the interconnect structure (resistance is optimized for readout and therefore resistance-capacitance is also optimized).
Claim 12: Yamauchi et al. discloses the method of claim 11, and in Figs. 1-2D and in paragraph 45, further discloses wherein the first filament via (F) is dissolved to disconnect a stable interconnecting electrical path when applying a reset bias (D2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. as applied to claim 11 above, and further in view of Haimoto et al. (U.S. Pub. 2012/0211719).
Claims 13 and 14: Yamauchi et al. discloses the method of claim 11.
Yamauchi et al. appears not to explicitly disclose further comprising:
forming a second filament dielectric layer, and a third metal layer over the second metal layer; and
applying a second bias between the third metal layer and the second metal layer and forming a second filament via through the second filament dielectric layer interconnecting the third metal layer and the second metal layer,
wherein the second bias is greater than the first bias to form the second filament via with a width greater than the first filament via, and
wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer.
Haimoto et al., however, in Figs. 3A-3D and in paragraphs 49, 52, 57, 68-70 and 82, discloses forming a second filament dielectric layer (12), and a third metal layer (11) over the second layer (13); and
applying a second bias (V1) between the third metal layer (11) and the second layer (13) and forming a second filament via (16) through the second filament dielectric layer (12) interconnecting the third metal layer (11) and the second layer (13),
wherein the second bias (V1) is greater than the first bias (V2) to form the second filament via (16) with a width (with of 16 near 11) greater than the first filament via (width of 17 near 13), and
wherein the first filament via (17) and the second filament via (16) form a continuous interconnecting electrical path across the first metal layer (15), the second layer (13), and the third metal layer (11) in order to increase tolerance of the resistance value of the device.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. with the disclosure of Haimoto et al. to have formed a second filament dielectric layer, and a third metal layer over the second metal layer; and
applied a second bias between the third metal layer and the second metal layer and forming a second filament via through the second filament dielectric layer interconnecting the third metal layer and the second metal layer;
wherein the second bias is greater than the first bias to form the second filament via with a width greater than the first filament via, and
wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. as applied to claim 11 above, and further in view of Ertosun (U.S. Patent 9,053,789).
Claim 15: Yamauchi et al. discloses the method of claim 11.
Yamauchi et al. appears not to explicitly disclose wherein the first bias is applied greater than a breakdown voltage of the first filament via and not for a memory device utilizing a switching mechanism.
Ertosun, however, in column 10, line 49 – column 11, line 33, discloses the first bias (program voltage) is applied greater than a breakdown voltage (high voltage) of the first filament via (conductive filament) and not for a memory device utilizing a switching mechanism (since the conductive filament is not erasable, it is a switching mechanism) in order to have a hard programmed cell that would require less power to maintain data.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. with the disclosure of Wang et al. to have made the first bias is applied greater than a breakdown voltage of the first filament via and not for a memory device utilizing a switching mechanism in order to have a hard programmed cell that would require less power to maintain data (Ertosun in column 10, line 49 – column 11, line 33).
Claim(s) 1, 3, 4 and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. (U.S. Pub. 2012/0205608) in view of Wang et al. (U.S. Pub. 2014/0353566).
Claim 1: Yamauchi et al. discloses a method to form an interconnect structure of an integrated chip, in Figs. 1-2D, 11A and 11B (orientation is inverted) and in paragraphs 28-32, 41-43, 80 and 123, the method comprising:
forming a first metal layer (1) of the interconnect structure comprising a first plurality of metal lines (1 in cell shown in Fig. 1, and 1 in adjacent cell in Fig. 11A);
forming a first filament dielectric layer (3) over the first metal layer (1);
forming a second metal layer (upper portion of 4 in Fig. 1 or lower portion of 4 in Fig. 11B) of the interconnect structure over the firs filament dielectric layer and comprising a plurality of metal lines (upper portion of 4 in Fig. 1, and lower portion of 4 in adjacent cell in Fig. 11B); and
applying a filament formation bias (D1) to form a first filament via (F) through the first filament dielectric layer (3) and forming a stable interconnecting electrical path between first pair of metal lines (between 1 and upper portion of 4 in Fig. 1) of the first metal layer (1) and the second metal layer (upper portion of 4 in Fig. 1 or lower portion of 4 in Fig. 11B).
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Yamauchi et al. appears not to explicitly disclose the first filament dielectric layer is a low-k dielectric material.
Wang et al, however, in Fig. 3A and in paragraphs 41 and 42, discloses the first filament dielectric layer (322) is a low-k dielectric material in order to use less power to set and reset.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. with the disclosure of Wang et al. to have made the first filament dielectric layer is a low-k dielectric material in order to use less power to set and reset (paragraph 41).
Claim 3: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D, further discloses comprising:
applying the filament formation bias (D1) to form a second filament via (F in adjacent cell) through the first filament dielectric layer (3) and forming another stable interconnecting electrical path connecting a second pair of metal lines (between 1 in adjacent cell and upper portion of 1 in adjacent cell in Fig. 11A) of the first metal layer (1) and the second metal layer (upper portion of 4 in Fig. 1 or lower portion of 4 in Fig. 11B),
wherein the first filament via (F) and the second filament via (F in adjacent cell) are configured to be formed separately (the cells of Yamauchi et al. are configured to separately form the conductive filaments).
Claim 4: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D and in paragraph 45, further discloses comprising applying a filament removal bias (D2) to remove the first filament via (F) and disconnect the first pair metal lines (between 1 and upper portion of 4 in Fig. 1).
Claim 7: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D and in paragraph 31, further discloses comprising forming a filament metal layer (lower portion of 4) between and directly contacting the first filament dielectric layer (3) and the second metal layer (upper portion of 4), wherein the filament metal layer (lower portion of 4) is made of metal chalcogenide.
Claim 8: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D, further discloses comprising forming a filament metal layer (lower portion of 4) between the directly contacting the first filament dielectric layer (3) and the second metal layer (upper portion of 4), wherein the filament metal layer (lower portion of 4) has sidewalls vertically aligned with sidewalls of the second metal layer (upper portion of 4).
Claim 9: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D and in paragraphs 41-43, further discloses comprising forming a filament metal layer (lower portion of 4) between the directly contacting the filament dielectric layer (3) and the second metal layer (upper portion of 4), wherein the filament metal layer (lower portion of 4) is made of a plurality of discrete islands comprising a first island (lower portion of 4 in Fig. 1) configured as a material source of the first filament via (F) and a second island (lower portion of 4 in adjacent cell) configured as a material source of a second filament via (F in adjacent cell).
Claim 10: Yamauchi et al. in view of Wang et al. discloses the method of claim 1, and Yamauchi et al., in Figs. 1-2D, further discloses wherein the first filament via (F) is formed contacting the first metal layer (1).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. in view of Wang et al. as applied to claim 1 above, and further in view of Ertosun (U.S. Patent 9,503,789).
Claim 2: Yamauchi et al. in view of Wang et al. discloses the method of claim 1.
Yamauchi et al. in view of Wang et al. appears not to explicitly disclose wherein the filament formation bias is applied greater than a breakdown voltage of the first filament via and not for a memory device utilizing a switching mechanism.
Ertosun, however, in column 10, line 49 – column 11, line 33, discloses the filament formation bias (program voltage) is applied greater than a breakdown voltage (high voltage) of the first filament via (conductive filament) and not for a memory device utilizing a switching mechanism (since the conductive filament is not erasable, it is a switching mechanism) in order to have a hard programmed cell that would require less power to maintain data.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. in view of Wang et al. with the disclosure of Wang et al. to have made the filament formation bias is applied greater than a breakdown voltage of the first filament via and not for a memory device utilizing a switching mechanism in order to have a hard programmed cell that would require less power to maintain data (Ertosun in column 10, line 49 – column 11, line 33).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. in view of Wang et al. as applied to claim 1 above, and further in view of Haimoto et al. (U.S. Pub. 2012/0211719).
Claim 5: Yamauchi et al. in view of Wang et al. discloses the method of claim 1.
Yamauchi et al. in view of Wang et al. appears not to explicitly disclose further comprising:
forming a second filament dielectric layer over the second metal layer;
forming a third metal layer of the interconnect structure over the second filament dielectric layer; and
forming a second filament via through the second filament dielectric layer, wherein the first filament via and the second filament via form continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer.
Haimoto et al., however, in Figs. 3A-3C and in paragraphs 49, 52, 57, 68-70 and 82, discloses forming a second filament dielectric layer (12) over the second layer (13);
forming a third metal layer (11) of the interconnect structure over the second filament dielectric layer (12); and
forming a second filament via (16) through the second filament dielectric layer (12), wherein the first filament via (17) and the second filament via (16) form continuous interconnecting electrical path across the first metal layer (15), the second layer, and the third metal layer (11) in order to increase tolerance of the resistance value of the device.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. in view of Wang et al. with the disclosure of Haimoto et al. to have formed a second filament dielectric layer over the second metal layer;
formed a third metal layer of the interconnect structure over the second filament dielectric layer; and
formed a second filament via through the second filament dielectric layer, wherein the first filament via and the second filament via form continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. in view of Wang et al. in view of Haimoto et al. as applied to claim 5 above, and further in view of Kusai et al. (U.S. Pub. 2012/0091420).
Claim 6: Yamauchi et al. in view of Haimoto et al. discloses the method of claim 5.
Yamauchi et al. in view of Wang et al. in view of Haimoto et al. appears to not explicitly disclose wherein the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer.
Kusai et al., however, in Fig. 3C and in paragraphs 42, 66 and 70, discloses the first filament via (18) is formed with a wider lateral dimension at a side closer to the second metal layer (13), and where the second filament via (17) is formed with a wider lateral dimension at a side closer to the third metal layer (16).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Kusai et al. that is in the same field of endeavor with Yamauchi et al. in view of Wang et al. in view of Haimoto et al., before the effective filing date of the claimed invention in order to substitute the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer as disclosed by Kusai et al. for the widths of the first and second filament vias disclosed by Yamauchi et al. in view of Wang et al. in view of Haimoto et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer disclosed by Kusai et al. for the widths of the first and second filament vias disclosed by Yamauchi et al. in view of Wang et al. in view of Haimoto et al. would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim(s) 21-23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. (U.S. Pub. 2012/0205608) in view of Chen et al. (U.S. Pub. 2016/0372196).
Claim 21: A method to form an interconnect structure of an integrated chip, in Figs. 1-2D, 11A and 11B (orientation is inverted) and in paragraphs 28-32, 41-43, 80 and 123, the method comprising:
forming a stack of metal layers (1 and 4) of the interconnect structure, comprising a plurality of metal lines (1 in cell shown in Fig. 1, 1 in adjacent cell in Fig. 11A, 4 in Fig. 1; and 4 in adjacent cell in Fig. 11A) separated by interlayer dielectric layers (2 and 3); and
by applying a filament formation bias (D1), forming stacked metallic filament vias (F and F in adjacent cell, which are stacked between the metal layers) through the interlayer dielectric layers (2 and 3) and interconnecting the plurality of metal lines (1 in cell shown in Fig. 1, 1 in adjacent cell in Fig. 11A, 4 in Fig. 1; and 4 in adjacent cell in Fig. 11A),
wherein the stacked metallic filament vias (F and F in adjacent cell in Fig. 11A) form a continuous interconnecting electrical path across stack of metal layers (1 and 4).
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Yamauchi et al. appears not to explicitly disclose by applying different filament formation biases, forming stacked metallic filament vias of different widths, the different widths determining a resistance and a capacitance of the interconnect structure.
Chen et al., however, in paragraphs 25-31 and 33, discloses by applying different filament formation biases (PSET1 and PSET2), forming stacked metallic filament vias (filament paths) of different widths (large width and narrow width), the different widths determining a resistance and a capacitance of the interconnect structure in order to write data of different logic levels to prevent an error in determining the logic level of the stored data.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. with the disclosure of Chen et al. to have made applied different filament formation biases, forming stacked metallic filament vias of different widths, the different widths determining a resistance and a capacitance of the interconnect structure in order to write data of different logic levels to prevent an error in determining the logic level of the stored data (paragraph 33 of Chen et al.).
Claim 22: Yamauchi et al. in view of Chen et al. discloses the method of claim 21, and Yamauchi et al., in Fig. 11A and in paragraph 123, further discloses comprising forming a first contact (34) on top of the integrated chip for applying the filament formation biases (D1 and D2) and forming the stacked metallic filament via (F and F in adjacent cell in Fig. 11A).
Claim 23: Yamauchi et al. in view of Chen et al. discloses the method of claim 22, and Yamauchi et al., in Figs. 1-2D and in paragraph 45, further discloses comprising applying a filament removal bias (D2) to at least partially remove at least one of stacked metallic filament vias (F and F in adjacent cell in Fig. 11A) and disconnect the continuous interconnecting electrical path.
Claim 25: Yamauchi et al. in view of Chen et al. discloses the method of claim 21, and Yamauchi et al., in Figs. 1-2D, further discloses wherein the stacked metallic filament vias (F and F in adjacent cell in Fig. 11A) are formed respectively contact the stack of metal layers (1 and 4).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamauchi et al. in view of Chen et al. as applied to claim 21 above, and further in view of Otsuka et al. (U.S. Pub. 2014/0268992).
Claim 24: Yamauchi et al. in view of Chen et al. discloses the method of claim 21.
Yamauchi et al. in view of Chen et al. appears not to explicitly disclose wherein the stacked metallic filament vias are formed permanently and not reversible.
Otsuka et al., however, in Fig. 4B and in paragraphs 3 and 65, discloses the stacked metallic filament vias (52 and 52 in adjacent cell) are formed permanently and not reversible
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. in view of Chen et al. with the disclosure of Otsuka et al. to have made the stacked metallic filament vias are formed permanently and not reversible in order to permanently store data (paragraph 3 of Otsuka et al.).
Response to Arguments
Applicant's arguments filed 22 September 2025 have been fully considered but they are not persuasive.
Applicant contends claim 11 is distinguished over Yamauchi et al.
Examiner notes that Yamauchi et al. discloses claim 11 (see rejection of claim 11 above).
Applicant’s arguments with respect to claim(s) 1-10 and 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.L/ Examiner, Art Unit 2815