DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 29 April 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 24 September 2026 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites “wherein the first filament via is formed by dielectric breakdown of the low-k interlayer.” Applicant’s originally filed specification does not disclose the first filament via being formed by dielectric breakdown, therefore it is considered new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “[a] method to form an interconnect structure of an integrated chip, in Fig. 3, the method comprising:
forming a first metal layer (25) and a second metal layer (29) separated by an interlayer dielectric (27) of an interconnect structure.”
It is unclear and indefinite as to whether the claimed interconnect structures are the same or are different. For compact prosecution, it will be interpreted as the same.
Claims 2-10, which depend either directly or indirectly from independent claim 1, do not remedy the issues of claim 1 and therefore are also rejected.
Claim 11 recites “[a] method of forming an integrated chip including an interconnect structure,” and “forming a first metal layer, a low-k interlayer dielectric of a back-end-of-line interconnect structure.” It is unclear and indefinite as to whether the “interconnect structure” and the “back-end-of-line interconnect structure” are the same or are different. For compact prosecution, it will be interpreted as the same.
Claims 12-15, which depend either directly or indirectly from independent claim 1, do not remedy the issues of claim 1 and therefore are also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4 and 7-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (U.S. Pub. 2006/0054950) in view of Wang et al. (U.S. Pub. 2014/0353566).
Claim 1: Baek et al. discloses a method to form an interconnect structure of an integrated chip, in Fig. 3, the method comprising:
forming a first metal layer (25; paragraph 28) and a second metal layer (upper portion of 29; paragraph 28) separated by an interlayer dielectric (27; paragraphs 27 and 31) of the interconnect structure, the first metal layer (25) and the second metal layer (27) respectively comprising a first plurality of metal lines (left 25 and right 25) and a second plurality of metal lines (upper portion of left 29 and upper portion of right 29);
applying a filament formation bias (set voltage; paragraphs 39 and 40) to form a first filament via (left conductive filament that is formed between left 25 and upper portion of left 29; paragraphs 39 and 40) through the interlayer dielectric (27) as a filament-forming medium to form a stable interconnecting electrical path (path through left conductive filament) between first pair of metal lines (left 25 and upper portion of left 29) of the first metal layer (25) and the second metal layer (upper portion of 29).
Baek et al. appears not to explicitly disclose the interlayer dielectric is low-k.
Wang et al, however, in Figs. 3A and 4B and in paragraphs 41, 42 and 47, discloses the interlayer dielectric (322 and/ or 422) is low-k in order to use less power to set and reset.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Wang et al. to have made the interlayer dielectric is low-k in order to use less power to set and reset (paragraph 41).
Claim 3: Baek et al. in view of Wang et al. discloses the method of claim 1, and in Fig. 3, Baek et al. further discloses comprising:
applying the filament formation bias (set voltage; paragraphs 39 and 40) to form a second filament via (right conductive filament that is formed between right 25 and upper portion of right 29; paragraphs 39 and 40) through the interlayer dielectric (27) and forming another stable interconnecting electrical path (path through right conductive filament) connecting a second pair of metal lines (right 25 and upper portion of right 29) of the first metal layer (25) and the second metal layer (upper portion of 29),
wherein the first filament via (left conductive filament) and the second filament via (right conductive filament) are configured to be formed separately (left and right conductive filaments are not physically touching, therefore they are formed separate).
Since Wang et al. discloses the interlayer dielectric can be low-k, Baek et al. in view of Wang et al. would disclose applying the filament formation bias to form a second filament via through the low-k interlayer dielectric.
Claim 4: Baek et al. in view of Wang et al. discloses the method of claim 1, and Baek further discloses comprising
applying a filament removal bias (reset voltage; paragraph 39 and 40) to remove the first filament via (left conductive filament) and disconnect the first pair metal lines (left 25 and upper portion of left 29).
Claim 7: Baek et al. in view of Wang et al. discloses the method of claim 1, and Baek et al. further discloses comprising forming a filament metal layer (lower portion of 29) between and directly contacting the interlayer dielectric (27) and the second metal layer (upper portion of 29), wherein the filament metal layer is made of metal chalcogenide.
Since Wang et al. discloses the interlayer dielectric can be low-k, Baek et al. in view of Wang et al. would disclose forming a filament metal layer between and directly contacting the low-k interlayer dielectric and the second metal layer
Claim 8: Baek et al. in view of Wang et al. discloses the method of claim 1, and Baek, in Fig. 3, further discloses comprising forming a filament metal layer (lower portion of 29) between and directly contacting the interlayer dielectric (27) and the second metal layer (upper portion of 29), wherein the filament metal layer (lower portion of 29) has sidewalls vertically aligned with sidewalls of the second metal layer (upper portion of 29).
Since Wang et al. discloses the interlayer dielectric can be low-k, Baek et al. in view of Wang et al. would disclose applying a filament metal layer between and directly contacting the low-k interlayer dielectric and the second metal layer.
Claim 9: Baek et al. in view of Wang et al. discloses the method of claim 1, and Baek, in Fig. 3, further discloses comprising forming a filament metal layer (lower portion of 29) between and directly contacting the interlayer dielectric (27) and the second metal layer (upper portion of 29), wherein the filament metal layer (lower portion of 29) is made of a plurality of discrete islands (lower portion of left 29 and lower portion of right 29) comprising a first island (lower portion of left 29) configured as a material source of the first filament via (left conductive filament) and a second island (lower portion of right 29) configured as a material source of a second filament via (lower portion of right 29).
Since Wang et al. discloses the interlayer dielectric can be low-k, Baek et al. in view of Wang et al. would disclose forming a filament metal layer between and directly contacting the low-k interlayer dielectric and the second metal layer
Claim 10: Baek et al. in view of Wang et al. discloses the method of claim 1, and Baek, in paragraphs 39 and 40, further discloses wherein the first filament via (left conductive filament) is formed contacting the first metal layer (25).
Claim 11: Baek et al. discloses a method of forming an integrated chip including an interconnect structure, in in Fig. 3, the method comprising:
forming a first metal layer (25; paragraph 28), an interlayer dielectric (27; paragraphs 27 and 31) of a back-end-of-line interconnect structure stacked on the first metal layer (25) and a second metal layer (29; paragraph 28) stacked on the interlayer dielectric (27); and
applying a first bias (set voltage; paragraphs 39 and 40) between the second metal layer (29) and the first metal layer (25) to form a first filament via (conductive filament; paragraphs 39 and 40) through the interlayer dielectric (25) as a filament-forming medium (25), wherein the first filament via (conductive filament) is formed with a selected width (width of conductive filament) by applying the first bias (set voltage), the selected width (width of conductive filament) determining a resistance (resistance of conductive filament) of the first filament via (conductive filament) such that the resistance (resistance of conductive filament) is adjusted to achieve resistance-capacitance optimization in the interconnect structure (resistance is optimized for readout and therefore resistance-capacitance is also optimized).
Baek et al. appears not to explicitly disclose the interlayer dielectric is low-k.
Wang et al, however, in Figs. 3A and 4B and in paragraphs 41, 42 and 47, discloses the interlayer dielectric (322 and/ or 422) is low-k in order to use less power to set and reset.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Wang et al. to have made the interlayer dielectric is low-k in order to use less power to set and reset (paragraph 41).
Claim 12: Baek et al. in view of Wang et al. discloses the method of claim 11, and Baek et al. further discloses wherein the first filament via (conducive filament) is dissolved to disconnect a stable interconnecting electrical path when applying a reset bias (reset voltage; paragraph 39 and 40).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. in view of Wang et al. as applied to claim 1 above, and further in view of Ishizaki et al. (U.S. Pub. 2012/0306081).
Claim 2: Baek et al. in view of Wang et al. disclose the method of claim 1.
Baek et al. in view of Wang et al. appears not to explicitly disclose wherein the first filament via is formed by dielectric breakdown of the low-k interlayer dielectric.
Ishizaki et al., however, in paragraph 269, discloses the first filament via (filament) is formed by dielectric breakdown (local dielectric breakdown) of the interlayer dielectric (31).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Ishizaki et al. that is in the same field of endeavor with Baek et al. in view of Wang et al., before the effective filing date of the claimed invention in order to substitute the first filament via is formed by dielectric breakdown of the interlayer dielectric as disclosed by Ishizaki et al. for the forming of the first filament via disclosed by Baek et al. in view of Wang et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first filament via is formed by dielectric breakdown of the interlayer dielectric disclosed by Ishizaki et al. for forming of the first filament via disclosed by Baek et al. in view of Wang et al. would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Since Wang et al. discloses the interlayer dielectric can be low-k, Baek et al. in view of Wang et al. in view of Ishizaki et al. would disclose the first filament via is formed by dielectric breakdown of the low-k interlayer dielectric.
Claim(s) 5, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. in view of Wang et al. as applied to claims 1 and 11 above, and further in view of Haimoto et al. (U.S. Pub. 2012/0211719).
Claim 5: Baek et al. in view of Wang et al. discloses the method of claim 1.
Baek et al. in view of Wang et al. appears to not explicitly disclose further comprising:
forming a second low-k interlayer dielectric over the second metal layer;
forming a third metal layer of the interconnect structure over the second low-k interlayer dielectric; and
forming a second filament via through the second low-k interlayer dielectric, wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer.
Haimoto et al., however, in Figs. 3A-3C and in paragraphs 49, 52, 57, 68-70 and 82, discloses forming a second interlayer dielectric (12) over the second layer (13);
forming a third metal layer (11) of the interconnect structure over the second interlayer dielectric (12); and
forming a second filament via (16) through the second interlayer dielectric (12), wherein the first filament via (17) and the second filament via (16) form continuous interconnecting electrical path (path through 16 and 17) across the first metal layer (15), the second layer, and the third metal layer (11) in order to increase tolerance of the resistance value of the device.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. in view of Wang et al. with the disclosure of Haimoto et al. to have formed a second low-k interlayer dielectric over the second metal layer; formed a third metal layer of the interconnect structure over the second low-k interlayer dielectric; and formed a second filament via through the second low-k interlayer dielectric, wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Haimoto et al. also appears not to explicitly disclose the second interlayer dielectric is low-k.
Wang et al, however, in Fig. 3A and in paragraphs 41 and 42, further discloses the second interlayer dielectric (322) is low-k in order to use less power to set and reset.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Haimoto et al. with the further disclosure of Wang et al. to have made the second interlayer dielectric is low-k in order to use less power to set and reset (paragraph 41).
Baek et al. in view of Wang et al. in view of Haimoto et al. would therefore disclose forming a second low-k interlayer dielectric over the second metal layer;
forming a third metal layer of the interconnect structure over the second low-k interlayer dielectric; and
forming a second filament via through the second low-k interlayer dielectric, wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer.
Claims 13 and 14: Baek et al. in view of Wang et al. discloses the method of claim 11.
Baek et al. in view of Wang et al. appears not to explicitly disclose further comprising:
forming a second filament dielectric layer, and a third metal layer over the second metal layer; and
applying a second bias between the third metal layer and the second metal layer and forming a second filament via through the second filament dielectric layer interconnecting the third metal layer and the second metal layer,
wherein the second bias is greater than the first bias to form the second filament via with a width greater than the first filament via, and
wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer.
Haimoto et al., however, in Figs. 3A-3D and in paragraphs 49, 52, 57, 68-70 and 82, discloses forming a second filament dielectric layer (12), and a third metal layer (11) over the second layer (13); and
applying a second bias (V1) between the third metal layer (11) and the second layer (13) and forming a second filament via (16) through the second filament dielectric layer (12) interconnecting the third metal layer (11) and the second layer (13),
wherein the second bias (V1) is greater than the first bias (V2) to form the second filament via (16) with a width (with of 16 near 11) greater than the first filament via (width of 17 near 13), and
wherein the first filament via (17) and the second filament via (16) form a continuous interconnecting electrical path across the first metal layer (15), the second layer (13), and the third metal layer (11) in order to increase tolerance of the resistance value of the device.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Wang et al. with the disclosure of Haimoto et al. to have formed a second filament dielectric layer, and a third metal layer over the second metal layer; and
applied a second bias between the third metal layer and the second metal layer and forming a second filament via through the second filament dielectric layer interconnecting the third metal layer and the second metal layer;
wherein the second bias is greater than the first bias to form the second filament via with a width greater than the first filament via, and
wherein the first filament via and the second filament via form a continuous interconnecting electrical path across the first metal layer, the second metal layer, and the third metal layer in order to increase tolerance of the resistance value of the device (paragraph 57 of Haimoto et al.).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. in view of Wang et al. in view of Haimoto et al. as applied to claim 5 above, and further in view of Kusai et al. (U.S. Pub. 2012/0091420).
Claim 6: Baek et al. in view of Wang et al. in view of Haimoto et al. discloses the method of claim 5.
Baek et al. in view of Wang et al. in view of Haimoto et al. appears to not explicitly disclose wherein the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer.
Kusai et al., however, in Fig. 3C and in paragraphs 42, 66 and 70, discloses the first filament via (18) is formed with a wider lateral dimension at a side closer to the second metal layer (13), and where the second filament via (17) is formed with a wider lateral dimension at a side closer to the third metal layer (16).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Kusai et al. that is in the same field of endeavor with Baek et al. in view of Wang et al. in view of Haimoto et al., before the effective filing date of the claimed invention in order to substitute the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer as disclosed by Kusai et al. for the widths of the first and second filament vias disclosed by Baek et al. in view of Wang et al. in view of Haimoto et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first filament via is formed with a wider lateral dimension at a side closer to the second metal layer, and where the second filament via is formed with a wider lateral dimension at a side closer to the third metal layer disclosed by Kusai et al. for the widths of the first and second filament vias disclosed by Baek et al. in view of Wang et al. in view of Haimoto et al. would have yielded predictable results, namely providing a suitable electrical connection between the metal layers. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim(s) 21-23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (U.S. Pub. 2006/0054950) in view of Wang et al. (U.S. Pub. 2014/0353566) in view of Chen et al. (U.S. Pub. 2016/0372196).
Claim 21: Baek et al. discloses a method to form an interconnect structure of an integrated chip, in Fig. 3, the method comprising:
forming a stack of metal layers (25 and 29; paragraph 28) of the interconnect structure, comprising a plurality of metal lines (left 25, right 25, left 29 and right 29) separated by interlayer dielectric layers (27; paragraphs 27 and 31), the interlayer dielectric layers (27) separating adjacent metal routing lines (left 25, right 25, left 29 and right 29) of the interconnect structure so as to electrically isolate the adjacent metal routing lines (left 25, right 25, left 29 and right 29); and
by applying a filament formation bias (set voltage; paragraphs 39 and 40), forming stacked metallic filament vias (left conductive filament and right conductive filament, which are stacked between the metal layers; paragraphs 39 and 40) through the interlayer dielectric layers (27) as a filament-forming medium (27) and interconnecting the plurality of metal lines (left 25, right 25, left 29 and right 29),
wherein the stacked metallic filament vias (left conductive filament and right conductive filament) form a continuous interconnecting electrical path (path through the conductive filaments) across the stack of metal layers (25 and 29).
Baek et al. appears not to explicitly disclose the interlayer dielectric layers being formed of a low-k dielectric material.
Wang et al, however, in Figs. 3A and 4B and in paragraphs 41, 42 and 47, discloses the interlayer dielectric (322 and/ or 422) is formed of a low-k dielectric material order to use less power to set and reset.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. with the disclosure of Wang et al. to have made the interlayer dielectric formed of a low-k dielectric material in order to use less power to set and reset (paragraph 41).
Baek et al. also appears not to explicitly disclose by applying different filament formation biases, forming stacked metallic filament vias of different widths, the different widths determining a resistance and a capacitance of the interconnect structure.
Chen et al., however, in paragraphs 25-31 and 33, discloses by applying different filament formation biases (PSET1 and PSET2), forming stacked metallic filament vias (filament paths) of different widths (large width and narrow width), the different widths determining a resistance and a capacitance of the interconnect structure in order to write data of different logic levels to prevent an error in determining the logic level of the stored data.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Yamauchi et al. with the disclosure of Baek et al. to have made applied different filament formation biases, forming stacked metallic filament vias of different widths, the different widths determining a resistance and a capacitance of the interconnect structure in order to write data of different logic levels to prevent an error in determining the logic level of the stored data (paragraph 33 of Chen et al.).
Claim 22: Baek et al. in view of Wang et al. in view of Chen et al. discloses the method of claim 21, and Baek et al., in Fig.4, further discloses comprising forming a first contact (37; paragraph 37) on top of the integrated chip for applying the filament formation biases (set voltage; paragraph 39) and forming the stacked metallic filament via (left conductive filament and right conductive filament).
Claim 23: Baek et al. in view of Wang et al. in view of Chen et al. discloses the method of claim 22, and Baek et al., further discloses comprising applying a filament removal bias (reset voltage; paragraphs 39 and 40) to at least partially remove at least one of stacked metallic filament vias (left conductive filament and right conductive filament) and disconnect the continuous interconnecting electrical path (path through the conductive filaments).
Claim 25: Baek et al. in view of Wang et al. in view of Chen et al. discloses the method of claim 21, and Baek et al., in paragraphs 39 and 40, further discloses wherein the stacked metallic filament vias (left conductive filament and right conductive filament) are formed respectively contact the stack of metal layers (25 and 29).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. in view of Wang et al. in view of Chen et al. as applied to claim 21 above, and further in view of Otsuka et al. (U.S. Pub. 2014/0268992).
Claim 24: Baek et al. in view of Wang et al. in view of Chen et al. discloses the method of claim 21.
Baek et al. in view of Wang et al. in view of Chen et al. appears not to explicitly disclose wherein the stacked metallic filament vias are formed permanently and not reversible.
Otsuka et al., however, in Fig. 4B and in paragraphs 3 and 65, discloses the stacked metallic filament vias (52 and 52 in adjacent cell) are formed permanently and not reversible
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Baek et al. in view of Wang et al. in view of Chen et al. with the disclosure of Otsuka et al. to have made the stacked metallic filament vias are formed permanently and not reversible in order to permanently store data (paragraph 3 of Otsuka et al.).
Allowable Subject Matter
Claim 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, the first bias is applied greater than a breakdown voltage of the first filament vias and not for data storage of a resistive memory device utilizing a switching mechanism.
Response to Arguments
Applicant's arguments filed 29 April 2026 have been fully considered but they are not persuasive.
Applicant contends Wang et al. does not teach forming a filament via with a low-k interlayer dielectric as the filament-forming medium.
Examiner notes Wang et al, however, in Fig. 3A and in paragraphs 41 and 42, discloses the interlayer dielectric (322) is formed of a low-k dielectric material in order to use less power to set and reset.
Examiner notes Wang et al., in Fig. 4B, discloses filament via (412B; paragraph 47) formed in a low-k interlayer dielectric (422; paragraphs 41, 42 and 47) as the filament-forming medium (422).
Applicant’s arguments with respect to claim(s) 1-14 and 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claim(s) 15 have been considered but are moot because they are rejected under 35 USC § 112.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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