DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/22/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim 13-16 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 13, 16, 20, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 20200006155 A1; hereinafter Chiang) in view of Kim (US 20230402382 A1; hereinafter Kim), and further in view of Wu (US 20200411415 A1; hereinafter Wu).
Regarding claim 13, FIGS. 1-26E of Chiang teach a method for manufacturing a semiconductor structure (e.g. FIGS. 1-26E), comprising: forming a first channel member (first instance of 35 shown in FIG. 13D) having a longitudinal axis in a first direction (x direction) and a second channel member (another instance of 35 shown in FIG. 13D) spaced apart from the first channel member in the first direction (x direction ¶ [0068]); forming a gate structure (170) between the first channel member (first instance of 35) and the second channel member (second instance of 35) and having a longitudinal axis in a second direction (y direction ¶ [0100]), wherein the gate structure (170) is laterally spaced apart from the first channel member (first instance of 35) and the second channel member (second instance of 35) in the first direction (x direction, see FIG. 23D, see also Examiner annotated FIG. 26D below); forming an isolation structure (105 filled with 110 shown in FIGS. 10A-B, 11A-B) abutting the gate structure (170, see FIGS. 23A-23B ¶ [0081]-[0082]).
Chiang does not teach forming a first trench in the isolation structure; forming a first dummy spacer over a sidewall of the first trench; forming a first liner covering the first dummy spacer; forming a first conductive filling layer over the first liner in the first trench; removing the first dummy spacer to form a first gap exposing a sidewall of the first liner; and forming a first sealing structure to block a first end portion of the first gap.
FIGS. 1-48 of Kim teach a method for manufacturing a semiconductor structure, comprising: forming an isolation structure (GC) abutting a gate structure (G2 ¶ [0065],[0067]; see FIG. 25); forming a first trench (140T) in the isolation structure (GC ¶ [0068], see FIG. 28); forming a first liner (141) covering a sidewall of the first trench (140T ¶ [0071], see FIG. 31); forming a first conductive filling layer (142) over the first liner (141) in the first trench (140T ¶ [0073], see FIG. 31).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the semiconductor structure taught by Chiang with the method of forming the isolation structure taught by Kim for the purpose of decreasing device size, improving current control (¶ [0004]), and increasing a process margin while preventing short-circuiting between the power rail via and the gate (¶ [0005]).
Chiang as modified does not teach forming a first dummy spacer over a sidewall of the first trench, forming the first liner covering the first dummy spacer; removing the first dummy spacer to form a first gap exposing a sidewall of the first liner; and forming a first sealing structure to block a first end portion of the first gap.
FIGS. 1-7 of Wu teach a method for manufacturing a semiconductor structure, comprising: forming a first trench (trench occupied by 270 ¶ [0026]); forming a first dummy spacer (282) over a sidewall of the first trench (trench occupied by 270 ¶ [0026]); forming a first liner (280) covering the first dummy spacer (282 ¶ [0026]); forming a first conductive filling layer (274) over the first liner (280) in the first trench (trench occupied by 270 ¶ [0026], see FIG. 2); removing the first dummy spacer (282) to form a first gap (284) exposing a sidewall of the first liner (outer sidewall of 280 ¶ [0031], see FIG. 3); and forming a first sealing structure (290) to block a first end portion of the first gap (upper end of 284 ¶ [0034], see FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing a semiconductor structure taught by Chiang with the method of forming an air gap taught by Wu for the purpose of reducing capacitance and/or resistance associated with the IC device, thereby reducing associated RC delay (¶ [0014]).
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Regarding claim 16, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13, and FIG. 36 of Kim further teaches further comprising: forming a second trench (trench occupied by CA) in the isolation structure (GC); and forming a second conductive filling layer (CA) in the second trench (trench occupied by CA ¶ [0078]), wherein the first conductive filling layer (142) is in physical contact with the second conductive filling layer (CA ¶ [0077], see FIG. 36).
Regarding claim 20, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13, and Wu further teaches wherein the first dummy spacer (282) is made of Si, SiGe, SiGeB, or SiB (¶ [0029]).
Regarding claim 34, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13, wherein the isolation structure (105 filled by 110) has a longitudinal axis in the second direction (y direction, see FIGS. 23A-B).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Kim and Wu, and further in view of Collins et al. (US 20160005833 A1; hereinafter Collins).
Regarding claim 14, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13.
Chiang as modified does not teach wherein a first air gap is embedded in the first sealing structure.
FIGS. 1-2E of Collins teach a method for manufacturing a semiconductor structure, comprising: forming a first dummy spacer (230) over a sidewall of a first trench (trench occupied by 220, 230 ¶ [0021]); forming a first conductive filling layer (220) over the first dummy spacer (230 ¶ [0021], see FIG. 2A); removing the first dummy spacer (230) to form a first gap (unlabeled gap ¶ [0023], see FIG. 2C); forming a first sealing structure (270) to block a first end portion of the first gap (unlabeled gap ¶ [0032], see FIG. 2E); and wherein a first air gap (275) is embedded in the first sealing structure (270 ¶ [0032], see FIG. 2E).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing a semiconductor structure taught by Chiang with the method of forming air gaps taught by Collins for the purpose of reducing the effective dielectric constant (¶ [0032]) and parasitic capacitance.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Kim and Wu, and further in view of Chen et al. (US 20150044865 A1; hereinafter Chen).
Regarding claim 15, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13.
Chiang as modified does not teach further comprising: forming a second liner on the sidewall of the first trench, wherein a first air gap is sandwiched between the first liner and the second liner.
FIGS. 3-4E of Chen teaches an integrated circuit including forming a first trench (trench occupied by 320/415a ¶ [0030],[0043]); forming a second liner (370a) disposed on a sidewall of the first trench (trench occupied by 320 ¶ [0029],[0043]); forming a first dummy spacer (350a) on the second liner (370a ¶ [0029],[0033],[0043]); forming a first liner (330a) on the first dummy spacer (350a ¶ [0029],[0033],[0043]); removing the first dummy spacer (350a) to form a first gap (340a) exposing a sidewall of the first liner (sidewall of 330a ¶ [0029],[0034],[0043]); wherein the first air gap (340a) is sandwiched between the first liner (330a) and the second liner (370a ¶ [0029]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing the semiconductor structure taught by Chiang with the method of forming the air gap taught by Chen for the purpose of reducing parasitic capacitance and improving resistance-capacitance time delay (¶ [0014]).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang in view of Kim and Wu, and further in view of Ganguly et al. (US 20210408246 A1; hereinafter Ganguly).
Regarding claim 18, Chiang as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 13, and FIGS. 14D-26E of Chiang further teach further comprising: forming a source/drain structure (120) abutting the first channel member (first instance of 35, see FIG. 14D ¶ [0088]), wherein the source/drain structure (120) is substantially aligned with the first channel member (first instance of 35) in the first direction (x direction); forming a source/drain contact (205) connected to a first side of the source/drain structure (upper side of 120 ¶ [0108]).
Chiang as modified does not teach forming a backside conductive via connected to a second side of the source/drain structure, wherein the second side is opposite the first side, wherein the source/drain contact, the source/drain structure, and the backside conductive via are substantially aligned in a third direction.
FIGS. 1A-1H of Ganguly teaches a method for manufacturing a semiconductor structure, comprising: forming a channel member (109) having a longitudinal axis in a first direction (first horizontal direction), wherein the channel member (109) has a first portion (a first portion of 109) and a second portion (another portion of 109) separated from each other (horizontal direction ¶ [0022]); forming a gate structure (162) between the first portion (a portion of 109) and the second portion (another portion of 109) of the channel member (109) and having a longitudinal axis in a second direction (second horizontal direction ¶ [0027]), wherein the gate structure (162) is spaced apart from the first portion and the second portion of the channel member (a portion of 109, another portion of 109) in the first direction (first horizontal direction, see Examiner annotated FIG. 1H below); forming a source/drain structure (130) abutting the first portion of the channel member (a portion of 109), wherein the source/drain structure (130) is substantially aligned with the first portion and the second portion of the channel member (a portion of 109, another portion of 109) in the first direction (first horizontal direction ¶ [0026]); forming a source/drain contact (132) connected to a first side of the source/drain structure (top of 130 ¶ [0030]); and forming a backside conductive via (184) connected to a second side of the source/drain structure (bottom of 130), wherein the second side (bottom of 130) is opposite the first side (top of 130 ¶ [0035]), wherein the source/drain contact (132), the source/drain structure (130), and the backside conductive via (184) are substantially aligned in a third direction (see FIG. 1H).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing a semiconductor structure taught by Chiang with the method of manufacturing backside source/drain contacts taught by Ganguly for the purpose of minimizing contact resistance and enhancing drive current (¶ [0002]).
Regarding claim 19, Kim as modified teaches the method for manufacturing the semiconductor structure as claimed in claim 18, and FIG. 35 of Kim further teaches wherein a thickness of the first conductive filling layer (thickness of 142) in the third direction (DR3) is greater than a thickness of the gate structure (thickness of G1) in the third direction (DR3).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 17 recites the method for manufacturing the semiconductor structure as claimed in claim 16, further comprising: forming a second dummy spacer over a sidewall of the second trench; forming a third liner covering the second dummy spacer; forming the second conductive filling layer over the third liner in the second trench; removing the second dummy spacer to form a second gap exposing a sidewall of the third liner; and forming a second sealing structure to block a second end portion of the second gap, wherein a second air gap is formed adjacent to the third liner.
Kim in view of Wu teaches the method for manufacturing the semiconductor structure as claimed in claim 16.
FIG. 36 of Kim further teaches forming a third liner (161) over a sidewall of the second trench (trench occupied by CA); forming a second conductive filling layer (162) over the third liner (161) in the second trench (trench occupied by CA)
However, the prior art fails to teach or reasonably suggest “forming a second dummy spacer over a sidewall of the second trench; forming the third liner covering the second dummy spacer; removing the second dummy spacer to form a second gap exposing a sidewall of the third liner; and forming a second sealing structure to block a second end portion of the second gap, wherein a second air gap is formed adjacent to the third liner” together with all the limitations of claims 13 and 16-17 as claimed.
Claims 21-22 and 24-32 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 21 recites a method for manufacturing a semiconductor structure, comprising: forming a first fin structure having a longitudinal axis in a first direction, wherein the first fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; forming an isolation feature around the first fin structure; forming a gate structure having a longitudinal axis in a second direction over the isolation feature and spaced apart from the first fin structure in the first direction; partially removing the gate structure to form a first trench; forming an isolation structure in the first trench; forming a first through via structure extending into the isolation structure from a first side, wherein a first air gap is between the first through via structure and the second semiconductor material layers; and forming a second through via extending into the isolation structure from a second side opposite to the first side.
FIGS. 1-48 of Kim teach a method for manufacturing a semiconductor structure, comprising: forming a first fin structure (20) having a longitudinal axis in a first direction (DR1), wherein the first fin structure (20) comprises first semiconductor material layers (21) and second semiconductor material layers (22) alternately stacked (¶ [0089] see FIG. 8); forming an isolation feature (122_1) around the first fin structure (20 ¶ [0045], see FIG. 23); forming a gate structure (G1) having a longitudinal axis in a second direction (DR2) over the isolation feature (122_1) and spaced apart from the first fin structure (20) in the first direction (DR1 ¶ [0042], see FIG. 23); partially removing the gate structure (G1) to form a first trench (trench occupied by GC, see FIG. 25); forming an isolation structure (GC) in the first trench (trench occupied by GC ¶ [0065], see FIG. 25); and forming a first through via structure (140) extending into the isolation structure (GC) from a first side (upper side ¶ [0068]).
FIGS. 1-7 of Wu teach a method for manufacturing a semiconductor structure, comprising: forming a first trench (trench occupied by 270 ¶ [0026]); forming a first dummy spacer (282) over a sidewall of the first trench (trench occupied by 270 ¶ [0026]); forming a first liner (280) covering the first dummy spacer (282 ¶ [0026]); forming a first conductive filling layer (274) over the first liner (280) in the first trench (trench occupied by 270 ¶ [0026], see FIG. 2); removing the first dummy spacer (282) to form a first air gap (284) exposing a sidewall of the first liner (outer sidewall of 280 ¶ [0031], see FIG. 3); and forming a first sealing structure (290) to block a first end portion of the first air gap (upper end of 284 ¶ [0034], see FIG. 4).
However, the prior art fails to teach or reasonably suggest “forming a second through via extending into the isolation structure from a second side opposite to the first side” together with all the limitations of claim 21 as claimed. Claims 22 and 24-27 are allowable insofar as they depend upon and require all the limitations of claim 21.
Claim 28 recites a method for manufacturing a semiconductor structure, comprising: forming first channel members and second channel members aligned in a first direction; forming third channel members spaced apart from the first channel members and the second channel members in a second direction; forming a gate structure between the first channel members and the second channel members and wrapping around the third channel members; removing a portion of the gate structure between the first channel members and the second channel members; forming a first isolation structure between the first channel members and the second channel members and attaching to the gate structure; and forming a conductive via in the first isolation structure, wherein an air gap is sandwiched between the first isolation structure and the conductive via.
FIGS. 1-31B of Zhou teach a method for manufacturing a semiconductor structure, comprising: forming first channel members (NS1) and second channel members (NS2) aligned in a first direction (first horizontal direction ¶ [0051]); forming third channel members (NS3) spaced apart from the first channel members (NS1) and the second channel members (NS2) in the first direction (¶ [0051]); forming a gate structure (GS1-GS2) between the first channel members (NS1) and the second channel members (NS2) and wrapping around the third channel members (NS3 ¶ [0051]).
However, the prior art fails to teach or reasonably suggest “removing a portion of the gate structure between the first channel members and the second channel members; forming a first isolation structure between the first channel members and the second channel members and attaching to the gate structure” together with all the limitations of claim 28 as claimed. Claims 29-32 are allowable insofar as they depend upon and require all the limitations of claim 28.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891