DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 10/28/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zang (US 2016/0293715 A1).
Regard claim 14, Zang discloses a method, comprising: providing a workpiece (combination of 102, 110, 125, 126, and unlabeled portion above 108 in Fig. 1) comprising first and second dummy gate structures (dummy gate structures 126; although Fig. 1 only shows three such structures, Zang discloses that workpieces may comprise more than three as seen in Fig. 16; any two of the dummy gate structures may be considered first gate dummy structures and any other two dummy gate structures may be considered second gate dummy structures), the first dummy gate structures disposed over an active region (combination of 102, 110, and unlabeled portion above 108 in Fig. 1) and the second dummy gate structures disposed over an isolation feature (125) adjacent to the active region, the second dummy gate structures being spaced apart from the active region (spaced by isolation feature 125), a first gate spacer layer (130 in Fig. 2) disposed along sidewalls of the first dummy gate structures, and a second gate spacer layer (142 in Fig. 3) disposed along sidewalls of the second dummy gate structures;
performing an etching process to selectively recess the second gate spacer layer (top portions of 142 are selectively removed relative to the bottom portions as seen in the transition between figures 5 and 6);
selectively removing the first dummy gate structures and the second dummy gate structures to form gate trenches (“an opening above polysilicon formation 126 (FIG. 5) can be formed and formations 126 can be removed”, ¶ 0053);
forming metal gate stacks in the gate trenches (“layer 162 which can be a work function metallic layer can be formed over layer 161. A metal formation 166 e.g., formed of tungsten (W) can be formed over layer 161,” ¶ 0053); and
after the forming of the metal gate stacks, selectively removing the first gate spacer layer to form air gaps (air gaps 182 in Fig. 10) over the active region.
Regarding claim 15, Zang further discloses wherein the selectively recessing of the second gate spacer layer comprises:
forming a patterned mask (152 in Fig. 5) over the workpiece, the patterned mask covering the first gate spacer layer (it covers the side surfaces of the first gate spacer layer) and exposing the second gate spacer layer (exposed from above); and
selectively removing top portions of the second gate spacer layer relative the second gate dummy structures (see transition between Figs. 5 and 6).
Regarding claim 16, Zang further discloses that after the performing of the etching process, a top surface of the remaining portion of the second gate spacer layer is above a top surface of the active region (see Fig. 6).
Regarding claim 17, Zang further discloses before the selectively removing of the first dummy gate structures and the second dummy gate structures, depositing a first dielectric layer (152 in Fig. 5) over the workpiece, wherein the first dielectric layer covers the first gate spacer layer and a remaining portion of the second gate spacer layer (bottom third of layer 142 in Fig. 5, this “portion” and the portion above the remaining portion up to the top surface 126 both remain as seen in Fig. 6);
depositing a second dielectric layer (154 in Fig. 12) over the first dielectric layer; and
performing a planarization process to the workpiece to expose top surfaces of gate electrodes in the first and second dummy gate structures and expose the first gate spacer layer without exposing the remaining portion of the second gate spacer layer (see transition from Fig. 5 to Fig. 6; the “remaining portion” of the second gate spacer layer is not exposed as it is still covered by an additional portion of the second gate spacer layer).
Regarding claim 19, Zang further discloses wherein heights of portions of the metal gate stack (height of portion 162 in Fig. 6) over the isolation feature are greater than heights of portions of the metal gate stacks (height of portion 166) over the active region (see Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zang as applied to claim 14 above, and further in view of Egard et al. (US 9,117,753 B2).
Regarding claim 18, Zang discloses the method of claim 14, as discussed above. Zang further discloses wherein a top surface of the isolation feature is below a top surface of the active region (see Fig. 1).
Zang does not disclose wherein the isolation feature comprises a concave surface.
Egard, in the same field of endeavor, discloses forming isolation features to have a concave surface (isolation feature 116 in Fig. 4b). There was a benefit to forming isolation features to slightly wrap around the layer immediately above in that it increases the amount of isolation. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form the isolation feature of Zang to have a concave surface as taught by Egard for this benefit.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zang as applied to claim 14 above, and further in view of Hsu et al. (US 2019/0172752 A1).
Regarding claim 20, Zang discloses the method of claim 14, as discussed above. Zang does not disclose discloses wherein each of the first gate spacer layer and the second gate spacer layer comprises a multi-layer structure that includes a first layer and a second layer extending along a sidewall surface of the first layer, wherein the performing of the etching process selectively recesses the second layer of the second gate spacer layer without substantially etching the first layer of the second gate spacer layer.
Hsu, in the same field of endeavor, discloses a first gate spacer layer (28 in Fig. 10) and a second gate spacer layer (60) wherein each of the first gate spacer layer and the second gate spacer layer comprises a multi-layer structure that includes a first layer and a second layer extending along a sidewall surface of the first layer, wherein the performing of the etching process selectively recesses the second layer of the second gate spacer layer without substantially etching the first layer of the second gate spacer layer (see Figs. 2-10). There was a benefit to using a plurality of distinct materials in that it allows for precise control of which portion is removed using material selective removal. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form each of the first gate spacer layer and the second gate spacer layer to comprise a multi-layer structure that includes a first layer and a second layer extending along a sidewall surface of the first layer, wherein the performing of the etching process selectively recesses the second layer of the second gate spacer layer without substantially etching the first layer of the second gate spacer layer for this benefit.
Response to Arguments
Applicant’s arguments with respect to claim(s) 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/C.A.C/Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815