Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 26, 2025 has been entered.
Election/Restrictions
Claims 1-5, 7, 9-11, 13, 14, 21, 22, and 24-30 are pending in this application.
Applicant elected without traverse of group I, species B (claims 1-7, 9-11, 13-14, and 21-28) in the reply filed on March 25, 2025. Newly added claims 29 and 30 also read on the elected group.
The Examiner notes that claims 1-5, 7, 9-11, 13, 14, 21, 22, and 24-30 are examined.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed November 26, 2025. Claims 1, 9, and 21 are amended. Claims 6 and 23 are cancelled. Claims 29-30 are newly added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2020/0105875 A1) in view of Murthy (US 2006/0148151 A1).
With respect to claim 1, Li teaches:
A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin (epitaxial layer 114) over a semiconductor substrate (substrate 100 which is a silicon wafer according to para. 16);
forming a gate structure (dummy gate layer 131 later replaced by gate electrode 146 in Fig. 17B) over a first portion (portion covered by 131) of the semiconductor fin;
etching a source/drain recess (recess 115) in a second portion (portion not covered by 131) of the semiconductor fin (Fig. 10, para. 29 “the epitaxial layer 114 is etched using dummy gates 131 as masks to form first recesses 115 on either side of the dummy gates 131”);
performing a source/drain etching and epitaxy process to form a source/drain epitaxial structure (epitaxial source/drain regions 139) over the second portion of the semiconductor fin,
wherein performing the in- situ source/drain etching and epitaxy process comprises:
performing a dry etching process to adjust a profile of the source/drain recess (Fig. 12 para. 34, “second recesses 138 are formed in the epitaxial layer 114 using the gate spacers 137 as a mask.” “recesses 138 may extend through the epitaxial layer 114 into the substrate 100. The second recesses 138 may be formed by an anisotropic etch using Cl.sub.2, HBr, HF, SF.sub.6, CHF.sub.3, CH.sub.2F.sub.2, CF.sub.4, SO.sub.2, NH.sub.3, NF.sub.3, He, SiCl.sub.4, O.sub.2, Ar, H.sub.2 and/or other gaseous etchants.”);
and after the dry etching process, epitaxially growing the source/drain epitaxial structure (139) in the source/drain recess (138) in the chamber (para. 35, Fig. 13 “the epitaxial source/drain regions 139 may be formed by being epitaxially grown in the second recesses 139. In some embodiments, the epitaxial source/drain regions 139 may extend”);
and forming a gate spacer (gate spacer 137) at a sidewall of the gate structure (dummy gate structure which is later replaced by 146) prior to etching the source/drain recess (formed in Fig. 11, s/d recess etched in Fig. 12), wherein the source/drain etching is performed such that at least a portion of a bottom surface of the gate spacer lower than a top surface of the semiconductor fin is exposed by the source/drain recess (see Fig. 12) and has an elevation increasing toward the sidewall of the source/drain recess (bottom of spacers is angled, see Fig. 11, 12, or 13).
Li does not teach:
performing an in-situ source/drain etching
performing a dry etching process to adjust a profile of the source/drain recess in a chamber
epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber
Murthy teaches in Para. 57:
performing an in-situ source/drain etching (“a process to perform in-situ recessed source drain etch”)
performing a dry etching process to adjust a profile of the source/drain recess in a chamber (“This process uses a set of etch gases and a set of deposition gases to form junction regions having facets 220 and 230”)
epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber (“followed immediately by deposition of source drain material (e.g., deposition of material 370 and 380) is performed in a UHV CVD chamber”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Murthy into the method of Li to perform an in-situ etch and epitaxial growth in the same chamber. The ordinary artisan would have been motivated to modify Li/Chiang in the manner set forth above for the purpose of “reduc[ing] undesired impurities including carbon, oxygen and nitrogen” (para. 55 of Murthy).
With respect to claim 2 and 3, Li does not specify whether either etch uses plasma or not. Therefore, Li is silent to the limitations of claim 2:
wherein the dry etching process is performed using gas-phase etchant without using a plasma.
Murthy teaches in para. 42:
“Suitable non-plasma etch chemistries for removing undesired portions of substrate 120, such as at surfaces 170 and 180 to form junction regions 270 and 280 include chlorine (Cl.sub.2), hydrochloric acid (HCl), fluorine (F.sub.2), bromine (Br.sub.2), HBr and/or other etch processes capable of removing portions of substrate 120”
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a non-plasma etch process for the dry etch that forms a recess in a substrate because the known technique of dry etching without plasma was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 3, Li is silent to:
wherein etching the source/drain recess is performed using a plasma etching process.
Murthy teaches in para. 42:
“Plasma etches including chemistries of SF.sub.6, NF.sub.3 or the like are possible as alternative embodiments”
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a plasma etch process for source/drain recess because the known technique of plasma etching to form a recess in a substrate was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 4, Li further teaches:
wherein etching the source/drain recess is performed using a fluorine-based chemistry (para. 29 “the etch may comprise a dry etch process using Cl.sub.2, HBr, HF, SF.sub.6, CHF.sub.3, CH.sub.2F.sub.2, CF.sub.4, SO.sub.2, NH.sub.3, NF.sub.3, He, SiCl.sub.4, O.sub.2, Ar, H.sub.2 and/or other gaseous etchants”), and the dry etching process is performed using a chlorine- based chemistry (para. 34 “The second recesses 138 may be formed by an anisotropic etch using Cl.sub.2, HBr, HF, SF.sub.6, CHF.sub.3, CH.sub.2F.sub.2, CF.sub.4, SO.sub.2, NH.sub.3, NF.sub.3, He, SiCl.sub.4, O.sub.2, Ar, H.sub.2 and/or other gaseous etchants”).
With respect to claim 5, Murthy further teaches:
wherein the in-situ source/drain etching and epitaxy process is performed without vacuum break (para. 58 of Murthy “an etch process using a flow rate of pure chlorine gas of between five and ten SCCM for a period of between ten and 300 minutes (e.g., a period of 30, 40, 50, 60, 70, 80, 90, 100 or 120 minutes) is used to form regions 270 and 280. Following pump-out of the pure chlorine gas, a deposition process occurs to form materials 370 and 380 in regions 270 and 280, in the same chamber, without exposing the inside of the chamber to the outside air.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Li in view of Murthy as explained above.
With respect to claim 7, Li further teaches:
wherein the in-situ source/drain etching and epitaxy process is performed such that a top portion of the source/drain epitaxial structure (139) extends beyond a sidewall of the gate spacer (117) facing away from the gate structure (see Fig. 13, top surface of 139 extends beyond bottom of the spacers).
With respect to claim 29, Li further teaches:
wherein after epitaxially growing the source/drain epitaxial structure (epitaxial source/drain structure 139) in the source/drain recess (second recess 138), the source/drain epitaxial structure is in contact with the portion of the bottom surface of the gate spacer previously exposed by the source/drain recess (in contact with triangular spacer extension 117, see Fig. 13).
Claims 9-11, 13-14, 21-22, 24-26, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2020/0105888 A1) in view Li (US 2020/0105875 A1).
With respect to claim 9, Hsu teaches in the embodiment of Figs. 1-10:
A method for manufacturing a semiconductor device, comprising:
forming a semiconductor fin (Fig. 1, para. 23, “one or more fin structures 20 are fabricated over a substrate 10) over a semiconductor substrate (10);
forming a gate structure (Fig. 2D, para. 33 “patterning operations are performed so as to obtain a gate structure including a gate electrode layer 45”) over a first portion of the semiconductor fin (20) (Fig. 2D);
performing a first etching process to etch a source/drain recess (source/drain recess 24) in a second portion (portion not covered by the gate structure) of the semiconductor fin (20) (para. 37 “as shown in FIGS. 4A and 4B, a source/drain region of the fin structure 20 not covered by the gate structure 40 is etched down (recessed) to form a source/drain recess 24”);
performing a second etching process to push a sidewall of the source/drain recess toward the first portion (portion covered by gate structure) of the semiconductor fin (20) (Fig. 5A-5B, para. 39-40, “the source/drain recess 24 of the fin structure 20 is treated to form the octagonal shape” As seen in Fig. 4B and 5B, the sidewall is pushed in the left/right direction toward the portion of the fin under the gate structure);
and after the second etching process, epitaxially growing a source/drain epitaxial structure in the source/drain recess (Fig. 6A-6B, para. 44, “After the octagonal source/drain recess 25 is formed, one or more source/drain epitaxial layers 60 are formed in the source/drain recess 25”).
and forming a gate spacer (sidewall spacers 55) at a sidewall of the gate structure (45) prior to the first etching process
wherein the first etching process is performed such that a bottom surface of the gate spacer (55) is in contact with the semiconductor substrate (Fig. 4B),
Hsu fails to teach:
the second etching process is performed such that at least a portion of the bottom surface of the gate spacer lower than a top surface of the semiconductor fin is exposed by the source/drain recess and has an elevation increasing toward the sidewall of the source/drain recess.
Li teaches in Fig. 12:
the second etching process (process that forms second recess 138) is performed such that at least a portion of the bottom surface of the gate spacer (triangular spacer extensions 117) lower than a top surface of the semiconductor fin is exposed by the source/drain recess (138) and has an elevation increasing toward the sidewall of the source/drain recess (117 is triangular shaped and slanted upward toward sides of recess).
Hsu discloses the claimed invention except for the second etching exposing the spacer lower than the top surface of the fin with an elevation increasing toward the sidewall of the recess. Li teaches that it is known to create the recess and spacer with the claimed geometry as shown in Fig. 12. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu as taught by Li in order to “block diffusion of metal from metal contacts to source/drain regions, thereby reducing parasitic capacitance of the device” (para. 33 of Li). See MPEP 2144.
With respect to claim 10, Hsu further teaches:
wherein the second etching process (process between Figs. 4B and 5B) is a dry etch process without using a plasma (para. 40 “the treatment is a chemical etching in some embodiments. The treatment is performed using a mixed gas of SiH.sub.4, HCl and H.sub.2 in some embodiments. No plasma assistance is used in some embodiments.”)
With respect to claim 11, Hsu further teaches:
wherein the second etching process is performed such that the source/drain recess is deepened (para. 39 “the source/drain recess 24 of the fin structure 20 is treated to form the octagonal shape.” In going from the recess 24 to the octagonal recess 25 parts of the recess are deepened in the left/right and/or up/down direction. Further, para. 43 teaches “In some embodiments, the (110) surface is located closer to the channel (just below the gate) than the center of the sidewall spacer,” teaching that the left and right sidewalls of the recess are deepened.)
The Examiner notes that for the purpose of this rejection, the dictionary definitions of “deep” relied upon are “extending far downward” and/or “extending far laterally from the center”
With respect to claim 13, Li further teaches:
wherein epitaxially growing the source/drain epitaxial structure (source/drain regions 139) is performed such that the source/drain epitaxial structure (13*) is in contact with the exposed portion of the bottom surface of the gate spacer (117) (see Fig. 13).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hsu in view of Li as explained above.
With respect to claim 14, Li further teaches:
wherein an interface between the bottom surface of the gate spacer (117) and the source/drain epitaxial structure (139) is inclined with respect to a top surface of the semiconductor substrate (see Fig. 13).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hsu in view of Li as explained above.
With respect to claim 21, Hsu teaches in the embodiment of Figs. 1-10:
forming an active region comprising a channel region (channel layer 20A);
forming a gate spacer (sidewall spacer 55) over the channel region (20A);
after forming the gate spacer (sidewall spacer 55), performing a first etching process to etch a source/drain recess (source/drain recess 24) in the active region (portion of channel region 20A that is etched and replaced by source/drain) and adjacent the channel region (portion of channel region 20A that is not etched) such that a top surface of the channel region (20A) is in contact with a bottom surface of the gate spacer (55) (see Fig. 4B);
performing a second etching process to push a sidewall of the source/drain recess toward the channel region (20A) (Fig. 5A-5B, para. 39-40, “the source/drain recess 24 of the fin structure 20 is treated to form the octagonal shape” As seen in Fig. 4B and 5B, the sidewall is pushed in the left/right direction toward the portion of the fin under the gate structure),
after performing the second etching process,
forming a first source/drain epitaxial layer (first epitaxial layer 62) on the active region (20A), wherein the first source/drain epitaxial layer extends below the gate spacer (55) (Fig. 6B);
and forming a gate structure (para. 33 “gate structure including a gate electrode layer 45”) extending over the channel region (20A) of the active region.
Hsu fails to teach:
wherein the second etching process is performed such that a portion of the bottom surface of the gate spacer is lower than a top surface of the channel region and has an elevation increasing toward the sidewall of the source/drain recess;
Li teaches in Fig. 12:
wherein the second etching process (process that forms second recess 138) is performed such that a portion of the bottom surface of the gate spacer (triangular spacer extensions 117) is lower than a top surface of the channel region (top surface of protruding portion of 114) and has an elevation increasing toward the sidewall of the source/drain recess (see Fig. 12);
Hsu discloses the claimed invention except for the second etching exposing the spacer lower than the top surface of the fin with an elevation increasing toward the sidewall of the recess. Li teaches that it is known to create the recess and spacer with the claimed geometry as shown in Fig. 12. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Hsu as taught by Li in order to “block diffusion of metal from metal contacts to source/drain regions, thereby reducing parasitic capacitance of the device” (para. 33 of Li). See MPEP 2144.
With respect to claim 22, Hsu further teaches:
wherein the first source/drain epitaxial layer (62) is U- shaped (Fig. 6B).
With respect to claim 24, Li further teaches:
wherein an interface between the bottom surface of the gate spacer (bottom of 117) and the first source/drain epitaxial layer (139) is inclined with respect to a top surface of the channel region (top surface of 114).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hsu in view of Li as explained above.
With respect to claim 25, Hsu further teaches:
forming a second source/drain epitaxial layer (second epitaxial layer 64) over the first source/drain epitaxial layer (first epitaxial layer 62), wherein the second source/drain epitaxial layer is in contact with a sidewall of the gate spacer (55) (Fig. 6B, the corner of 64 is in direct contact with the bottom of the sidewall of 55 and/or in indirect contact through third epitaxial layer 66).
With respect to claim 26, Li further teaches:
forming a source/drain contact (source/drain contacts 154) over the source/drain epitaxial layer (139); and forming a silicide region (silicide contact 156) between the source/drain contact (154) and the source/drain epitaxial layer (139).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Li into the method of Hsu/Li to include a source/drain contact and a silicide region. The ordinary artisan would have been motivated to modify Hsu/Li in the manner set forth above for the purpose reducing the Schottky barrier height of the gate contact (para. 46 of Li).
With respect to claim 30, Li further teaches:
wherein after forming the first source/drain epitaxial structure (epitaxial source/drain structure 139) in the source/drain recess (second recess 138) of the active region, the first source/drain epitaxial structure is in contact with the portion of the bottom surface of the gate spacer previously exposed by the source/drain recess (in contact with triangular spacer extension 117, see Fig. 13).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Hsu in view of Li as explained above.
Claim 27 is rejected under 35 U.S.C. as being unpatentable over Hsu (US 2020/0105888 A1) in view Li (US 2020/0105875 A1) as applied to independent claim 21 above and further in view of Murthy (US 2006/0148151 A1).
With respect to claim 27, Hsu-1/Chiang teaches all limitations of independent claim 21 upon which claim 27 depends.
Hsu/Li does not explicitly specify:
Wherein the second etching process is an in-situ source/drain etching
Murthy teaches in Para. 57:
performing an in-situ source/drain etching (“a process to perform in-situ recessed source drain etch”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Murthy into the method of Hsu/Li to perform an in-situ etch. The ordinary artisan would have been motivated to modify Hsu/Li in the manner set forth above for the purpose of “reduc[ing] undesired impurities including carbon, oxygen and nitrogen” (para. 55 of Murthy).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Li (US 2020/0105875 A1) in view of Murthy (US 2006/0148151 A1) as applied to independent claim 1 above and further in view of Mochizuki (US 9,991,382 B1)
With respect to claim 28, Li/Murthy teaches all limitations of claim 1 upon which claim 28 depends. Li/Murthy fails to teach:
wherein a topmost position of the source/drain epitaxial structure is lower than a top surface of the semiconductor fin.
Mochizuki teaches in Fig. 9:
wherein a topmost position of the source/drain epitaxial structure (source/drain structure 22) is lower than a top surface of the semiconductor fin (semiconductor fin 10F).
Li/Murthy discloses the claimed invention except for the topmost position of the source/drain structure is lower than a top surface of the semiconductor fin. Mochizuki discloses that it is known in the art to provide a topmost position of a source/drain region lower than a top surface of a semiconductor fin. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the method of Li/Murthy with the layout of Mochizuki, in order to leave space besides the fin and above the source/drain structure for additional elements (See MPEP 2144) and/or because changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B).
Response to Arguments
Applicant’s arguments with respect to claims 1, 9, 21, and their dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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