Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 4/13/2026.
Claims 1-6, 8-15, and 21-26 are currently pending.
Claims 1, 10, and 21 have been amended.
Claims 1-6, 8-15, and 21-26 have been examined.
Response to Arguments
Applicant's arguments filed 4/13/2026 have been fully considered but they are not persuasive. With regards to claim 1, Applicant appears to assert that Xiao does not disclose “a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess.” However, the Office Action of 1/13/2026 explains of page 5 that Xiao does disclose the claim element cited. While Xiao does not specifically show in the figures a top view, it is by necessity has the topmost portion of the first and second source/drain recess because as shown in Figure 13 is connected to the width of the P-type semiconductor channel 305 or N-type semiconductor channel 405. The top portion of the P-type source/drain 306 would be necessity be related to the length D1 and the top portion of the N-type source/drain 406 would by necessity be related to the length of D2 and the length D1 is greater than the length of D2.
The Applicant further asserts that Xiao does not teach or suggest “wherein the first source/drain recess is formed adjacent to a first gate structure extending in a first direction in a top-down view, and wherein the second source/drain recess is formed adjacent to a second gate structure extending in the first direction in the top-down view” or “wherein the first width and the second width are defined along a second direction in the top-down view, the second direction perpendicular to the first direction.” However, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, Chiang discloses “wherein the first source/drain recess is formed adjacent to a first gate structure extending in a first direction in a top-down view, and wherein the second source/drain recess is formed adjacent to a second gate structure extending in the first direction in the top-down view” or “wherein the first width and the second width are defined along a second direction in the top-down view, the second direction perpendicular to the first direction.” Therefore, device made by the modification of Chaing as modified by Iguchi, and Xiao would disclose all the elements of the amended claim. See below for more details.
Similar arguments are asserted for claims 10 and 21. These are arguments are refuted for similar reasons as claim 1 above.
See below for more detail on the rejections.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "wherein the first source/drain recess is formed adjacent to a first gate structure extending in a first direction in a top-down view, and wherein the second source/drain recess is formed adjacent to a second gate structure extending in the first direction in the top-down view" must be shown or the feature(s) canceled from the claim(s). While Fig.1 shows a gate structure 108 no figures appear to show that there is a second gate structure. Figs. 21 and 23 show a gate stack 316, however it is unclear if these are the same gate structure or a discrete first and second gate structure. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. US 20190067113 (hereinafter Chiang) and Iguchi et al. US 5734185 A (hereinafter Iguchi) in further view of Xiao US 20210066292 A1 (hereinafter Xiao).
Regarding Claim 1:
A method of fabricating a semiconductor device (Chiang, paragraph [0051], "FIGS. 2-21D show various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure."), comprising:
performing an ion implantation process into a first device region of a substrate, (Chiang, Fig. 2, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region.) …
after performing the ion implantation process (Chiang, Fig.2 of the ion implantation process is done prior to other processing steps including is prior to subsequent photolithography and etch steps described below.) performing a first photolithography and etch process to simultaneously (Chiang, Figs. 12A-12D, paragraph [0079], "The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations." The first and second source/drain region can be formed in one lithography and etching operation therefor could be done simultaneously.) form a first source/drain recess for a first device in the first device region and a second source/drain recess (Chiang, Fig. 12A-12D, S/D space 22.) for a second device in a second device region different than the first device region (Chiang, Fig. 1, paragraph [0038], "a first GAA FET Q1 and a second GAA FET Q2 are disposed over a substrate 10." There are two devices Q1 and Q2 which each have a source/drain region 40 which as shown in method steps it's shown that there are S/D space 22 in the source/drain region and the source/drain region of the second device Q2 is different from the first Q1 source/drain region.) wherein the first source/drain recess is formed adjacent to a first gate structure extending in a first direction in a top-down view (Chiang discloses in Fig. 12C shows that the source/drain recess 22 is adjacent to the gate structure 38 and would extend in first direction such as in the X-direction.), and wherein the second source/drain recess is formed adjacent to a second gate structure extending in the first direction in the top-down view; (Chiang discloses in Fig. 12D, shows that the source/drain space 22 adjacent to the gate structure 38 and would extend in first direction such as in the X-direction.);
wherein a first depth of the first source/drain recess is greater than a second depth of the second source/drain recess, (Chiang, Fig. 23, paragraph [0100], “FIG. 23, the four-wire contact structure and two-wire contact structure are formed on the same substrate 10.” Therefore, on substrate the first depth of the source/drain recess is greater than the second source/drain recess.)…
wherein the first width (Chiang would by necessity have a first width of the source/drain of the device of Fig. 12C.) and the second width (Chiang would by necessity have a second width of the source/drain of the device of Fig. 12D.) are defined along a second direction in the top-down view (The device of 12C and 12D would by necessity have a width that in the y-direction that goes into and out of the paper that would be defined by the channel width in the y-direction as well.), the second direction perpendicular to the first direction. (The y-direction is perpendicular to the x-direction.)
Chiang appears to be silent on "the ion implantation process includes performing a plurality of ion implantation processes at different implant angles;" and “a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess”.
Iguchi, which teaches a MOS transistor where the channel region is level with the source/drain region and can be under sidewall spacers (Iguchi, Abstract), discloses:
wherein the ion implantation process includes performing a plurality of ion implantation processes at different implant angles (Iguchi, Fig. 4(l), col. 15, lines 51-56.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang to have the ion implantation process includes performing a plurality of ion implantation processes at different implant angles as modified by Iguchi for the purpose of implanting dopant ions underneath sidewall region. (Iguchi, Fig. 4(l), col. 15, lines 57-65)
Neither Chiang or Iguchi appear to disclose “a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess”.
However, Xiao, which teaches CMOS FinFETs (Xiao, [0004]) which have one the source/drain region widths being defined by the channel length ([0011]), discloses:
a first width of a topmost portion of the first source/drain recess (Fig. 13, drain region 306 having a width that is defined by D1 the width of the channel for P-type device) is greater than a second width of a topmost portion of the second source/drain recess (Fig. 13, drain region 406 having a width that is defined by D2 the width of the channel for N-type device. Also, [0024], the source/drain regions of the P-type device is greater than the source/drain regions of the N-type device.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang and Iguchi to have a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess as modified by Xiao for the purpose of reducing short channel effects, improve the integration level of device, and improve the power of the device. (Xiao, [0075])
Regarding Claim 2, Chiang, Iguchi, and Xiao disclose all the elements of claim 1.
Chiang further teaches:
The method of claim 1, further comprising forming a first source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40 in Q1 and contact layer 60 in Q1) within the first source/drain recess (Chiang, Fig. 1, S/D space 22 in Q1) and a second source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40 and contact layer 60 in Q2) within the second source/drain recess. (Chiang, Fig. 1, S/D space 22 in Q2 and paragraph [0083], "After the second S/D space 22 is formed, a source/drain epitaxial layer 40 is formed".)
Regarding Claim 6, Chiang, Iguchi, and Xiao disclose all the elements of claim 1.
Chiang further teaches:
The method of claim 1, further comprising:
performing a second photolithography and etch process to simultaneously form a third source/drain recess for a third device in the first device region and a fourth source/drain recess for a fourth device in the second device region (Chiang, Figs. 12A-12D, paragraph [0061], "But the number of the fin structures is not limited to two, and may be as small as one and three or more" and paragraph [0079], "The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations." Therefor more than three or more devices can be processed in one lithography and etching step.);
wherein a third depth of the third source/drain recess is greater than a fourth depth of the fourth source/drain recess. (Chiang teaches that one or more lithography and etch operations can be performed and the duplication of parts has no patentable significance unless a new and unexpected result is produced. Therefore, a third source/drain recess being greater than a fourth source/drain recess being merely a duplication of the first source/drain recess being greater than the second source/drain recess. MPEP 2144.04 (VI.)(B.)
Regarding Claim 8, Chiang, Iguchi, and Xiao disclose all the elements of claim
Chiang further teaches:
The method of claim 1, wherein the ion implantation process further includes performing the ion implantation process into a portion of the second device region (Chiang, Fig. 2, and paragraph [0052], "As shown in FIG. 2, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region." Therefore, the ion implantation process in the second device region), wherein the first photolithography and etch process simultaneously forms the first source/drain recess, the second source/drain recess, and a third source/drain recess for a third device in the portion of the second device region. (Chiang, Figs. 12A-12D, paragraph [0061], "But the number of the fin structures is not limited to two, and may be as small as one and three or more", and paragraph [0079], "The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations." Therefor this can be processed in one lithography and etching step. Therefore, there can be three or more fin structures which equals there being more devices that are made around the fin structure.)
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Iguchi, and Xiao as applied to claims 1 and 8 above, and further in view of Murthy et al. US 20160240534 (hereinafter Murthy).
Regarding Claim 3, Chiang, Iguchi, and Xiao teach all the elements of claim 1.
Chiang, Iguchi, and Xiao appear to be silent regarding “ the ion implantation process increases an etch rate of a first source/drain region of the first device.”
Murthy, which teaches increasing the effect gate length through deposition of a gate control layer, discloses:
The method of claim 1, wherein the ion implantation process increases an etch rate of a first source/drain region of the first device. (Murthy paragraph [0021], “The dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process.” Therefore, by implanting ions into the first region of the first device the etch rate of the material is increased based on the choice of dopants.)
Murthy thus establishes that it is known in the art that that ion implantation can be controlled to achieve a specific etch rate. Furthermore, to the Examiner’s understanding, there is no evidence of criticality in the specification for a specific etch rate of a first source/drain region of the first device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Murthy reference to achieve a specific etch rate, as it has been held obvious the ion implantation process done to a specific region leads to a related change in the etch rate of the region.
Regarding Claim 9, Chiang, Iguchi, and Xiao disclose all the elements of claim 8.
Chiang, Iguchi, and Xiao appear to be silent on “a third depth of the third source/drain recess is both greater than the second depth of the second source/drain recess and substantially equal to the first depth of the first source/drain recess.”
Murthy, which teaches increasing the effect gate length through deposition of a gate control layer, discloses:
The method of claim 8, wherein a third depth of the third source/drain recess is both greater than the second depth of the second source/drain recess and substantially equal to the first depth of the first source/drain recess. (As taught by Murthy, the ion implantation would lead to an increased depth of the source/drain recess (See Murthy, paragraph [0021].) compared to areas that would not have the dopants implanted in the area of the recess. Therefore, the third and first source/drain recess would be substantially equal to each other and the second source/drain would have a smaller depth.)
The Murthy reference teaches that ion implantation can be controlled to achieve a specific etch rate. Therefore, the ion implantation process done to a region is a change which leads to related change in the etch rate of the region making this a result effective variable and it would have been obvious to a person skilled in the art to optimize it for that purpose. MPEP 2144.05 (II)(B).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Iguchi, and Xiao as applied to claim 1 and further in view of Chang et al. US 20170351802 (hereinafter Chang).
Regarding claim 4, Chiang, Iguchi, and Xiao teach the elements of claim 1 as recited above.
The combination of Chiang, Iguchi, and Xiao do not appear to disclose "wherein the first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device".
Chang, which teaches a method of fabricating an integrated circuit, discloses:
wherein the first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device(Chang, Fig. 3, Core Logic Device 330, paragraph [0026], "PMOS transistors 331, 333, 335, 337 of the core logic devices 330" and "the NMOS transistors 332, 334, 336, 338 of the core logic devices 330".), and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device. (Chang, Fig. 3, SRAM Block 310, paragraph [0025[, "The SRAM block 310 includes PMOS pull-up transistors 312, NMOS pull-down transistors 314, and NMOS access transistors 316. Similarly, the SRAM block 320 includes PMOS pull-up transistors 322, NMOS pull-down transistors 324, and NMOS access transistors 326.")
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang, Iguchi, and Xiao to have e first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device as modified by Chang for purposes of allowing decoupling of the threshold voltage of a transistor (e.g., a SRAM transistor) from the threshold voltage of a SVT transistor, thereby allowing adjustment of the threshold voltage or driving current of the decoupled transistor independently from the SVT transistor. See Chang paragraph [0010].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Iguchi, and Xiao as applied to claim 2, and further in view of Liaw et al. US 20200013776 A1 (hereinafter Liaw).
The following annotated figure form Liaw will be used in discussion:
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Regarding Claim 5, Chiang, Iguchi, and Xiao disclose all the elements of claim 2.
Chiang further teaches:
The method of claim 2, wherein the first source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40in Q1 and contact layer 60) is formed over a first fin, (Chiang, Fig. 1, the contact layer 60 extends above the top layer semiconductor wire 25 in Q1),
Chiang, Iguchi, and Xiao do not appear to disclose :
wherein the first source/drain feature merges with a third source/drain feature formed over a second fin adjacent to the first fin.
Liaw, which teaches a fin structure with a source/drain region (Liaw, Abstract), disclose:
wherein the first source/drain feature (annotated Fig. 4B, S/D1) merges with a third source/drain feature (S/D3) formed over a second fin (F2) adjacent to the first fin (F1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang as modified by Iguchi and Xiao to have the first source/drain feature merges with a third source/drain feature formed over a second fin adjacent to the first fin as further modified by Liaw for the purpose of tying together multiple fins in a multi-fin N-type or P-type FinFET well region. (Liaw, [0040]-[0041].)
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao, and Murthy.
Regarding Claim 10:
A method (Chiang, paragraph [0051], "FIGS. 2-21D show various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure."), comprising:
simultaneously etching the first source/drain region to form a first source/drain recess (Chiang, Fig. 12A-12D, S/D space 22) for a first memory device and the second source/drain region to form a second source/drain recess for a first logic device (Chiang, Figs. 12A-12D, paragraph [0079], "The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations." The first and second source/drain region can be one in one lithography and etching operation therefor could be done simultaneously.) ; and
forming a first source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40 and contact layer 60 in Q2) within the first source/drain recess (Chiang, Fig. 12A-12D, S/D space 22 in Q2) adjacent to a first gate structure (Fig. 1, gate structure including gate electrode layer 58, work function adjustment layer 56, gate electric layer 53 and interfacial layer 52 around Q2.) and a second source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40 and contact layer 60 in Q1) within the second source/drain recess (Chiang, Fig. 12A-12D, S/D space 22 in Q1) adjacent to a second gate structure(Fig. 1, gate structure including gate electrode layer 58, work function adjustment layer 56, gate electric layer 53 and interfacial layer 52 around Q1.), wherein the first and second gate structures extend in a first direction in a top-down view; (Chiang discloses in Fig. 12C and D, shows that first and second gate structures would extend in first direction such as in the X-direction.),
wherein a first depth of the first source/drain recess is greater than a second depth of the second source/drain recess; (Chiang, Fig. 23, paragraph [0100], “FIG. 23, the four-wire contact structure and two-wire contact structure are formed on the same substrate 10.” Therefore, on substrate the first depth of the source/drain recess is greater than the second source/drain recess.)…
wherein the first width (Chiang would by necessity have a first width of the source/drain of the device of Fig. 12C.) and the second width (Chiang would by necessity have a second width of the source/drain of the device of Fig. 12D.) are defined along a second direction in the top-down view (The device of 12C and 12D would by necessity have a width that in the y-direction that goes into and out of the paper that would be defined by the channel width in the y-direction as well.), the second direction perpendicular to the first direction. (The y-direction is perpendicular to the x-direction.)
Chiang appears to be silent on “performing an ion implantation into a memory device region or a logic device region to modify an etch rate of one of a first source/drain region within the memory device region or a second source/drain region within the logic device region” and, while Chiang does show “wherein a first depth of the first source/drain feature is different than a second depth of the second source/drain feature,” Chiang appears silent as to reason why the first depth of the first source/drain feature would be different than the second depth of the second source drain feature.
Furthermore, Chiang does not appear to disclose “a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess”.
However, Xiao, which teaches CMOS FinFETs (Xiao, [0004]) which have one the source/drain region widths being defined by the channel length ( [0011]), discloses:
a first width of a topmost portion of the first source/drain recess (Fig. 13, drain region 306 having a width that is defined by D1 the width of the channel for P-type device) is greater than a second width of a topmost portion of the second source/drain recess (Fig. 13, drain region 406 having a width that is defined by D2 the width of the channel for N-type device. Also, [0024], the source/drain regions of the P-type device is greater than the source/drain regions of the N-type device.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang to have a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess as modified by Xiao for the purpose of reducing short channel effects, improve the integration level of device, and improve the power of the device. (Xiao, [0075])
Chiang and Xiao appears to be silent on “performing an ion implantation into a memory device region or a logic device region to modify an etch rate of one of a first source/drain region within the memory device region or a second source/drain region within the logic device region” and, while Chiang does show “wherein a first depth of the first source/drain feature is different than a second depth of the second source/drain feature,” Chiang appears silent as to reason why the first depth of the first source/drain feature would be different than the second depth of the second source drain feature.
Murthy, which teaches increasing the effect gate length through deposition of a gate control layer, discloses:
performing an ion implantation process into a memory device region or a logic device region to modify an etch rate of one of a first source/drain region within the memory device region or a second source/drain region within the logic device region (Murthy, paragraph [0021], “The dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process.” Therefore, by implanting ions into the first region of the first device the etch rate of the material is increased based on the choice of dopants.); and
wherein a first depth of the first source/drain feature is different than a second depth of the second source/drain feature.(The result of etching both a region that has had the implantation process and region where the process has not been performed would result in the depth of the first source/drain region being greater and therefore different from the second source/drain region. )
Murthy thus establishes that it is known in the art that that ion implantation can be controlled to achieve a specific etch rate. Furthermore, to the Examiner’s understanding, there is no evidence of criticality in the specification for a specific etch rate of a first source/drain region of the first device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Murthy reference to achieve a specific etch rate, as it has been held obvious the ion implantation process done to a specific region leads to a related change in the etch rate of the region.
Regarding Claim 12:
Murthy further discloses:
The method of claim 10, wherein the ion implantation process is performed into the logic device region, and wherein the etch rate of the second source/drain region is increased. (Murthy, paragraph [0021] The dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process.)
Regarding Claim 13:
The method of claim 10, wherein the first depth of the first source/drain feature (Chiang, Fig. 1,source/drain epitaxial layer 40 and contact layer 60 in Q2) is less than the second depth of the second source/drain feature. (Chiang, Fig. 1, source/drain epitaxial layer 40 and contact layer in Q1. The source/drain epitaxial layer 40 of device Q2 has a smaller depth than the source/drain epitaxial layer 40 of device Q1.)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao, and Murthy as applied to claim 10 above, and further in view of Du.
Regarding claim 11, Chiang, Xiao, and Murthy teach the elements of claim 10 as recited above.
Chiang further discloses:
wherein the ion implantation process is performed into the memory device region (Fig. 2, shows the ion implantation process for the FET devices, Fig. 29A shows the use of these transistors being used a SRAM cell therefore the ion implantation would initially be done in the memory device region.)
The combination of Chiang, Xiao, and Murthy do not appear to disclose “wherein the etch rate of the first source/drain region is decreased”.
Du, which teaches processing of Fin-type field effect transistors improving etch selectivity of material layers in the fin-type structure, discloses:
wherein the ion implantation process is performed into the memory device region, and wherein the etch rate of the first source/drain region is decreased. ( Du, paragraph [0043] the ion implantation in the shallow trench isolation 103 may reduce the etch rate to the shallow trench isolation 103 during the subsequent etching to remove a portion of the isolation material layer 1030 in the regions between adjacent fins of the fin-type structure 1001, thereby reducing the loss of the shallow trench isolation 103 in that process and paragraph [0044] the ion implantation uses vertical injection. That is, the injecting direction is substantially perpendicular to the upper surface of the semiconductor substrate 100.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang, as modified by Xiao and Murthy to have the wherein the etch rate of the first source/drain region is decrease as modified by Du for purposes of reducing the etch rate in the area where larger width of an opening to recess compared to the area with the smaller opening of the recess. See Du paragraph [0054]. Therefor this is solving the same problem of reducing the etch rate in a region even though Du’s process is being done in an STI region instead of a memory region.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao, and Murthy as applied to claim 10 above, and further in view of Iguchi.
Regarding claim 14, Chiang, Xiao, and Murthy disclose all the elements of claim 10 as recited above.
Chiang, Xiao, and Murthy appear to be silent regarding “the ion implantation process includes performing a plurality of ion implantation processes at different implant angles.”
Iguchi, which teaches a MOS transistor where the channel region is level with the source/drain region and can be under sidewall spacers (Iguchi, Abstract), discloses:
the ion implantation process includes performing a plurality of ion implantation processes at different implant angles (Iguchi, Fig. 4(l), col. 15, lines 51-56.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang as modified by Xiao and Murthy to have the ion implantation process includes performing a plurality of ion implantation processes at different implant angles as modified by Iguchi for the purpose of implanting dopant ions underneath sidewall region. (Iguchi, Fig. 4(l), col. 15, lines 57-65)
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao and Murthy as applied to claim 10 above, and further in view of Chang et al. US 20170351802 (hereinafter Chang).
Regarding claim 15, Chiang, Xiao, and Murthy teach the elements of claim 10 as recited above.
The combination of Chiang. Xiao, and Murthy do not appear to disclose "wherein the first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device".
Chang, which teaches a method of fabricating an integrated circuit, discloses:
wherein the first memory device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device (Chang, Fig. 3, Core Logic Device 330, paragraph [0026], "PMOS transistors 331, 333, 335, 337 of the core logic devices 330" and "the NMOS transistors 332, 334, 336, 338 of the core logic devices 330".), and wherein the first logic device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device. (Chang, Fig. 3, SRAM Block 310, paragraph [0025[, "The SRAM block 310 includes PMOS pull-up transistors 312, NMOS pull-down transistors 314, and NMOS access transistors 316. Similarly, the SRAM block 320 includes PMOS pull-up transistors 322, NMOS pull-down transistors 324, and NMOS access transistors 326.")
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang, Xiao, and Murthy to have first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device as modified by Chang for purposes of allowing decoupling of the threshold voltage of a transistor (e.g., a SRAM transistor) from the threshold voltage of a SVT transistor, thereby allowing adjustment of the threshold voltage or driving current of the decoupled transistor independently from the SVT transistor. See Chang paragraph [0010].
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao, Murthy, Meiser et al.US 20170301791 (hereinafter Meiser), and Chang.
Regarding claim 21, Chiang discloses:
A method (Chiang, paragraph [0051], "FIGS. 2-21D show various stages of manufacturing a semiconductor FET device according to an embodiment of the present disclosure."), comprising:
after modifying the etch rate of the source/drain regions (Chiang, Fig.2 of the ion implantation process is done prior to other processing steps including is prior to subsequent photolithography and etch steps described below.), etching (Chiang, Figs. 12A-12D, paragraph [0079], "The structures of FIGS. 12A-12D can be formed by one or more lithography and etching operations."), …, to simultaneously form a first source/drain recess for a first device in the first device region and a second source/drain recess (Chiang, Fig. 12A-12D, S/D space 22 in Q1) for a second device in a second device region (Chiang, Fig. 12A-12D, S/D space 22 in Q2) different than the first device region (Chiang discusses that this can be done in at least lithography and etch operation therefore the first and second source/drain recess can be done in simultaneously.) wherein the first source/drain recess is formed adjacent to a first gate structure extending in a first direction in a top-down view (Chiang discloses in Fig. 12C shows that the source/drain recess 22 is adjacent to the gate structure 38 and would extend in first direction such as in the X-direction.), and wherein the second source/drain recess is formed adjacent to a second gate structure extending in the first direction in the top-down view; (Chiang discloses in Fig. 12D, shows that the source/drain space 22 adjacent to the gate structure 38 and would extend in first direction such as in the X-direction.);
…and
wherein the first width (Chiang would by necessity have a first width of the source/drain of the device of Fig. 12C.) and the second width (Chiang would by necessity have a second width of the source/drain of the device of Fig. 12D.) are defined along a second direction in the top-down view (The device of 12C and 12D would by necessity have a width that in the y-direction that goes into and out of the paper that would be defined by the channel width in the y-direction as well.), the second direction perpendicular to the first direction. (The y-direction is perpendicular to the x-direction.)
Chiang appears to be silent on:
modifying an etch rate of source/drain regions, through a first patterned mask layer defined using a first-grade photomask, of each of an N-type logic device and a P-type logic device in a first device region of a substrate;
…., through a second patterned mask layer defined using a second grade photomask different than the first grade photomask, … ;
wherein a first depth of the first source/drain recess is different than a second depth of the second source/drain recess.
Furthermore, Chiang does not appear to disclose “a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess”.
However, Xiao, which teaches CMOS FinFETs (Xiao, [0004]) which have one the source/drain region widths being defined by the channel length ([0011]), discloses:
a first width of a topmost portion of the first source/drain recess (Fig. 13, drain region 306 having a width that is defined by D1 the width of the channel for P-type device) is greater than a second width of a topmost portion of the second source/drain recess (Fig. 13, drain region 406 having a width that is defined by D2 the width of the channel for N-type device. Also, [0024], the source/drain regions of the P-type device is greater than the source/drain regions of the N-type device.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang to have a first width of a topmost portion of the first source/drain recess is greater than a second width of a topmost portion of the second source/drain recess as modified by Xiao for the purpose of reducing short channel effects, improve the integration level of device, and improve the power of the device. (Xiao, [0075])
However, Murthy, which teaches increasing the effect gate length through deposition of a gate control layer, discloses:
modifying an etch rate of source/drain regions (Murthy, paragraph [0021], “the dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process.” Therefore, the etch rate can be modified by ion implantation. ),...;
wherein a first depth of the first source/drain recess is different than a second depth of the second source/drain recess. (The result of etching both a region that has had the implantation process and region where the process has not been performed would result in the depth of the first source/drain region being greater region has a higher etch rate. This is because as Murthy, paragraph [0021], “The dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang and Xiao to have modifying an etch rate of the source/drain regions resulting in the first depth of the first source/drain recess being different than the second depth of the second source/drain recess as modified by Murthy because Murthy teaches that ion implantation can be controlled to achieve a specific etch rate. Murthy thus establishes that it is known in the art that that ion implantation can be controlled to achieve a specific etch rate. Furthermore, to the Examiner’s understanding, there is no evidence of criticality in the specification for a specific etch rate of a first source/drain region of the first device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Murthy reference to achieve a specific etch rate, as it has been held obvious the ion implantation process done to a specific region leads to a related change in the etch rate of the region.
Chiang, Xiao, and Murthy appears to be silent on:
through a first patterned mask layer defined using a first-grade photomask, of each of an N-type logic device and a P-type logic device in a first device region of a substrate;
…., through a second patterned mask layer defined using a second grade photomask different than the first grade photomask, … ;
However, Meiser which teaches forming an integrated circuit, discloses:
through a first patterned mask layer defined using a first grade photomask (Meiser, paragraph [0034] and [0038], " the distance between adjacent trenches that corresponds to the width d1 of the body regions may be larger than 100 nm, for example more than 130 nm, e.g. even more than 200, 300, 400 or 500 nm." and "[T]his may be accomplished by forming a hard mask layer (stack) over the semiconductor substrate or workpiece and by photolithographically patterning the hard mask layer (stack)." , Therefor a person a person of ordinary skill in the art would pick a first photo mask to match the resolution for the device that they seek.),
through a second patterned mask layer defined using a second grade photomask different than the first grade photomask (Meiser, paragraph [0034] and [0038], " [T]he width of the body region 220 may be approximately 20 to 130 nm, e.g. 40 to 120 nm along the second direction and parallel to the first main surface 110 of the semiconductor substrate 100.." and "[T]his may be accomplished by forming a hard mask layer (stack) over the semiconductor substrate or workpiece and by photolithographically patterning the hard mask layer (stack)." , Therefor a person a person of ordinary skill in the art would pick a second photo mask to match the resolution for the device that they seek.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang as modified by Xiao and Murthy to have a first patterned mask and second patterned defined by respective first grade and second grade photomask as modified by Meiser for purposes of defining the body regions having difference resolutions on the device. See Meiser paragraph [0034].
The combination of Chiang, Xiao, Murthy, and Meiser do not appear to disclose "of each of an N-type logic device and a P-type logic device in a first device region of a substrate".
Chang, which teaches a method of fabricating an integrated circuit, discloses:
of each of an N-type logic device and a P-type logic device in a first device region of a substrate (Chang, Fig. 3, Core Logic Device 330, paragraph [0026], "PMOS transistors 331, 333, 335, 337 of the core logic devices 330" and "the NMOS transistors 332, 334, 336, 338 of the core logic devices 330");
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang as modified by Xiao and Murthy to have e first device includes an N-type system-on-a-chip (SOC) logic device or a P-type SOC logic device, and wherein the second device includes an N-type static random-access memory (SRAM) device or a P-type SRAM device as modified by Chang for purposes of allowing decoupling of the threshold voltage of a transistor (e.g., a SRAM transistor) from the threshold voltage of a SVT transistor, thereby allowing adjustment of the threshold voltage or driving current of the decoupled transistor independently from the SVT transistor. See Chang paragraph [0010].
Regarding claim 22, Chiang, Xiao, Murthy, Meiser, and Chang teach the elements of claim 21 as recited above.
Murthy further discloses:
wherein the modifying the etch rate includes performing an ion implantation process into the first device region. (Murthy et al. US 20160240534, paragraph [0021] The dopant used in the ion implantation process can be chosen, for example, based on its ability to increase the etch rate of the substrate material in which it is implanted, and the specific dopant selected for the ion implantation process may vary based on the substrate material(s) and the etchant used in a subsequent etching process. Therefore, the etch rate can be modified by ion implantation where the modification increases the etch rate. )
Regarding claim 23, Chiang, Xiao Murthy, Meiser, and Chang teach the elements of claim 21 as recited above.
Meiser further discloses:
wherein the first-grade photomask includes a low- grade photomask. (Meiser, paragraph [0034] and [0038], " the distance between adjacent trenches that corresponds to the width d1 of the body regions may be larger than 100 nm, for example more than 130 nm, e.g. even more than 200, 300, 400 or 500 nm." and "[T]his may be accomplished by forming a hard mask layer (stack) over the semiconductor substrate or workpiece and by photolithographically patterning the hard mask layer (stack)." , Therefor a person a person of ordinary skill in the art would pick a first photo mask to match the resolution for the device that they seek.)
Regarding claim 24, Chiang, Xiao, Murthy, Meiser, and Chang teach the elements of claim 21 as recited above.
Meiser further discloses:
wherein the second grade photomask includes a high-grade photomask. (Meiser, paragraph [0034] and [0038], " [T]he width of the body region 220 may be approximately 20 to 130 nm, e.g. 40 to 120 nm along the second direction and parallel to the first main surface 110 of the semiconductor substrate 100.." and "[T]his may be accomplished by forming a hard mask layer (stack) over the semiconductor substrate or workpiece and by photolithographically patterning the hard mask layer (stack)." , Therefor a person a person of ordinary skill in the art would pick a second photo mask to match the resolution for the device that they seek.)
Regarding claim 25, Chiang, Xiao, Murthy, Meiser, and Chang teach the elements of claim 21 as recited above.
Chiang further discloses:
wherein the first depth is greater than the second depth. (Chiang, Fig. 1, The etch depth of S/D space in Q1 is greater than the etch depth of the S/D space in Q2.)
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang, Xiao and Murthy as applied to claims 10 above, and further in view of Liaw.
Regarding Claim 26, Chiang, Xiao, and Murthy disclose all the elements of claim 10.
Chiang further teaches:
The method of claim 10, wherein the first source/drain feature (Chiang, Fig. 1, source/drain epitaxial layer 40in Q1 and contact layer 60) is formed over a first fin, (Chiang, Fig. 1, the contact layer 60 extends above the top layer semiconductor wire 25 in Q1),
Chiang, Xiao, and Murthy do not appear to disclose:
wherein the first source/drain feature merges with a third source/drain feature formed over a second fin adjacent to the first fin.
Liaw, which teaches a fin structure with a source/drain region (Liaw, Abstract), disclose:
wherein the first source/drain feature (annotated Fig. 4B, S/D1) merges with a third source/drain feature (S/D3) formed over a second fin (F2) adjacent to the first fin (F1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chiang as modified by Xiao and Murthy to have the first source/drain feature merges with a third source/drain feature formed over a second fin adjacent to the first fin as further modified by Liaw for the purpose of tying together multiple fins in a multi-fin N-type or P-type FinFET well region. (Liaw, [0040]-[0041].)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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