DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sidhu et al. (PG Pub. No. US 2014/0319682 A1) in view of Hong et al. (PG Pub. No. US 2012/0193783 A1) and Bachman et al. (PG Pub. No. US 2011/0163441 A1).
Regarding claim 16, Sidhu teaches a method comprising:
placing a first set of connectors on a first package (¶ 0059: 314 placed on package assembly 300), the first package comprising an embedded die (¶ 0023 & fig. 3A: 300 comprises embedded die 102);
reflowing the first set of connectors at a reflow temperature to attach the first set of connectors to a connector surface of the first package (¶¶ 0060, 0065 & fig. 3D: 314 reflowed to at least a peak reflow temperature to attach 314 to connector surface of 300), each connector of the first set of connectors including a spacer embedded therein (¶ 0059 & fig. 3C: each 314 includes embedded core 120), each spacer comprising a solid core (¶ 0045: solid core 120), a barrier layer surrounding the solid core (¶¶ 0034, 0051: 120 surrounded by structural barrier 116a), and a solder material layer (¶¶ 0030, 0059: 116b/118) surrounding the barrier layer (fig. 3C among others: 118/116b at least partially surrounds 116a), the solder material layer including an undoped central region (¶¶ 0032-0033: 116b/118 absent dopant, and therefore includes an undoped central region);
reflowing the first set of connectors at a reflow temperature (¶ 0060: second reflow process) to attach the first set of connectors to a connector surface of a substrate (fig. 3E: 314 attached to pad surface 117 of board 122); and
cooling the first package (implicit: in order for the reflowed solder to solidify, package 300 must be cooled below the reflow temperature).
Sidhu does not teach the first set of connectors further comprises a second barrier layer surrounding the conductive layer, and the solder material layer surrounding the second barrier layer, the solder material layer including a doped sublayer at its outer periphery, or that wherein after the first set of connectors are attached to the substrate, the first package has a warped connector surface.
However, Sidhu does teach at least one embodiment wherein first connectors (¶ 0048: 114, corresponding to 314 of figs. 3A-3E) are reflowed and attached to pads of a warped package substrate (¶ 0048: 114 reflowed on pads 110 of substrate 104), wherein the package substrate remains warped (implicit: Sidhu does not disclose any change to the warpage property of the package substrate).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Sidhu with a warped connector surface, as a means to improve manufacturing efficiency and reduce costs by utilizing components with non-planar surfaces.
Sidhu as modified above does not teach the first set of connectors further comprises a second barrier layer surrounding the conductive layer, and the solder material layer surrounding the second barrier layer, the solder material layer including a doped sublayer at its outer periphery.
Hong teaches package connectors (¶ 0049 & figs. 2-3: connection members 140, similar to 314 of Sidhu) including a core (¶ 0054: 141, similar to 120 of Sidhu), a first barrier layer (¶ 0056: nickel layer 142) surrounding the core (fig. 3: 142 surrounds 141), a conductive layer (¶ 0056: copper layer 143) surrounding the first barrier layer (fig. 3: 143 surrounds 142), and a solder material layer (¶ 0057: 144, similar to 116 and/or 118 of Sidhu) surrounding the conductive layer (fig. 3: 144 surrounds 143). Hong further teaches an embodiment (¶¶ 0097-0099 & fig. 10) wherein an adhesive layer (532, similar to 142 and 143 of fig. 3) includes more than two layers (¶ 0099: 532 may be formed in a multilayer structure having two or more layers), wherein the layers include barrier material (¶ 0099: nickel).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first connectors of Sidhu with the structure of Hong, as a means to improve yield and package minimization (Hong, ¶ 0054). Furthermore, it would have been obvious configure the connectors of Sidhu in view of Hong to further comprise a second barrier layer surrounding the conductive layer, as a means to prevent heat from being transferred to the core when the conductive layer is melted (Hong, ¶ 0099).
Sidhu in view of Hong does not teach the solder material layer including a doped sublayer at its outer periphery.
Bachman teaches a set of solder connectors (¶ 0042: 140) on a package (fig. 3 among others: 140 disposed on package substrate 120), the connectors dopant at its outer periphery (¶ 0036: 140 includes dopant in at least the outer periphery region).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the solder material layer of Sidhu in view of Hong with a doped periphery, as a means to reduce a solidification undercooling temperature (Bachman, ¶ 0004), enhancing crystalline properties and mechanical properties of the solder (Bachman, ¶ 0018).
Regarding claim 20, Sidhu in view of Hong and Bachman teaches the method of claim 16, further comprising:
placing a second set of connectors (Sidhu, ¶ 0058: balls 312) on the first package (Sidhu, fig. 3B: 312 placed on 300) and reflowing the second set of connectors to attach the second set of connectors to the connector surface of the first package (Sidhu, ¶ 0060 & fig. 3D: 312 reflowed to attach to connector surface of 300), wherein each of the second set of connectors is free from the spacer (Sidhu, figs. 3B-3D: 312 free of spacer 120).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sidhu in view of Hong and Bachman as applied to claim 16 above, and further in view of Yasuda et al. (PG Pub. No. US 2002/0100610 A1).
Regarding claim 17, Sidhu in view of Hong and Bachman teaches the method of claim 16, further comprising:
attaching the first set of connectors to a substrate (Sidhu, ¶ 0061 & fig. 3E: 114 attached to board 122).
Sidhu in view of Hong and Bachman does not teach wherein every connector attached to both the first package and the substrate is a connector in the first set of connectors, each connector of the first set of connectors including a spacer embedded therein.
Yasuda teaches attaching a first set of connectors (¶ 0078: composite connection materials 9 each formed of a core 1 and a conductor 2 covering core 1, similar to 114/314 of Sidhu) to a substrate (¶ 0079: 6, similar to 122 of Sidhu), wherein every connector attached to both a first package (¶ 0079: 5, similar to 300 of Sidhu) and the substrate is a connector in the first set of connectors (¶ 0097 & fig. 9: all connection materials constituting external electrodes are composite connection materials 9).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure every connector of Sidhu in view of Hong and Bachman with a spacer embedded therein, as a means to provide accurate positional matching between a semiconductor device and a substrate 6 by a self-alignment function (Yasuda, ¶ 0097).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sidhu in view of Hong and Bachman as applied to claim 16 above, and further in view of Cheng et al. (PG Pub. No. US 2017/0136582 A1).
Regarding claim 18, Sidhu in view of Hong and Bachman teaches the method of claim 16, further comprising:
attaching a first connector (Sidhu, 314) of the first set of connectors to a first contact pad of the first package (Sidhu, ¶ 0050 & fig. 1: 314 attached to pad 110 of 104) and a second contact pad of a substrate (Sidhu, ¶ 0050 & fig. 1: 314 attached to pad 117 of substrate 122), wherein a first spacer of the first connector contacts both the first contact pad and the second contact pad (Sidhu, fig. 1: 120 at least electrically contacts both 110 and 117); and
attaching a second connector of the first set of connectors to a third contact pad of the first package and a fourth contact pad of the substrate (Sidhu, fig. 1: second 314 attached to additional pad 110 of 104 and additional pad 117 of 122), the first spacer of the first connector and a second spacer of the second connector being the same size (Sidhu, fig. 1: 120 of first and second 314 have a same size).
Sidhu in view of Hong and Bachman further teaches the spacers of the first and second connectors include materials such as metal and polymer (Sidhu, ¶ 0046), and may comprise spherical or other shapes (Sidhu, ¶ 0046).
Sidhu in view of Hong and Bachman does not teach wherein the second spacer of the second connector contacts neither the third contact pad nor the fourth contact pad.
Cheng teaches a method including attaching connectors (¶ 0017: 140, similar to 314 of Sidhu) of to a first and third contact pads (¶ 0018: 111) of a first substrate and a second and fourth contact pads of a second substrate (¶ 0017 & fig. 1: 140 attached to pads 111 of substrates 110 and 120). Cheng further teaches the connectors include spacers (¶ 0022: spherical metal core 141, similar to 120 of Sidhu), and at least some of the spacers are not physically connected to contact pads of the first and second substrates (fig. 1: metal cores electrically connected to pads 111, but physically disconnected from pads 111).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Sidhu in view of Hong and Bachman to include at least some connectors to be physically disconnected from the package and substrate pads, as a means to provide a barrier layer (Cheng, ¶ 0022: 142) to encapsulate the core (Cheng, fig. 1), preventing the core from over-deforming during reflow process (Cheng, ¶ 0025).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sidhu in view of Hong and Bachman as applied to claim 16 above, and further in view of Martin et al. (PG Pub. No. US 2003/0146505 A1).
Regarding claim 19, Sidhu in view of Hong and Bachman teaches the method of claim 16, comprising two connectors of the first set of connectors disposed on a package and/or a substrate (fig. 3E: at least two connectors 314 disposed on surfaces of 104 and 122).
Sidhu in view of Hong and Bachman does not teach the method further comprising:
attaching a surface mount device between the two connectors of the first set of connectors.
Martin teaches a method of forming semiconductor package (¶ 0014 & fig. 1: 10) including two connectors (¶ 0018: 20, similar to 314 of Sidhu), each connector including a spacer embedded therein (¶ 0018: 20 includes core 32, similar to 120 of Sidhu), the connectors disposed on a package and/or a substrate (¶¶ 0016, 0023 & fig. 1: 20 disposed on surfaces of 22 and 44, corresponding to 104 and 122 of Sidhu), the method comprising:
attaching a surface mount device (¶ 0027: 52) between two connectors of the first set of connectors (fig. 1: 52 attached to 22 between two connectors 20).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Sidhu in view of Hong and Bachman with the surface mount device of Martin, as a means to increase the functionality of the package by including a capacitive function to the integrated circuit of Sidhu.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02.
Allowable Subject Matter
Claims 1-15 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations stating:
“each first connector having embedded therein a spacer, wherein the spacer includes an inter portion comprising a core, a first barrier layer surrounding the core, and a conductive layer surrounding the first barrier layer, and wherein the spacer further includes an outer portion comprising a eutectic solder material layer surrounding the conductive layer, the eutectic solder material including an undoped central portion and a doped portion surrounding the central portion” as recited in claim1, and
“the first connectors comprising a spacer embedded in a first solder, a first barrier layer surrounding the spacer, a conductive layer surrounding the first barrier layer, and a eutectic solder material layer surrounding the conductive layer, the eutectic solder material layer including an undoped central region and a doped sublayer surrounding the undoped central region” as recited in claim 8.
The cited prior art teaches connectors including a spacer, a barrier layer and inner/outer solder surrounding the barrier layer. However, none of the cited references, either alone or in combination, teach the solder comprising eutectic material.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 5/30/2025 regarding the 35 USC § 103 rejections of claims 1-15 have been fully considered and are persuasive. Accordingly, the 35 USC § 103 rejections of claims 1-15 have been withdrawn.
Applicant's arguments with respect to claims 16-20 have been fully considered but they are not persuasive.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In particular, the examiner notes that Bachman is not relied upon to teach the feature of a solder layer having both an undoped central portion. Accordingly, the argument is not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN TURNER/Examiner, Art Unit 2818