DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1 and 3-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-9, 11-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210202323 A1) in view of Zhang et al. (US 20200279777 A1) and Rachmady et al. (US 20200294969 A1).
Re Claim 1 Wu teaches an integrated circuit (IC) chip, comprising:
a first gate-all-around (GAA) device (206a) [0017] comprising:
a first set of silicon dioxide structures (252a) [0031] around a first set of silicon channels (220) [0021], wherein adjacent silicon channels (220) in the first set of silicon channels (220 in 206a) are spaced apart by a first distance (distance between 220 parts in 206a, FIG. 18), and wherein each silicon dioxide structure in the first set of silicon dioxide structures (252a) has a first thickness,
a first set of hafnium dioxide structures (254a) [0036] around the first set of silicon dioxide structures (252a), wherein each hafnium dioxide structure (254a) has a second thickness, and
a first metal structure (282) [0036] around the first set of hafnium dioxide structures (254a) (FIG. 18); and
a second GAA device (206c) [0017] comprising:
a second set of silicon dioxide structures (252c) [0042] around a second set of silicon channels (220) [0021], and wherein adjacent silicon channels (220) in the second set of silicon channels (220 in 206c) are spaced apart by the first distance (220 in 206a and 206c have same spacing between 220 parts, FIG. 18), wherein each silicon dioxide structure in the second set of silicon dioxide structures (252c) has a third thickness, and
a second metal structure (282 in 204 region) around and in contact with the second set of silicon dioxide structures (252c, FIG. 18).
Wu does not teach the third thickness is substantially equal to a sum of the first thickness and the second thickness.
Zhang (FIG. 9) teaches a first thickness (thickness of SiO2 layer 902, [0047] states, “…IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm.” Use 1 nm for first thickness), a second thickness (thickness of HfO2 layer 904, [0048] states, “…904/908 are each deposited to a thickness of from about 2 nm to about 10 nm…” Use 2.5 nm for second thickness), and a third thickness (thickness of SiO2 layer 906, [0047] states, “IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. At this point in the process, IL oxide 902 (logic device) and IL oxide 906 (I/O device) generally have the same thickness. However, steps will be taken later in the process to selectively increase the thickness of the IL oxide in the I/O device.” Use 3.5 nm for third thickness) Therefore, the third thickness (thickness of 906, 3.5 nm) is substantially equal to a sum of the first thickness (thickness of 902, 1 nm) and the second thickness (thickness of 904, 2.5 nm, FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhang into the structure of Wu since Zhang is about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Zhang in combination with Wu in the above manner for the motivation of forming the third thickness to be equal to the first and second thickness combined to create a device that functions at a peak level and helps meet the requirements of aggressive device scaling. [0002] states, “Gate-all-around (GAA) field-effect transistors (FETs) like nanosheet-based devices provide better electro-static control. Thus, a GAA device architecture helps meet the requirements for further aggressive device scaling.”
Wu in view of Zhang does not teach the second metal structure in physical contact with the second set of silicon dioxide structures.
Rachmady teaches the second metal structure (124-2) [0027] in physical contact with the second set of silicon dioxide structures (122 in 124-2, [0026], FIG. 17A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Rachmady into the structure of Wu in view of Zhang since Rachmady is about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Rachmady in combination with Wu in view of Zhang in the above manner for the motivation of arranging the silicon dioxide and the gate in relation to the channel region to help optimize the current and impedance in the semiconductor device. [0027] states, “Together, the gate metal 124 and the gate dielectric 122 may provide a gate for the associated channel material 106, with the electrical impedance of the channel material 106 modulated by the electrical potential applied to the associated gate.”
Re Claim 3 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the first thickness (Zhang, thickness of 902, FIG. 9) is about 1 nm ([0047] states, “…902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm.”).
Re Claim 4 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1,but does not explicitly teach the second thickness is about 2.5 nm.
Zhang teaches the second thickness is between 2 nm and 10 nm (thickness of HfO2 layer 904, [0048] states, “…904/908 are each deposited to a thickness of from about 2 nm to about 10 nm…” Use 2.5 nm for second thickness).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhang into the structure of Wu in view of Zhang and Rachmady.
The ordinary artisan would have been motivated to modify Zhang in combination with Wu in view of Zhang and Rachmady in the above manner for the motivation of finding optimal thickness for the second thickness. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal thickness values.
Re Claim 6 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the second GAA device drives an output pin of the IC chip (Wu [0042] states, “ . . . the third GAA device is an input/output (I/O) device of the integrated circuit.” (Using the third GAA device is the same concept as using the second GAA device).
Re Claim 7 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the second GAA device (Wu, 24, [0013] “third GAA device”) receives an input signal from a source which is external to the IC chip (FIG. 1B).
The limitation “…wherein the second GAA device receives an input signal from a source which is external to the IC chip.” is merely functional/intended use limitation that do structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114.
Re Claim 8 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein a second operating voltage range of the second GAA device is greater than a first operating voltage range of the first GAA device (Wu, FIG. 1B, [0012] states, “Operating voltage for the I/O area may be similar to external voltage (voltage level of the external/peripheral circuitry) and is higher than the operating voltage of the core area.”).
Re Claim 9 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the first metal structure and the second metal structure are made of titanium nitride (Wu, [0039]).
Re Claim 11 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the first metal structure and the second metal structure are made of tantalum (Wu, [0039]).
Re Claim 12 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, wherein the first metal structure and the second metal structure are made of tungsten (Wu, [0039]).
Re Claim 14 Wu teaches an integrated circuit (IC) manufactured using gate-all-around (GAA) process technology, the IC comprising:
a first GAA transistor (206a, FIG. 18) [0017], comprising:
a first set of channels (220) made of a semiconductor material [0021], wherein adjacent channels (220) in the first set of channels (220 in 206a) are spaced apart by a first distance (distance between 220 parts in 206a, FIG. 18),
a first set of silicon dioxide structures (252a) [0031] around the set of channels (220), wherein each silicon dioxide structure (252a) in the first set of silicon dioxide structures has a first thickness,
a first set of hafnium dioxide structures (254a) [0036] around the first set of silicon dioxide structures (252a), wherein each hafnium dioxide structure has a second thickness, and
a first metal structure (282 in 202 region, FIG. 18) around the first set of hafnium dioxide structures (254a); and
a second GAA transistor (206c) [0017], comprising:
a second set of channels (220, FIG. 18) made of the semiconductor material [0021], wherein adjacent channels (220) in the second set of channels (220 in 206c) are spaced apart by the first distance (220 in 206a and 206c have same spacing between 220 parts, FIG. 18),
a second set of silicon dioxide structures (252c) [0043] around the second set of channels (220 in 204 region), wherein each silicon dioxide structure (252c) in the second set of silicon dioxide structures has a third thickness, and
a second metal structure (282) around and in contact with the second set of silicon dioxide structures (252c, FIG. 18).
The limitations “…wherein a current flowing through the first set of channels is controlled by a first voltage which is applied to the first metal structure…” and “…wherein a current flowing through the second set of channels is controlled by a second voltage which is applied to the second metal structure.” are merely functional/intended use limitation that do structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114.
Wu does not teach the third thickness is substantially equal to a sum of the first thickness and the second thickness.
Zhang teaches a first thickness (thickness of SiO2 layer 902, [0047] states, “…IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm.” Use 1 nm for first thickness), a second thickness (thickness of HfO2 layer 904, [0048] states, “…904/908 are each deposited to a thickness of from about 2 nm to about 10 nm…” Use 2.5 nm for second thickness), and a third thickness (thickness of SiO2 layer 906, [0047] states, “IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. At this point in the process, IL oxide 902 (logic device) and IL oxide 906 (I/O device) generally have the same thickness. However, steps will be taken later in the process to selectively increase the thickness of the IL oxide in the I/O device.” Use 3.5 nm for third thickness) Therefore, the third thickness (thickness of 906, 3.5 nm) is substantially equal to a sum of the first thickness (thickness of 902, 1 nm) and the second thickness (thickness of 904, 2.5 nm, FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhang into the structure of Wu since Zhang is about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Zhang in combination with Wu in the above manner for the motivation of forming the third thickness to be equal to the first and second thickness combined to create a device that functions at a peak level and helps meet the requirements of aggressive device scaling. [0002] states, “Gate-all-around (GAA) field-effect transistors (FETs) like nanosheet-based devices provide better electro-static control. Thus, a GAA device architecture helps meet the requirements for further aggressive device scaling.”
Wu in view of Zhang does not teach the second metal structure in physical contact with the second set of silicon dioxide structures.
Rachmady teaches the second metal structure (124-2) [0027] in physical contact with the second set of silicon dioxide structures (122 in 124-2, [0026], FIG. 17A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Rachmady into the structure of Wu in view of Zhang since Rachmady is about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Rachmady in combination with Wu in view of Zhang in the above manner for the motivation of arranging the silicon dioxide and the gate in relation to the channel region to help optimize the current and impedance in the semiconductor device. [0027] states, “Together, the gate metal 124 and the gate dielectric 122 may provide a gate for the associated channel material 106, with the electrical impedance of the channel material 106 modulated by the electrical potential applied to the associated gate.”
Re Claim 15 Wu in view of Zhang and Rachmady teaches the IC of claim 14, wherein a second operating voltage range of the second GAA transistor is greater than a first operating voltage range of the first GAA transistor (Wu, FIG. 1B, [0012] states, “Operating voltage for the I/O area may be similar to external voltage (voltage level of the external/peripheral circuitry) and is higher than the operating voltage of the core area.”).
Re Claim 16 Wu in view of Zhang and Rachmady teaches the IC of claim 14, wherein the first thickness is about1 nm (Zhang, thickness of SiO2 layer 902, [0047] states, “…IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm.”).
Wu in view of Zhang and Rachmady does not explicitly teach the second thickness is about 2.5 nm.
Zhang teaches the second thickness is between 2 nm and 10 nm (thickness of HfO2 layer 904, [0048] states, “…904/908 are each deposited to a thickness of from about 2 nm to about 10 nm…” Use 2.5 nm for second thickness).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhang into the structure of Wu in view of Zhang and Rachmady.
The ordinary artisan would have been motivated to modify Zhang in combination with Wu in view of Zhang and Rachmady in the above manner for the motivation of finding optimal thickness for the second thickness. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal thickness values.
Re Claim 17 Wu in view of Zhang and Rachmady teaches the IC of claim 14, wherein the first metal structure and the second metal structure are made of a material selected from a group comprising titanium nitride, titanium aluminum nitride, tantalum, tungsten, and lanthanum (Wu [0039] identifies tungsten as a structure material).
Re claim 18 Wu in view of Zhang and Rachmady teaches the IC of claim 14, wherein the first GAA transistor is in an area of the IC that includes logic circuitry (Wu, FIG. 1A and 1B, [0013] states, “The core area 12 includes logic circuits…”).
Re claim 19 Wu in view of Zhang and Rachmady teaches the IC of claim 14, wherein the second GAA transistor is in an area of the IC that includes input/output (I/O) circuitry (Wu, 14, FIG. 1B).
Re claim 20 Wu teaches a method, comprising:
manufacturing a first gate-all-around (GAA) (206a) [0017] device on a silicon substrate (208) [0019], comprising:
creating a first set of silicon dioxide structures (252a) [0031] around a first set of silicon channels (220) [0018], wherein adjacent silicon channels (220) in the first set of silicon channels (220 in 206a) are spaced apart by a first distance (distance between 220 parts in 206a, FIG. 18), and wherein each silicon dioxide structure (252a) in the first set of silicon dioxide structures has a first thickness,
creating a first set of hafnium dioxide structures (254a) [0036] around the first set of silicon dioxide structures (252a), wherein each hafnium dioxide structure (254a) has a second thickness, and
creating a first metal structure (282 in 202 region) [0039] around the first set of hafnium dioxide structures (254a, FIG. 18); and
manufacturing a second GAA device (206c) [0017] on the silicon substrate (208), comprising:
creating a second set of silicon dioxide structures (252c) [0043] around a second set of silicon channels (220), wherein adjacent silicon channels (220) in the second set of silicon channels (220 in 206c) are spaced apart by the first distance (220 in 206a and 206c have same spacing between 220 parts, FIG. 18), wherein each silicon dioxide structure (252c) in the second set of silicon dioxide structures has a third thickness, and creating a second metal structure (282 in 204 region) around and in contact with the second set of silicon dioxide structures (252c, FIG. 18).
Wu does not teach the third thickness is substantially equal to a sum of the first thickness and the second thickness.
Zhang teaches a first thickness (thickness of SiO2 layer 902, [0047] states, “…IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm.” Use 1 nm for first thickness), a second thickness (thickness of HfO2 layer 904, [0048] states, “…904/908 are each deposited to a thickness of from about 2 nm to about 10 nm…” Use 2.5 nm for second thickness), and a third thickness (thickness of SiO2 layer 906, [0047] states, “IL oxide 902/906 is formed by an oxidation process to a thickness of from about 0.3 nm to about 5 nm, and ranges therebetween, e.g., about 1 nm. At this point in the process, IL oxide 902 (logic device) and IL oxide 906 (I/O device) generally have the same thickness. However, steps will be taken later in the process to selectively increase the thickness of the IL oxide in the I/O device.” Use 3.5 nm for third thickness) Therefore, the third thickness (thickness of 906, 3.5 nm) is substantially equal to a sum of the first thickness (thickness of 902, 1 nm) and the second thickness (thickness of 904, 2.5 nm, FIG. 16).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhang into the structure of Wu since both patents are about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Rachmady in combination with Wu in the above manner for the motivation of forming the third thickness to be equal to the first and second thickness combined to create a device that functions at a peak level and helps meet the requirements of aggressive device scaling. [0002] states, “Gate-all-around (GAA) field-effect transistors (FETs) like nanosheet-based devices provide better electro-static control. Thus, a GAA device architecture helps meet the requirements for further aggressive device scaling.”
Wu in view of Zhang does not teach the second metal structure in physical contact with the second set of silicon dioxide structures.
Rachmady teaches the second metal structure (124-2) [0027] in physical contact with the second set of silicon dioxide structures (122 in 124-2, [0026], FIG. 17A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Rachmady into the structure of Wu in view of Zhang since Rachmady is about Gate-all-around semiconductor devices.
The ordinary artisan would have been motivated to modify Rachmady in combination with Wu in view of Zhang in the above manner for the motivation of arranging the silicon dioxide and the gate in relation to the channel region to help optimize the current and impedance in the semiconductor device. [0027] states, “Together, the gate metal 124 and the gate dielectric 122 may provide a gate for the associated channel material 106, with the electrical impedance of the channel material 106 modulated by the electrical potential applied to the associated gate.”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210202323 A1) in view of Zhang et al. (US 20200279777 A1) and Rachmady et al. (US 20200294969 A1) as applied to claim 1 above, and further in view of Huang et al. (US 20210098456 A1).
Re Claim 5 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, but does not teach wherein the first GAA device implements a logic function.
Huang teaches wherein the first GAA device implements a logic function ([0016] states, “. . . GAA transistor in a core device area to serve logic functions.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Huang into the structure of Wu in view of Zhang and Rachmady since Huang is also a patent about a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Huang in combination with Wu in view of Rachmady in the above manner for the motivation to build and optimally control an IC chip. [0003] states, “IC devices include transistors that serve different functions, such as input/output (I/O) functions and core functions. These different functions require the transistors to have different constructions.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210202323 A1) in view of Zhang et al. (US 20200279777 A1) and Rachmady et al. (US 20200294969 A1) as applied to claim 1 above, and further in view of Song et al. (US 20200395482 A1).
Claim 10 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, but does not teach the first metal structure and the second metal structure are made of titanium aluminum nitride.
Song teaches the first metal structure (120) [0027] and the second metal structure (120, see FIG. 1 fragment below) are made of titanium aluminum nitride. [0030]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Song into the structure of Wu in view of Zhang and Rachmady since Song is also a patent about a gate-all-around semiconductor device.
The ordinary artisan would have been motivated to modify Song in combination with Wu in view of Zhang and Rachmady in the above manner for the motivation to use titanium aluminum nitride to build the first and second metal structures. Using titanium aluminum nitride to form the metal structures offers thermal stability, resistance to diffusion, and hardness.
Song FIG. 1 fragment below shows the 1st and 2nd metal structures.
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20210202323 A1) in view of Zhang et al. (US 20200279777 A1) and Rachmady et al. (US 20200294969 A1) as applied to claim 1 above, and further in view of Xie et al. (US 20200365687 A1).
Re Claim 13 Wu in view of Zhang and Rachmady teaches the IC chip of claim 1, but does not teach the first metal structure and the second metal structure are made of lanthanum.
Xie teaches the first metal structure (1102) [0074] and the second metal structure (1102, see Fig. 11A &11B fragments below) are made of lanthanum. [0075]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xie into the structure of Wu in view of Rachmady since Xie is a semiconductor device feature wrap around gates.
The ordinary artisan would have been motivated to modify Xie in combination with Wu in view of Rachmady in the above manner for the motivation to use lanthanum to build the first and second metal structures. Lanthanum is used in gate semiconductors because it can us used to help fine tune the device’s threshold voltage. [0075] states, “The work function layer can serve to modify the work function of the gates 1102 and enables tuning of the device threshold voltage.”
Xie Fig. 11A &11B fragments below show the 1st and 2nd metal structures.
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Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 20200098643 A1) teaches a gate all around device with hafnium oxide and silicon dioxide layers wrapped around channel structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818
9/21/26
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