DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Prior objection to drawing is withdrawn in view of amendments to claim 21.
Claim Rejections - 35 USC § 112
Prior rejections of Claims 7 and 21-24 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of applicant’s amendments to claims 7 and 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-7 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1, of record).
Re Claim 1, Ju teaches a device (Figs. 27-29), comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 28 below, paras [0049] – [0051]) over a substrate (100, Fig. 27, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 28 below, paras [0050] – [0051]) over the substrate (100);
a first source/drain region (marked “111a-1” in annotated Fig. 29 below, para [0050]) abutting the first vertical stack of nanostructures (“1st stack”, see Figs. 27-29);
a second source/drain region (marked “111b-1” in annotated Fig. 29 below, para [0050]) abutting the second vertical stack of nanostructures (“2nd stack”, see Figs. 27-29);
a first gate structure (115’, marked “1st gate” in annotated Fig. 28 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the first vertical stack (“1st stack”);
a second gate structure (115’, marked “2nd gate” in annotated Fig. 28 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the second vertical stack (“2nd stack”);
a dielectric layer (marked “1122-a” in annotated Fig. 29 below, paras [0044] and [0053]) over the first (“111a-1”) and second source/drain regions (“111b-1”); and
a single, unitary isolation structure (1122-b1 + 103b-1 + 104”-1, marked in annotated Figs. 28 and 29 below, paras [0051] – [0053]) that extends (see Fig. 29) from an upper surface of the dielectric layer (upper surface of “1122-a”) to a level below respective upper surfaces of the first and second source/drain regions (lower surface of “103b-1” is below the upper surface of the S/D regions, see Fig. 29), the isolation structure (1122-b1 + 103b-1 + 104”-1) disposed laterally between (see annotated Fig. 29 below) the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”), and laterally between the first gate structure (“1st gate”) and the second gate structure (“2nd gate”).
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Re Claim 5, Ju teaches the device of claim 1, further comprising:
an isolation region (105’, Figs. 28-29, para [0049]) between the first (“1st stack”) and second vertical stacks (“2nd stack”);
wherein the isolation structure (1122-b1+103b-1+104”-1) lands on the isolation region (105’, see Figs. 28-29).
Re Claim 6, Ju teaches the device of claim 1, further comprising:
a third source/drain region (there will be another set of S/D regions along the cross-section X-X’ shown in annotated Fig. 27 below, symmetric to C1-C1’ in Figs. 27 and 29, marked “111a-2” in annotated Fig. 29-v2 below; paras [0050] – [0053]) abutting the first vertical stack of nanostructures (“1st stack”), the third source/drain region (“111a-2”) being separated from the first source/drain region (“111a-1”) by the first vertical stack (“1st stack”, see annotated Fig. 27 below and annotated Figs. 28-29 above);
a fourth source/drain region (marked “111b-2” in annotated Fig. 29-v2 below) abutting the second vertical stack of nanostructures (“2nd stack”), the fourth source/drain region (“111b-2”) being separated from the second source/drain region (“111b-1”) by the second vertical stack (“2nd stack”, see annotated Fig. 27 below and annotated Figs. 28-29 above); and
a second isolation structure (1122-b2 + 103b-2 + 104”-2, marked in annotated Figs. 28 above and 29-v2 below, paras [0051] – [0053]) that extends from the upper surface of the dielectric layer (upper surface of “1122-a”) to a level below upper surfaces of the third and fourth source/drain regions (see Fig. 29-v2 below), the second isolation structure (1122-b2 + 103b-2 + 104”-2) being between the third source/drain region (“111a-2”) and the fourth source/drain region (“111b-2”), the second isolation structure being separated from the isolation structure (1122-b1 + 103b-1 + 104”-1) by a third gate structure (marked “3rd gate” in annotated Fig. 28 above).
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Re Claim 7, Ju teaches the device of claim 6, wherein the third gate structure (“3rd gate”) includes:
a gate dielectric layer (1142, Figs. 26 and 28, para [0049]) that is in contact with upper surfaces and lower surfaces of spacer portions (1141, Figs. 26 and 28, para [0049]); and
a conductive layer (115, Fig. 28, para [0050]) that is vertically separated (see Fig. 28) from the spacer portions (1141) by the gate dielectric layer (1142).
Re Claim 10, Ju teaches the device of claim 1, further comprising an etch stop layer (1121, see Figs. 19 and 29, para [0044], also see annotated Fig. 29 above) between the dielectric layer (1122-a) and the first (“111a-1”) and second source/drain regions (“111b-1”).
Re Claim 11, Ju teaches the device of claim 10, wherein the isolation structure (1122-b1+103b-1+104”-1) is in contact with the etch stop layer (1121, see Figs. 19 and 29, also see annotated Fig. 29 above), and is separated from the first source/drain region (“111a-1”) by the etch stop layer (the top part of “111a-1” is separated from 103b-1 by the etch stop layer 1121, see Fig. 29).
Re Claim 12, Ju teaches the device of claim 10, wherein the isolation structure (1122-b1+103b-1+104”-1) is in contact with the first source/drain region (111a-1, see Fig. 29), and the etch stop layer (1121) terminates on the isolation structure (see Fig. 29).
Claims 1, 2 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1).
Re Claim 1 (Rejection-2), Ju teaches a device (Figs. 27-29), comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 28-v2 below, paras [0049] – [0051]) over a substrate (100, Fig. 27, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 28-v2 below, paras [0050] – [0051]) over the substrate (100);
a first source/drain region (marked “111b-1” in annotated Fig. 29-v3 below, para [0050]) abutting the first vertical stack of nanostructures (“1st stack”, see Figs. 27-29);
a second source/drain region (marked “111b-2” in annotated Fig. 29-v3 below, para [0050]) abutting the second vertical stack of nanostructures (“2nd stack”, see Figs. 27-29);
a first gate structure (115’, marked “1st gate” in annotated Fig. 28-v2 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the first vertical stack (“1st stack”);
a second gate structure (115’, marked “2nd gate” in annotated Fig. 28-v2 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the second vertical stack (“2nd stack”);
a dielectric layer (marked “1122-b” in annotated Fig. 29-v3 below, paras [0044] and [0053]) over the first (“111b-1”) and second source/drain regions (“111b-2”); and
a single, unitary isolation structure (1122-a1 + 103a-1, marked in annotated Figs. 28-v2 and 29-v3 below, paras [0051] – [0053]) that extends (see Fig. 29) from an upper surface of the dielectric layer (upper surface of “1122-b”) to a level below respective upper surfaces of the first and second source/drain regions (lower surface of “103a-1” is below the upper surface of the S/D regions, see Fig. 29), the isolation structure (1122-a1 + 103a-1) disposed laterally between (see annotated Fig. 29-v3 below) the first source/drain region (“111b-1”) and the second source/drain region (“111b-2”), and laterally between the first gate structure (“1st gate”) and the second gate structure (“2nd gate”).
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Re Claim 2 Ju teaches the device of claim 1 (Rejection-2), wherein the first source/drain region (“111b-1”) has a first vertical sidewall proximal the isolation structure (right vertical sidewall of 111b-1, see annotated Fig. 29-v3 above), and a second vertical sidewall distal the isolation structure (left vertical sidewall of 111b-1, see annotated Fig. 29-v3 above), the first vertical sidewall being larger in the vertical direction than the second vertical sidewall (see Fig. 29).
Re Claim 8 Ju teaches the device of claim 1 (Rejection-2), wherein the first source/drain region (“111b-1”) is part of a first integrated circuit cell (marked “1st cell” in annotated Figs. 29-v3 above), the second source/drain region (“111b-2”) is part of a second integrated circuit cell (marked “2nd cell” in annotated Figs. 29-v3 above), and the isolation structure (1122-a1 + 103a-1) overlaps a cell boundary (see annotated Fig. 29-v3 above) between the first (“1st cell”) and second integrated circuit cells (“2nd cell”).
Re Claim 9 Ju teaches the device of claim 8, further comprising:
a second isolation structure (marked “103b-1” in annotated Fig. 29-v3 above) positioned in the first integrated circuit cell (“1st cell”), the first source/drain region (“111b-1”) being between (see annotated Fig. 29-v3 above) the isolation structure (1122-a1 + 103a-1) and the second isolation structure (103b-1).
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1).
Re Claim 1, Ju (Rejection-3) teaches a device (Figs. 49-51), comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 50 below, paras [0069] – [0071]) over a substrate (100, see Figs. 28 and 50, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 50 below, paras [0069] – [0071]) over the substrate (100);
a first source/drain region (marked “111a-1” in annotated Fig. 51 below, para [0050]) abutting the first vertical stack of nanostructures (“1st stack”, see Figs. 49-51);
a second source/drain region (marked “111b-1” in annotated Fig. 51 below, para [0050]) abutting the second vertical stack of nanostructures (“2nd stack”, see Figs. 49-51);
a first gate structure (1st 115, marked “1st gate” in annotated Fig. 50 below, paras [0050], [0051] and [0070] – [0071]) wrapping around the nanostructures (see Fig. 50) of the first vertical stack (“1st stack”);
a second gate structure (2nd 115, marked “2nd gate” in annotated Fig. 50 below, paras [0050] – [0051] and [0070] – [0071]) wrapping around the nanostructures (see Fig. 50) of the second vertical stack (“2nd stack”);
a dielectric layer (marked “1122-a” in annotated Fig. 51 below, paras [0044] and [0053]) over the first (“111a-1”) and second source/drain regions (“111b-1”); and
a single, unitary isolation structure (1122-b1 + 103b-1 + 104”-1, marked in annotated Figs. 50 and 51 below, paras [0051] – [0053] and paras [0070] – [0072]) that extends (see Fig. 51) from an upper surface of the dielectric layer (upper surface of “1122-a”) to a level below respective upper surfaces of the first and second source/drain regions (lower surface of “103b-1” is below the upper surface of the S/D regions, see Fig. 51), the isolation structure (1122-b1 + 103b-1 + 104”-1) disposed laterally between (see annotated Fig. 51 below) the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”), and laterally between the first gate structure (“1st gate”) and the second gate structure (“2nd gate”).
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Re Claim 3, Ju teaches the device of claim 1 (Rejection-3), further comprising a wall structure (105’, Fig. 50, para [0068]) laterally between the first and second vertical stacks (“1st stack” and “2nd stack”), wherein the isolation structure (1122-b1 + 103b-1 + 104”-1) contacts the wall structure (105’, see Fig. 50).
Re Claim 4, Ju teaches the device of claim 1 (Rejection-3), further comprising: a wall structure (103a-1 + 105’ + 103a-2 + 114, marked in annotated Figs. 50 and 51 above, para [0053] and paras [0068] – [0072]) between and in direct contact (see annotated Fig. 50 above) with the first vertical stack (“1st stack”) and the second vertical stack (“2nd stack”); wherein the isolation structure (1122-b1 + 103b-1 + 104”-1) lands on the wall structure (isolation structure lands on 105’ which is part of wall structure defined above).
Claims 13-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1).
Re Claim 13, Ju teaches a device, comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 28-v3 below, paras [0049] – [0051]) over a substrate (100, Fig. 27, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 28-v3 below, paras [0049] – [0051]) over the substrate (100);
a third vertical stack of nanostructures (1003’, marked “3rd stack” in annotated Fig. 28-v3 below, paras [0049] – [0051]) over the substrate (100);
a first source/drain region (marked “111a-1” in annotated Fig. 29-v4 below, para [0050]) abutting the first vertical stack of nanostructures (“1st stack”, see Figs. 27-29);
a second source/drain region (marked “111b-1” in annotated Fig. 29-v4 below, para [0050]) abutting the second vertical stack of nanostructures (“2nd stack”, see Figs. 27-29);
a third source/drain region (marked “111b-2” in annotated Fig. 29-v4 below, para [0050]) abutting the third vertical stack of nanostructures (“3rd stack”, see Figs. 27-29);
a first gate structure (115’, marked “1st gate” in annotated Fig. 28-v3 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the first vertical stack (“1st stack”);
a second gate structure (115’, marked “2nd gate” in annotated Fig. 28-v3 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the second vertical stack (“2nd stack”);
a third gate structure (115’, marked “3rd gate” in annotated Fig. 28-v3 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the third vertical stack (“3rd stack”);
a first, unitary isolation structure (1122-1 + 103b-1 + 104”-1, marked in annotated Figs. 28-v3 below and 29-v4 below, paras [0051] – [0053]) disposed laterally between and contacting the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”), and disposed laterally between and contacting the first gate structure (“1st gate”) and the second gate structure (“2nd gate”); and
a second, unitary isolation structure (1122-2 + 103b-2 + 104”-2, marked in annotated Figs. 28-v3 below and 29-v4 below, paras [0051] – [0053]) disposed laterally between and contacting the second gate structure (“2nd gate”) and the third gate structure (“3rd gate”), the second isolation structure (1122-2 + 103b-2 + 104”-2) being laterally between and separated (see annotated Fig. 29-v4 below) from the second source/drain region (“111b-1”) and the third source/drain region (“111b-2”).
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Re Claim 14, Ju teaches the device of claim 13, wherein the first isolation structure (1122-1 + 103b-1 + 104”-1) and the second isolation structure (1122-2 + 103b-2 + 104”-2) are the same material (both the isolation structures are made of same materials).
Re Claim 16, Ju teaches the device of claim 13, further comprising:
a wall structure (105’, Fig. 29, para [0029]) between the first vertical stack (“1st stack”), the second vertical stack (“2nd stack”), the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”);
an isolation region (“103a-1”, marked in annotated Figs. 28-v3 and 29-v4 above) between the second vertical stack (“2nd stack”), the third vertical stack (“3rd stack”), the second source/drain region (“111b-1”) and the third source/drain region (“111b-2”), the wall structure including a different material (105’ is made of the material 105 which is made of the same material as 102 which is silicon oxide, paras [0027] - [0034]) than the isolation region (103a is made of low-k dielectric like SiCN, paras [0027] and [0049]);
wherein the first isolation structure (1122-1 + 103b-1 + 104”-1) includes:
a first portion (1122-1 + 103b-1) that is in contact with the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”), and lands on the wall structure (105’) at a first level (marked “1st level” in annotated Fig. 29-v4 above); and
a second portion (104”-1) that is in contact with the first gate structure (“1st gate”) and the second gate structure (“2nd gate”), and lands on the wall structure (105’) at a second level (marked “2nd level” in annotated Fig. 29-v4 above) further from the substrate than the first level (“2nd level” is higher than the “1st level”, see annotated Figs. 28-v3 and 29-v4 above).
Claims 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1).
Re Claim 13 (Rejection-2), Ju teaches a device, comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 28-v3 above, paras [0049] – [0051]) over a substrate (100, Fig. 27, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 28-v3 above, paras [0049] – [0051]) over the substrate (100);
a third vertical stack of nanostructures (1003’, marked “3rd stack” in annotated Fig. 28-v3 above, paras [0049] – [0051]) over the substrate (100);
a first source/drain region (marked “111a-1” in annotated Fig. 29-v4 above, para [0050]) abutting the first vertical stack of nanostructures (“1st stack”, see Figs. 27-29);
a second source/drain region (marked “111b-1” in annotated Fig. 29-v4 above, para [0050]) abutting the second vertical stack of nanostructures (“2nd stack”, see Figs. 27-29);
a third source/drain region (marked “111b-2” in annotated Fig. 29-v4 above, para [0050]) abutting the third vertical stack of nanostructures (“3rd stack”, see Figs. 27-29);
a first gate structure (115’, marked “1st gate” in annotated Fig. 28-v3 above, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the first vertical stack (“1st stack”);
a second gate structure (115’, marked “2nd gate” in annotated Fig. 28-v3 above, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the second vertical stack (“2nd stack”);
a third gate structure (115’, marked “3rd gate” in annotated Fig. 28-v3 above, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the third vertical stack (“3rd stack”);
a first, unitary isolation structure (1122-1 + 103b-1 + 104”-1, marked in annotated Figs. 28-v3 above and 29-v4 above, paras [0051] – [0053]) disposed laterally between and contacting the first source/drain region (“111a-1”) and the second source/drain region (“111b-1”), and disposed laterally between and contacting the first gate structure (“1st gate”) and the second gate structure (“2nd gate”); and
a second, unitary isolation structure (1122-2 + 103b-2 + 105’-2 + 104”-2, marked in annotated Figs. 28-v3 above and 29-v4 above, paras [0049] – [0053]) disposed laterally between and contacting the second gate structure (“2nd gate”) and the third gate structure (“3rd gate”), the second isolation structure (1122-2 + 103b-2 + 105’-2 + 104”-2) being laterally between and separated (see annotated Fig. 29-v4 above) from the second source/drain region (“111b-1”) and the third source/drain region (“111b-2”).
Re Claim 15, Ju teaches the device of claim 13 (Rejection-2), wherein the second isolation structure (1122-2 + 103b-2 + 105’-2 + 104”-2) is longer in the vertical direction (see annotated Fig. 29-v4 above) than the first isolation structure (1122-1 + 103b-1 + 104”-1).
Claims 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 2020/0266192 A1).
Re Claim 21, Ju teaches a device, comprising:
a first vertical stack of nanostructures (1003’, marked “1st stack” in annotated Fig. 28-v4 below, paras [0049] – [0051]) over a substrate (100, Fig. 27, para [0051]);
a second vertical stack of nanostructures (1003’, marked “2nd stack” in annotated Fig. 28-v4 below, paras [0049] – [0051]) over the substrate (100);
a wall structure (102’+109+1121, Fig. 29, also see Figs. 19 and 27, paras [0041], [0044] and [0049]) laterally between the first (“1st stack”) and second vertical stacks (“2nd stack”), the wall structure (102’+109+1121) including a liner dielectric layer (109, Fig. 29, para [0041]), an etch-stop layer (1121, Figs. 27-29, also see Fig. 19, para [0044]), and a core dielectric layer (102’, Fig. 29, paras [0027] and [0049]);
a first source/drain region (marked “111b-1” in annotated Fig. 29-v5 below, para [0050]) abutting the first vertical stack (“1st stack”, see Figs. 27-29);
a second source/drain region (marked “111b-2” in annotated Fig. 29-v5 below, para [0050]) abutting the second vertical stack (“2nd stack”, see Figs. 27-29);
a first gate structure (115’, marked “1st gate” in annotated Fig. 28-v4 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the first vertical stack (“1st stack”);
a second gate structure (115’, marked “2nd gate” in annotated Fig. 28-v4 below, paras [0050] – [0051]) wrapping around the nanostructures (see Fig. 28) of the second vertical stack (“2nd stack”); and
a unitary isolation structure (1122-1 + 103a-1, marked in annotated Figs. 28-v4 below and 29-v5 below, paras [0051] – [0053]) disposed laterally between the first gate structure (“1st gate”) and the second gate structure (“2nd gate”), and laterally between the first source/drain region (“111b-1”) and the second source/drain region (“111b-2”), the isolation structure (1122-1 + 103a-1) contacting the core dielectric layer (102’) of the wall structure (102’+109+1121).
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Re Claim 22, Ju teaches the device of claim 21, wherein the first source/drain region (“111b-1”) has a first vertical sidewall proximal the isolation structure (right vertical sidewall of 111b-1, see annotated Fig. 29-v5 above), and a second vertical sidewall distal the isolation structure (left vertical sidewall of 111b-1, see annotated Fig. 29-v5 above), the first vertical sidewall being larger in the vertical direction than the second vertical sidewall (see Fig. 29).
Re Claim 23, Ju teaches the device of claim 21, wherein the first gate structure (1st gate) and the second gate structure (“2nd gate”) are laterally separated from each other by the isolation structure (1122-1 + 103a-1, see annotated Fig. 28-v4 above).
Re Claim 24, Ju teaches the device of claim 21, wherein the first source/drain region (“111b-1”) is part of a first integrated circuit cell (marked “1st cell” in annotated Figs. 29-v5 above), the second source/drain region (“111b-2”) is part of a second integrated circuit cell (marked “2nd cell” in annotated Figs. 29-v5 above), and the isolation structure (1122-1 + 103a-1) overlaps a cell boundary between (see annotated Fig. 29-v5 above) the first (“1st cell”) and second integrated circuit cells (“2nd cell”).
Response to Arguments
Applicant’s arguments with respect to claims 1, 13 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claims 1, 13 and 21, applicant argued that the amended claim language “a single, unitary isolation structure” overcomes the rejection of record, made in the Office Action dated 5/29/2025. Examiner respectfully disagrees with the applicant. “A single, unitary” structure does not require a single continuous layer of material. “A single, unitary” structure can still be made of plurality of layers or combinations of layers, and can still form a single entity or “unitary”. The claim language does not preclude this treatment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898