DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/20/2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2021-0119314, filed on 09/07/2021.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant's amendments on 12/16/2025 have been reviewed and entered. Claims 1-2, 4-5, 12, 14, 16, and 18 have been amended. Claims 1-20 remain for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8, 12-13, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Park-1 (US 2019/0148476 A1, embodiment where the planarization layer 116 is an inorganic insulating layer, [0151]).
Regarding claim 1, Park-1 teaches a display panel (display device 100, Fig. 1, [0049]) comprising:
a base layer (substrate 110, Fig. 12, [0104]) including a plurality of pixel areas (pixels PX (Fig.1) including pixels PX1, PX2, …; Figs. 4 and 12, [0082]) and a boundary area (region between the first pixel PX1 and second pixel PX2, Figs. 5 and 12, [0086]) between pixel areas (pixels PX (Fig.1) including pixels PX1, PX2, …; Figs. 4 and 12) next to each other in a second direction (vertical direction in Figs. 4-8: the region between pixel PX1 and PX2, and the region between PX3 and PX4) among the plurality of pixel areas (pixels PX, Figs. 4 and 12, [0083]: “… groove GR disposed in a region between a plurality of pixels, …“);
a pixel circuit (thin film transistors T1-T7, Figs. 4 and 12, [0103]) overlapping a pixel area (first pixel area PX1, Fig. 12) of the plurality of pixel areas (pixels PX, Figs. 4 and 12);
a plurality of insulating layers (buffer layer 111 ([0086]), first gate insulating layer 112 ([0086]), second gate insulating layer 113 ([0086], interlayer insulating layer 115 ([102]), planarization layer 116 ([0151]), Fig. 12) which include at least a first insulating layer (third gate insulating layer 114, Fig. 12) and in which an opening (groove GR, Fig. 12, [0083]) overlapping the boundary area (region between the first pixel PX1 and second pixel PX2, Figs. 7 and 12) is defined;
a first signal line (first connection wire 140, Fig. 12, [0098]: “The first connection wiring 140 and the second connection wiring 150 may serve as wirings that transfer an electric signal to the pixels. “) disposed on the first insulating layer (third gate insulating layer 114, Fig. 12), overlapping the boundary area (region between the first pixel PX1 and second pixel PX2, Fig. 12) and the pixel areas (first pixel area PX1, Fig. 12) and extending in a first direction (horizontal direction in Figs. 4-8 and 12) crossing the second direction (first direction is perpendicular to the second direction, and therefore crosses the second direction);
an organic layer (organic material layer 161 and upper-organic material layer 163, Figs. 7 and 12, [0094]; [0178]: ”The upper-organic material layer 163 may include the same material as that of the organic material layer 161.”) including a first portion (see first portion in Illustrative Fig. 1, which is an annotated version of Fig. 12) filling the opening (groove GR, Illustrative Fig. 1); and
a light-emitting element (OLED, Illustrative Fig. 1, [0157]) disposed on the plurality of insulating layers (buffer layer 111, first gate insulating layer 112, second gate insulating layer 113, third gate insulating layer 114, interlayer insulating layer 115, planarization layer 116; Illustrative Fig. 1) and electrically connected to the pixel circuit (driving thin film transistor T1, Illustrative Fig. 1, [0110]: pixel circuit including the driving thin film transistor T1 controls the OLED, and therefore electrically connected to the OLED),
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wherein the opening (groove GR, Illustrative Fig. 1) includes:
a first area (the portion of the top surface of the first connection wire 140 within the groove, Illustrative Fig. 1, see also Illustrative Fig. 2 which is an annotated version of Fig. 8 (top view) and shows the first area from top view) overlapping the first signal line (first connection wire 140/142, Illustrative Figs. 1-2 (see also I-I’ in Fig. 4 for the location of the cross-section shown in Illustrative Fig. 1)), the first area having a first depth (first depth, Illustrative Fig. 1); and
a second area (bottom surface of the groove GR that is not under the first connection wire 140, see second area in Illustrative Figs. 2) having a second depth (second depth, Illustrative Fig. 1) greater than the first depth (first depth, Illustrative Fig. 1), and the first area (first area, Illustrative Fig. 2) and the second area (second area, Illustrative Fig. 2) are arranged in the second direction (second direction, Illustrative Fig. 2).
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Regarding claim 7, Park-1 the display panel of claim 1, further comprising a barrier layer (barrier layer 101, Fig. 12, [0106]) disposed on the base layer (substrate 110, Fig. 12, [0104]),
wherein the opening (groove GR, Fig. 12, [0083]) exposes the barrier layer (barrier layer 101, Fig. 12) in the second area (bottom surface of the groove GR that is not under the first connection wire 140, Fig. 12, see also Fig. 8 for top view).
Regarding claim 8, Park-1 teaches the display panel of claim 7, wherein in the second area (bottom surface of the groove GR that is not under the first connection wire 140, Fig. 12, see also Fig. 8 for top view), the barrier layer (barrier layer 101, Fig. 12, [0106]) contacts the organic layer (organic material layer 161, Fig. 12).
Regarding claim 12, Park-1 teaches the display panel of claim 1, wherein the boundary area (region between pixels PX1, PX2, PX3, …, Illustrative Fig. 2, [0082]) includes a first boundary area (horizontal portions of the boundary area between the rows of pixels, Illustrative Fig. 2) extending in the first direction (first direction, Illustrative Fig. 2) and a second boundary area (vertical portions of the boundary area between the columns of pixels, Illustrative Fig. 2) extending in the second direction (second direction, Illustrative Fig. 2) crossing the first direction (Illustrative Fig. 2: first and second directions are perpendicular to each other and cross each other), and
wherein the first signal line (first connection wire 142, Illustrative Fig. 2) extends in the first direction (first direction, Illustrative Fig. 2).
Regarding claim 13, Park-1 teaches the display panel of claim 1, wherein the plurality of insulating layers (buffer layer 111 ([0086]), first gate insulating layer 112 ([0086]), second gate insulating layer 113 ([0086]), third gate insulating layer 114 ([0086]), interlayer insulating layer 115 ([0140]), planarization layer 116 ([0151], Fig. 12) further includes a buffer layer (buffer layer 111, Fig. 12) disposed under the first insulating layer (third gate insulating layer 114, Fig. 12), a second insulating layer (interlayer insulating layer 115, Figs. 12) disposed on the first insulating layer (third gate insulating layer 114, Fig. 12), and a third insulating layer (planarization layer 116, Fig. 12) disposed on the second insulating layer (interlayer insulating layer 115, Fig. 12),
wherein the first area (the portion of the top surface of the first connection wire 140 within the groove, Fig. 12) penetrates the second insulating layer (interlayer insulating layer 115, Fig. 12) and the third insulating layer (planarization layer 116, Fig. 12), and
wherein the second area (bottom surface of the groove GR that is not under the first connection wire 140, Fig. 12) penetrates the buffer layer (buffer layer 111, Fig. 12) and the first to third insulating layers (third gate insulating layer 114, interlayer insulating layer 115, planarization layer 116, Fig. 12).
Regarding claim 20, Park-1 teaches the display panel of claim 1,
wherein the boundary area (region between pixels PX1, PX2, PX3, …; Figs. 7) surrounds each of the plurality of pixel areas (pixels PX1, PX2, PX3 …; Fig. 7) in a plan view (Fig. 7), and
wherein one light-emitting element (OLED, Fig. 12, [0157]), two light-emitting elements, or four light-emitting elements are disposed in each of the pixel areas (pixels PX1 and PX2, Fig. 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Park-1 (US 2019/0148476 A1, embodiment where the planarization layer 116 is an inorganic insulating layer, [0151]).
Regarding claim 2, Park-1 teaches the display panel of claim 1, wherein the plurality of insulating layers (buffer layer 111 ([0086]), first gate insulating layer 112 ([0086]), second gate insulating layer 113 ([0086]), third gate insulating layer 114 ([0086]), interlayer insulating layer 115 ([0140], planarization layer 116 ([0151]), Fig. 12) further includes a second insulating layer (interlayer insulating layer 115, Fig. 12) disposed on the first insulating layer (interlayer insulating layer 115, Fig. 12),
wherein the display panel (display device 100, Fig. 1) further comprises a second signal line (data line 151, Figs. 4 and 12, [0140]) disposed on the second insulating layer (interlayer insulating layer 115, Figs. 4 and 12) and overlapping the boundary area (region between the first pixel PX1 and second pixel PX2, Figs. 7 and 12, [0086]) and the pixel areas (first pixel PX1 and third pixel PX3, Fig. 4: the data line 151 runs through the first pixel PX1 and the third pixel PX3, and through the region between the pixels).
Park-1, however, does not teach that
the opening further includes a third area overlapping the second signal line (the second signal line is not in the groove GR, but over the groove GR), the third area having a third depth smaller than the first depth.
Park-1, however, discloses that disposing the organic material layers 161 under the first connection wiring 140 and upper organic material 163 over the first connection wiring 140 would make the first connection wiring 140 stronger against external stress ([0177]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the display panel of Park-1 by extending the opening through the planarization layer 116 to cover the upper surface of the connection wiring 150 (includes data line 151) with an organic material layer, as taught by Park-1, for protecting data line 151 against external stress. This modification of the display device according to the teachings of Park-1 would lead to an opening
wherein the opening further includes a third area (the portion of the top surface of the data line 151 within the groove GR, see Fig. 4 for top view) overlapping the second signal line (data line 151, Fig. 4), the third area having a third depth smaller than the first depth (first depth, Illustrative Fig. 1: the depth of the third area will be smaller than the first depth because the data line 151 is in a higher insulating layer than the first connection wiring 140 is).
Regarding claim 3, Park-1 teaches the display panel of claim 2, wherein the second area (bottom surface of the groove GR that is not under the first connection wire 140 and data line 151 (according to the modification in claim 2), Fig. 8) does not overlap the first signal line (first connection wire 140, Fig. 8) and the second signal line (data line 151, Fig. 8).
Regarding claim 5, Park-1 teaches the display panel of claim 2, wherein in the pixel areas (first pixel PX1 and second pixel PX2, Fig. 12, [0086]), the second insulating layer (interlayer insulating layer 115, Fig. 12, [0151]) covers the first signal line (first connection wire 140, Fig. 12, [0098]).
Regarding claim 6, Park-1 teaches the display panel of claim 2, wherein in the boundary area (region between the first pixel PX1 and second pixel PX2, Figs. 4 and 12, [0086]), a first surface (the bottom surface of the upper organic material 163, Fig. 12) of the organic layer (organic material layers 161 and upper-organic material layers 163, Fig. 12) facing the base layer (substrate 110, Fig. 12, [0104]) contacts the first signal line (first connection wire 140, Fig. 12) and the second signal line (data line 151, Figs. 4 and 12: after the modification of the display device according to claim 2, the organic layer is extended through the planarization layer 116 and cover the data line 151.).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Park-1 ((US 2019/0148476 A1, embodiment where the planarization layer 116 is an inorganic insulating layer, [0151]) as applied to claims 1, 7-8, 12-13, and 20 above, and further in views of He (US 2022/0085074 A1) and Chen (US 2021/0280649 A1).
Regarding claim 9, Park-1 teaches the display panel of claim 1, wherein the pixel circuit includes:
a first transistor (driving thin film transistor TFT T1, Fig. 12, [0065]) including a first source area (driving source electrode S1, Fig. 12, [0067]), a first drain area (driving drain electrode D1, Fig. 12, [0067]), a first channel area (channel region A1, Fig. 12, [0110]), and a first gate (driving gate electrode G1, Fig. 12, [0067]); and
a second transistor (switching TFT T2, Fig. 5, [0103]) including a second source area (switching source region S2, Fig. 5, [0111]), a second drain area (switching drain region D2, Fig. 5, [0111]), a second channel area (switching gate electrode G2, Fig. 5, [0068]) disposed in a different layer (channel region AC2 of the second transistor is in the fourth insulating layer 40, and channel region AC1 of the first transistor is in the first insulating layer 10) from the first channel area (channel region AC1, Fig. 5), and a second (gate GT2, Fig. 5) gate disposed in a different layer from the first gate (gate GT1, Fig. 5: gate GT2 of the second transistor is in the fifth insulating layer 50, and gate region GT1 of the first transistor is in the second insulating layer 20).
Park-1, however, does not teach that
the second gate is disposed in a different layer from the first gate, and
the first signal line is disposed in the same layer as the first gate or the second gate.
He, on the other, hand teaches a pixel circuit-- (pixel circuit 60, Fig. 9, [0062]) for a display device [0005] comprising a first transistor (first transistor 20, Fig. 9, [0051]: a silicon transistor) and a second transistor (third transistor 70, Fig. 9, [0062]: oxide semiconductor transistor), wherein
the second gate (third gate 72, Fig. 9, [0062]) is disposed in a different layer from the first gate (first gate 22, Fig. 9, [0068]).
He further discloses that the having the first transistor 20 as a silicon transistor ([0051]) and the second transistor 70 as an oxide semiconductor transistor ([0062]), the leakage current in the pixel circuit can be reduced ([0004]), and by putting the first and second transistors on different layers, the second active layer can be protected from being eroded by hydrogen and water and oxygen and ensured to have a good performance and meanwhile the migration performance of carriers in the first transistor is ensured to further show a good performance of the first transistor [0011]. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the pixel circuit in the display panel of Park-1 by replacing one of the transistors with an oxide semiconductor transistor and placing the first and second transistors in different layers, as disclosed by He, which will improve the performance of the drive circuit and the performance of the pixel circuit (He, [0011]).
He, however, is silent on that
the first signal line is disposed in the same layer as the first gate or the second gate.
Chen, on the other hand, teaches a display panel (display panel structure, Fig. 2, [0040]-[0043]), wherein a metal trace (trace 220 on the left, Fig. 2) is disposed in the same layer (insulation layer 121, Fig. 2, [0041]) as the first gate (gate electrode 125, Fig. 2, [0043]: “… the trace 220 and the gate electrode 125 are located in the same layer…”) or the second gate.
Chen further disclosed that having the traces and the first gate in the same layer provides the benefit of manufacturing the traces and the devices located in the same layer simultaneously by a same exposure and development process ([0043]), and therefore, reduces the production time and cost. Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to place the first and second transistors in the display panel of Park-1 in view of He in such a way that the first signal line is disposed in the same layer as the first gate or the second gate, as disclosed by Chen, to reduce the manufacturing time and cost.
Regarding claim 11, while Park-1 teaches the display panel of claim 9,
Park-1 does not teach that the first transistor is a silicon transistor, and the second transistor is an oxide transistor.
He, on the other, hand teaches a pixel circuit-- (pixel circuit 60, Fig. 9, [0062]) for a display device [0005] comprising a first transistor (first transistor 20, Fig. 9, [0051]) and a second transistor (third transistor 70, Fig. 9, [0062]), wherein
the first transistor (first transistor 20, Fig. 9, [0051]) is a silicon transistor ([0051]), and the second transistor (third transistor 70, Fig. 9, [0062]) is an oxide transistor ([0062]).
He further discloses that the having the first transistor as a silicon transistor and the second transistor as an oxide semiconductor transistor, the leakage current in the pixel circuit can be reduced ([0004]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a semiconductor transistor for the first transistor and an oxide semiconductor transistor for the second transistor in the display panel of Park-1 in views of He and Chen, as disclosed by He, to improve the performance of the pixel circuit by decreasing the leakage current (He, [0011]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park-1 (US 2019/0148476 A1, embodiment where the planarization layer 116 is an inorganic insulating layer, [0151]) in views of He (US 2022/0085074 A1) and Chen (US 2021/0280649 A1) as applied to claims 9 and 11 above, and further in view of Moon (US 2021/0399074 A1).
Regarding claim 10, while Park-1 in view of He and Chen teaches the display panel of claim 9,
Park-1 does not teach that the second transistor further includes a third gate electrically connected with the second gate and disposed in a different layer from the first gate and the second gate.
He, on the other hand, teaches a pixel circuit (pixel circuit 60, Fig, 9, [0068]) comprising a silicon transistor (first transistor 20 corresponding to first transistor of the current application, Fig. 9, [0051]: “active layer 21 is a poly-silicon active layer”) and an oxide transistor (third transistor 70 corresponding to second transistor of the current application, Fig. 9, [0051]: “The third active layer 71 in the third transistor 70 includes an oxide semiconductor”) wherein the second transistor (third transistor 70, Fig. 9) further includes a third gate (fifth gate 75, Fig. 9, [0061]: the other gate of the transistor is the third gate 72), and disposed in a different layer from the first gate (first gate 22, Fig. 9, [0052]) and the second gate (the third gate 72, Fig. 9, [0061]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a third gate in a stacked configuration with the second gate (making second and third gates to be in different layers) in the second transistor of the display panel of Park-1 in view of He and Chen, as disclosed by He, to enhance the mobility of carriers in the second transistor and the response capability of the second transistor (He, [0062]). A person of ordinary skill in the art before the effective filing date of the claimed invention would be further motivated to form the third gate at a layer different than the first and second gates, as disclosed by He, to be able to control the distances between gate electrodes and corresponding active layers independently and keeping the oxide transistor further away from the substrate to optimize the device longevity (He, [0036]-[0037])
He, however, does not disclose that the third gate is connected with the second gate.
Moon, on the other, hand teaches a transistor substrate for a display device (Fig. 4, [0076]) wherein the bottom gate (metal layer 180, Fig. 4, [0077]-[0078]) and the top gate (first gate electrode 150a, Fig. 4, para. [0078]) of an oxide transistor (first transistor TRa, Fig. 4, [0081]) are connected [0078]: “The metal layer 180 may be connected to the first gate electrode 150a”).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to connect the second and third gates in the display panel of Park-1, in views of Chen-2 and He, as disclosed by Moon, which would provide the benefit of improving the charge mobility in the oxide semiconductor layer (Moon, [0080]).
Thus, the combination of Park-1, He, Chen, and Moon meets all the limitations of claim 10.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park-1 ((US 2019/0148476 A1, embodiment where the planarization layer 116 is an inorganic insulating layer, [0151]) as applied to claims 1, 7-8, 12-13, and 20 above, and further in view of Park-2 (US 2019/0148476 A1, embodiment where the planarization layer 116 is an organic material layer, [0151]).
Regarding claim 18, Park-1 teaches the display panel of claim 1, wherein the organic layer (organic material layer 161 and upper-organic material layer 163, Figs. 7 and 12, [0094]) further includes a second portion (second portion, Illustrative Fig. 1), extending from the first portion (first portion, Illustrative Fig. 1) and overlapping the boundary areas (region between the first pixel PX1 and second pixel PX2, Fig. 12, [0086]).
Park-1, however, does not teach that the second portion overlaps the pixel areas.
Park-2, on the other hand, teaches a display panel (Fig. 12) with an organic layer (comprising planarization layer 116, organic material layer 161 and upper-organic material layer 163, Fig. 12, [0151]: “The planarization layer 116 may include, for example, an organic material, … ”) as planarization layer with a second portion (see second portion in Illustrative Fig. 3, which is an annotated version of Fig. 12) which extends from the first portion (first portion in Illustrative Fig. 3) and overlaps the boundary area (region between the first pixel PX1 and second pixel PX2, Illustrative Fig. 3, [0086]) and the pixel areas (pixels PX1 and PX2 Illustrative Fig. 3, [0082]).
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It would be obvious to a person of ordinary skill in the art that having the planarization layer from an organic material would provide the benefit of reducing the stress in the underlying areas of the display device and increase the flexibility of the display device during bending, as evidenced by Chen (US 2021/0280649 A1, [0037]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the display panel of Park-1 to make the planarization layer 116 from an organic material as the second portion of the organic layer, as disclosed by Park-2, which would provide the benefit of increasing the stress and flexibility of the display panel between pixels (Chen, [0037]).
Thus, the combination of Park-1 and Park-2 meets all the limitations of claim 18.
Allowable Subject Matter
Claims 4 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4, disclosing the limitation that “the second signal line extends in the first direction”, would be allowable if this limitation is incorporated in a claim combining claims 1 and 2. Regarding the closest prior art, Cheng (US 2022/0406879 A1) discloses a display panel wherein the signal lines (metal layers 214-217, Fig. 6) extending in the same direction are distributed between different insulating layers (205-210, Fig. 6). However, Cheng cannot modify the display panel of Park-1 (US 2019/0148476 A1) as disclosed in claim 2, because of the limitation that the signal lines need to be separated in the lateral direction due to the limitation claimed in claim 2, which is against the motivation of placing the signal lines in different layers (to minimize lateral width) in Cheng. There is no other prior art identified that can be combined with Park-1 to make claim 4 obvious considering the inherited limitations from claims 1 and 2.
Claim 19, disclosing the limitations that “a data line is disposed on the second portion” and “a data line is connected through a contact hole defined through the second portion“, would be allowable if this limitations are incorporated in a claim combining claims 1 and 18. There is no prior art identified that can modify Park-1 to make claim 19 obvious.
Claim 14-17 are allowed.
Claim 14, which is amended to express previously objected claim 14 in an independent form, is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitation that “a first opening and a second opening are defined in the first insulating layer with the first insulating portion therebetween” and “the first opening and the second opening constitute a portion of the opening of the plurality of insulating layers”, “as recited in claim 14, in combination with the remaining structural components of the claim.
Regarding the closest prior art, Park-1 teaches all the limitations of claim 14 except the limitations stated above. In terms of secondary references that can modify Park-1, Chen (US 2021/0280649 A1) discloses a display panel (display panel structure, Fig. 2) with a bending area (bending region 100B, Fig. 2, [0030]) which comprises a first opening (left portion of hole 131b, Fig. 2) and a second opening (right portion of hole 131b, Fig. 2). However, Cheng does not disclose that these holes are between the pixels (disclosed in claim 1) and there is no motivation to modify the regions between the pixels in Park-1 to include the insulating layers between the pixels as disclosed by Chen. There is no other prior art identified that can make, by itself or in combination with Park-1 or Chen, claim 14 obvious or anticipated.
Claim 15 is also allowed, because claim 15 inherits allowable subject matter from allowed claim 14.
Claim 16, which is amended to express previously objected claim 16 in an independent form, is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitations that “an organic insulating layer disposed on … an outermost insulating layer farthest from the base layer among the plurality of insulating layers and contacting the first portion and the outermost insulating layer” and “a data line disposed on the organic insulating layer”, as recited in claim 16, in combination with the remaining structural components of the claim.
Regarding the closest prior art, Park-1, again, Park-1 teaches all the limitations of claim 16 except the limitation stated above. In terms of secondary references that can modify Park-1, Chen (US 2021/0280649 A1) discloses a display panel (display panel structure, Fig. 2) with a bending area (bending region 100B, Fig. 2, [0030]) which comprises an organic layer (planarizing layer 200, Fig. 2, [0036]-[0037]) extending over the outermost insulating layer (interlayer insulation layer 123, Fig. 2, [0033]) and carrying traces(trace 220, Fig. 2, [0039]) which can be data lines. However, extending the organic layer over the outermost insulating layer, as disclosed by Chen, in the display of Park-1 would require rearranging the signal lines between layers, and therefore cannot be motivated as a single preferable or definite improvement for the display device of Park-1, due to required significant changes in the design of the device. There is no other prior art identified that can make, by itself or in combination with Park-1 or Chen, claim 16 obvious or anticipated.
Claim 17 is also allowed, because claim 17 inherits allowable subject matter from allowed claim 16.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-2, 4-5, 12, 14, 16, and 18 per response dated on 12/16/2025. Applicant's arguments with respect to claims have been fully considered.
Applicant argues in substance:
The Examiner states that Park-1 teaches "a plurality of insulating layers (buffer layer 111 ([0086]), first gate insulating layer 112 ([0086]), second gate insulating layer 113 ([0086]), third gate insulating layer 114 ([0086]), interlayer insulating layer 115 ([0140]), planarization layer 116 ([0151]), Fig. 12) which include at least a first insulating layer (third gate insulating layer 114, Fig. 12) and in which an opening overlapping (groove GR, Fig. 12, [0083]) the boundary area (region between the first pixel PXI and second pixel PX2, Figs. 7 and 12) is defined".
As noted above, the Examiner states that the planarization layer 116 corresponds to the claimed insulating layer. However, it is noted that Park-1 merely discloses that the planarization layer 116 may be an inorganic layer, and does not disclose that the planarization layer 116 is an insulating layer as there are numerous inorganic layers that are highly conductive or semiconducting
The Examiner agrees with the Applicant on that Park-1 does not explicitly disclose that the planarization layer is an insulating layer. However, a person of ordinary skill in the art will understand that the planarization layer has to be an insulating layer, because (see Fig. 12), otherwise all connection lines in this layer (such as wiring 150) and all connection lines going through this layer (vias) would be shorted and the display device would be non-functional. Therefore, the Applicant’s argument regarding the planarization layer 116 is not persuasive.
Further, the Examiner states that Park-1 teaches "wherein the opening (groove GR, Illustrative Fig. 1) includes: a first area (the portion of the top surface of the first connection wire 140 within the groove, Illustrative Fig. 1, see also Fig. 8 for top view) overlapping the first signal line (the first connection wire 140), the first area (the portion of the top surface of the first connection wire 140 within the groove GR, Illustrative Fig. 1) having a first depth (first depth, Illustrative Fig. 1); a second area (bottom surface of the groove GR that is not under the first connection wire 140, Illustrative Fig. 1, see also Fig. 8 for top view) having a second depth (second depth, Illustrative Fig. 1) greater than the first depth (first depth, Illustrative Fig. 1)".
However, referring to Illustrative Fig. 1 annotated by the Examiner and reproduced below, the Examiner equates a thickness of only a portion of the alleged opening GR, which is defined in the insulating layer 115 above the alleged first connection wire 140 and in which the organic layer 163 is disposed, with the claimed first depth of the first area. However, since the portion under the alleged first connection wire 140 is also an opening defined in the alleged insulating layers 111 to 115 and filled with the organic layer 161 (which is actually the same as the organic layer 163 except for the location; paragraph 0178 of Park-1 - "The upper-organic material layer 163 may include the same material as that of the organic material layer 161"), it is respectfully submitted that a thickness of the portion under the alleged first connection wire 140 should be also considered as the alleged first depth by the same standard.
The Examiner respectfully disagrees with the Applicant’s argument about the definition of the depth (thickness), because, as it can be seen in Fig. 8A, the depths of the areas overlapping the signal lines are also defined as the depth from the top surfaces of the signal lines in the application. The same standard was applied in the interpretation of Park-1. The Examiner recommends that the Applicant clarifies the definition of depths in the claim language to eliminate any broader interpretation than intended.
Further, referring to FIG. 8 of Park-1 (reproduced below), the Examiner appears to equate an area (annotated in FIG. 8 of Park-1 below) of the groove GR, in which the first connection wire 140 is disposed, with the claimed first area, and equate an area (annotated in FIG. 8 of Park-I below) of the groove GR, in which the first connection wire 140 is not disposed ("bottom surface of the groove GR that is not under the first connection wire 140"), with the claimed second area. However, in Park-1, it is noted that the alleged first area and the alleged second area are arranged in a direction (e.g., vertical direction in FIG. 8 of Park-1) perpendicular to a direction (e.g., horizontal direction in FIG. 8 of Park-1) along which the pixel areas PX1 and PX2 are arranged and the alleged first connection wire 140 extends.
Therefore, it is respectfully submitted that Park-1 does not disclose "a base layer including a plurality of pixel areas and a boundary area between pixel areas next to each other in a second direction among the plurality of pixel areas;... a first signal line disposed on the first insulating layer, overlapping the boundary area and the pixel areas and extending in a first direction crossing the second direction ... the first area and the second area are arranged in the second direction," as recited in amended claim 1.
In contrast, as shown in FIG. 6 and 8A of the present application, for example, pixel areas are next to each other in a second direction (e.g., DR2 in FIG. 6 or horizontal direction in FIG. 8A) among the plurality of pixel areas; the first signal line extends in a first direction (e.g., DRI in FIG. 6) crossing the second direction, and the first area and the second area are arranged in the second direction.
The Examiner respectfully disagrees with the Applicant on that Park-1 does not disclose "a base layer including a plurality of pixel areas and a boundary area between pixel areas next to each other in a second direction among the plurality of pixel areas;... a first signal line disposed on the first insulating layer, overlapping the boundary area and the pixel areas and extending in a first direction crossing the second direction ... the first area and the second area are arranged in the second direction.” To clarify this point, the current office action now includes an Illustrative Figure 2 which shows the directions and the locations of the pixels and the signal lines. The Examiner again recommends that the Applicant modifies the claim language to eliminate the possibility of any broader interpretation than intended.
Accordingly, claim 1 is again rejected based on Park-1. Claim 2-3, 5-13, 18, and 20 are also rejected based on the prior art of the final office action, and claim 4 and 19 are objected due to their dependency on rejected claims. Claims 14 and 16, however, are allowed because both of these claims were written in an independent form including the allowable subject matter indicated in the final office action. Claims 15 and 17 are also allowed because of their dependencies on allowed claims 14 and 16, respectively.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating limitations disclosed in objected claims 4 and/or 19 with claim 1 will make the independent claim 1 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jang (US 2023/0008830 A1) teaches a display panel, which relevant to all claims.
Park (US 2018/0204896 A1) teaches a flexible display which is relevant to all claims.
Lee (US 2021/0202681 A1) teaches a display device, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/
Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812