DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,6, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Briggs et al (US Patent No. 10395986), in view of Ren et al (US Pub No. 20180315650).
With respect to claim 1, Hasegawa discloses forming a first interlayer dielectric (ILD) (PMD) over a source/drain (where CP is connected to in sub); etching a first opening through the first ILD (Para 59), wherein the first opening partially exposes the source/drain (Fig.6); filling the first opening with a source/drain contact (CP); forming one or more dielectric layers (ILD,Fig.16) over the first ILD and over the source/drain contact (Fig.16); etching a second opening through the one or more dielectric layers (VH,Fig.11), and filling the second opening with a source/drain via (Vp,Fig.16), wherein the filling the second opening is performed using a selective metal growth process (Para 68). However, Hasegawa does not explicitly disclose wherein the second opening exposes the source/drain contact. On the other hand, Moon et al discloses wherein the second opening ( the opening in 30 and 32 that exposes 16,Fig.7) exposes the source/drain contact (Fig.7). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the Hasegawa according to the teachings of the Moon et al such that the second opening exposes the source drain contact, in order to save cost and lessen the manufacturing time. However, the arts cited above do not explicitly disclose that deposits a metal material on an exposed upper surface of the source/drain contact but not directly on exposed surfaces of the one or more dielectric layers. On the other hand, Briggs et al discloses a metal material (claim 1) on an exposed upper surface of metal lines (Claim 1) but not directly on exposed surfaces of the one or more dielectric layers (Claim 1). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Briggs et al such that that deposits a metal material on an exposed upper surface of the source/drain contact but not directly on exposed surfaces of the one or more dielectric layers, in order to avoid CMP process, thereby cutting cost. However, the arts cited above do not explicitly disclose wherein the selective metal growth process is performed until the deposited metal material extends to side surfaces of the one or more dielectric layers. On the other hand, Ren et al discloses wherein the selective metal growth process (220,Fig.2F) is performed until the deposited metal material (220) extends to side surfaces of the one or more dielectric layers (210 on the side and the middle, Fig.2E-F). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Ren et al such that selective metal deposition is performed until the deposited metal extends to side surfaces of the one or more dielectric layers, in order to produce a low resistance contact structure.
With respect to claim 2, Hasegawa discloses wherein the filling the second opening is performed without using a glue layer (Fig.13).
With respect to claim 3, Hasegawa discloses wherein the selective metal growth process includes a selective chemical vapor deposition (CVD) (para 68).
With respect to claim 6, the arts cited above do not explicitly disclose wherein the source/drain contact is formed to have a first material composition, and wherein the source/drain via is formed with a second material composition different from the first material composition. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that source drain contact is made from copper and the via is formed aluminum, in order to cut the cost and improve the performance of the device, as a design choice.
With respect to claim 8, Moon et al discloses wherein the forming the one or more dielectric layers includes: forming an etching-stop layer (30) over the first ILD (14) and over the source/drain contact (Fig.9); and forming a second ILD over the etching-stop layer (32).
With respect to claim 9, Moon et al discloses wherein the etching the second opening includes: etching a first portion of the second opening in the second ILD (Fig.7); and etching a second portion of the second opening in the etching-stop layer (Fig.7), However, the arts cited above do not explicitly disclose wherein the second portion of the second opening is etched to be wider than the first portion of the second opening. However, Hasegawa discloses that word line (WL1,Fig.1) which contacts the first ILD (PMD) has a trapezoidal shape (Fig.1) with bottom wider than the top (Fig.1). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Hasegawa such that the word line is incorporated in the devices described above so the second portion of the second opening is etched to be wider than the first portion of the second opening, in order to use the device for the memory applications.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Wu et al (US Patent No. 6821841), in view of Briggs et al (US Patent No. 10395986), in view of Ren et al (US Pub No. 20180315650).
With respect to claim 4, Hasegawa discloses that VP is made from tungsten (Para 47), however, the arts cited above do not explicitly disclose wherein the selective CVD is performed at a pressure in a range between about 1 Torr and about 50 Torr, and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius. On the other hand, Wu et al discloses wherein the tungsten plug (col 4, lines 55-65) is formed using selective CVD ( col 4) is performed at a pressure in a range between about 1 Torr and about 50 Torr (Col 4), and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius (Col 4). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Wu et al such that tungsten plug is formed using process parameters described in the claim 4, in order to make a uniform and defect free tungsten plug.
With respect to claim 5, Wu et al discloses wherein the selective CVD is performed using WF6 (Col 4) or WCl5 as a precursor gas.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Sharangpani et al (US Pub No. 20160149049), in view of Briggs et al (US Patent No. 10395986), in view of Ren et al (US Pub No. 20180315650).
With respect to claim 7, the arts cited above do not explicitly disclose wherein the selective metal growth process selectively deposits polycrystalline tungsten on an upper surface of the source/drain contact. On the other hand, Sharangpani et al discloses that the plug is formed by polycrystalline tungsten (Para 103). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Sharangpani et al such that polycrystalline tungsten is used for the contact material because of it’s excellent durability.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Nakatsuji et al (US Patent No. 10355017), in view of Briggs et al (US Patent No. 10395986), in view of Ren et al (US Pub No. 20180315650).
With respect to claim 10, Hasegawa discloses wherein the first ILD (PMD) is formed over a gate (TR on the right), and wherein the method further comprises: etching a third opening through the one or more dielectric layers and through the first ILD (Fig.1). However, the arts cited above do not explicitly disclose wherein the third opening partially exposes the gate; partially filling the third opening with a glue layer; and completely filling the third opening with a gate via, wherein the gate via is formed on the glue layer. On the other hand, Nakatsuji et al et discloses it passes one or more dielectric layer (763) wherein the third opening partially exposes the gate (754); partially filling the third opening with a glue layer (782A); and completely filling the third opening with a gate via (782B), wherein the gate via is formed on the glue layer (Fig.12). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Nkatsuji et al such that the third opening partially exposes the gate; partially filling the third opening with a glue layer; and completely filling the third opening with a gate via, wherein the gate via is formed on the glue layer, in order to make the logic device functioning, and be able to process signals.
Allowable Subject Matter
Claims 11-20 are allowed.
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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