DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Briggs et al (US Patent No. 10395986).
With respect to claim 1, Hasegawa discloses forming a first interlayer dielectric (ILD) (PMD) over a source/drain (where CP is connected to in sub); etching a first opening through the first ILD (Para 59), wherein the first opening partially exposes the source/drain (Fig.6); filling the first opening with a source/drain contact (CP); forming one or more dielectric layers (ILD,Fig.16) over the first ILD and over the source/drain contact (Fig.16); etching a second opening through the one or more dielectric layers (VH,Fig.11), and filling the second opening with a source/drain via (Vp,Fig.16), wherein the filling the second opening is performed using a selective metal growth process (Para 68). However, Hasegawa does not explicitly disclose wherein the second opening exposes the source/drain contact. On the other hand, Moon et al discloses wherein the second opening ( the opening in 30 and 32 that exposes 16,Fig.7) exposes the source/drain contact (Fig.7). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the Hasegawa according to the teachings of the Moon et al such that the second opening exposes the source drain contact, in order to save cost and lessen the manufacturing time. However, the arts cited above do not explicitly disclose that deposits a metal material on an exposed upper surface of the source/drain contact but not directly on exposed surfaces of the one or more dielectric layers. On the other hand, Briggs et al discloses a metal material (claim 1) on an exposed upper surface of metal lines (Claim 1) but not directly on exposed surfaces of the one or more dielectric layers (Claim 1). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Briggs et al such that that deposits a metal material on an exposed upper surface of the source/drain contact but not directly on exposed surfaces of the one or more dielectric layers, in order to avoid CMP process, thereby cutting cost.
With respect to claim 2, Hasegawa discloses wherein the filling the second opening is performed without using a glue layer (Fig.13).
With respect to claim 3, Hasegawa discloses wherein the selective metal growth process includes a selective chemical vapor deposition (CVD) (para 68).
With respect to claim 8, Moon et al discloses wherein the forming the one or more dielectric layers includes: forming an etching-stop layer (30) over the first ILD (14) and over the source/drain contact (Fig.9); and forming a second ILD over the etching-stop layer (32).
With respect to claim 9, Moon et al discloses wherein the etching the second opening includes: etching a first portion of the second opening in the second ILD (Fig.7); and etching a second portion of the second opening in the etching-stop layer (Fig.7), However, the arts cited above do not explicitly disclose wherein the second portion of the second opening is etched to be wider than the first portion of the second opening. However, Hasegawa discloses that word line (WL1,Fig.1) which contacts the first ILD (PMD) has a trapezoidal shape (Fig.1) with bottom wider than the top (Fig.1). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Hasegawa such that the word line is incorporated in the devices described above so the second portion of the second opening is etched to be wider than the first portion of the second opening, in order to use the device for the memory applications.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Wu et al (US Patent No. 6821841), in view of Briggs et al (US Patent No. 10395986).
With respect to claim 4, Hasegawa discloses that VP is made from tungsten (Para 47), however, the arts cited above do not explicitly disclose wherein the selective CVD is performed at a pressure in a range between about 1 Torr and about 50 Torr, and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius. On the other hand, Wu et al discloses wherein the tungsten plug (col 4, lines 55-65) is formed using selective CVD ( col 4) is performed at a pressure in a range between about 1 Torr and about 50 Torr (Col 4), and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius (Col 4). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Wu et al such that tungsten plug is formed using process parameters described in the claim 4, in order to make a uniform and defect free tungsten plug.
With respect to claim 5, Wu et al discloses wherein the selective CVD is performed using WF6 (Col 4) or WCl5 as a precursor gas.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Wu et al (US Patent No. 6821841), Fujimori et al (US Pub No. 20120313218), in view of Briggs et al (US Patent No. 10395986).
With respect to claim 6, Wu et al discloses that silane is used to reduce the WF6 gas, but it does not explicitly disclose wherein the selective CVD is performed by mixing the precursor gas with H2. On the other hand, Fujimori et al discloses wherein the WF6 gas is can be reduced by H2 instead of silane (Para 4). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Fujimori et al such that hydrogen is used instead of silane, because they are interchangeable, and hydrogen is more available and cheaper than silane.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Sharangpani et al (US Pub No. 20160149049), in view of Briggs et al (US Patent No. 10395986).
With respect to claim 7, the arts cited above do not explicitly disclose wherein the selective metal growth process selectively deposits polycrystalline tungsten on an upper surface of the source/drain contact. On the other hand, Sharangpani et al discloses that the plug is formed by polycrystalline tungsten (Para 103). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Sharangpani et al such that polycrystalline tungsten is used for the contact material because of it’s excellent durability.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Nakatsuji et al (US Patent No. 10355017), in view of Briggs et al (US Patent No. 10395986).
With respect to claim 10, Hasegawa discloses wherein the first ILD (PMD) is formed over a gate (TR on the right), and wherein the method further comprises: etching a third opening through the one or more dielectric layers and through the first ILD (Fig.1). However, the arts cited above do not explicitly disclose wherein the third opening partially exposes the gate; partially filling the third opening with a glue layer; and completely filling the third opening with a gate via, wherein the gate via is formed on the glue layer. On the other hand, Nakatsuji et al et discloses it passes one or more dielectric layer (763) wherein the third opening partially exposes the gate (754); partially filling the third opening with a glue layer (782A); and completely filling the third opening with a gate via (782B), wherein the gate via is formed on the glue layer (Fig.12). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Nkatsuji et al such that the third opening partially exposes the gate; partially filling the third opening with a glue layer; and completely filling the third opening with a gate via, wherein the gate via is formed on the glue layer, in order to make the logic device functioning, and be able to process signals.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al (US Pub No. 20140035164), in view of Hasegawa (US Pub No. 20180277486).
With respect to claim 11, Moon et al discloses forming a first interlayer dielectric (ILD) (14,Fig.1A) over a source/drain (12 is a transistor naturally it has source and drain next to it); forming a contact hole through the first ILD (where 16 is formed),; depositing a source/drain contact in the source/drain contact hole (16); forming an etching-stop layer over the first ILD (30) and over the source/drain contact (Fig.1A); forming a second ILD over the etching-stop layer (38); performing a second etching process (Fig.7) that etches a top portion of a source/drain via hole in the etching stop layer (Fig.7); performing a third etching process that etches a bottom portion of the source/drain via hole in the etching stop layer (Fig.7); and depositing a source/drain via (36,Fig.8) that fills both the top portion and the bottom portion of the source/drain via hole (Fig.8). However, Moon et al does not explicitly disclose performing etching process to make via in the first and second ILDs, and in the etch stop layer, in order to make contact holes for source and drain; wherein the source/drain contact hole partially exposes the source/drain, wherein the bottom portion is etched to be wider than top portion,
etching second ILD, wherein the top portion of the source/drain via hole has a side surface that slopes inwards as a depth of the source/drain via hole increases. On the other hand, Hasegawa discloses performing etching process to make via in the first and second ILDs, and in the etch stop layer(Para 59,66) , in order to make contact holes for source and drain (Fig.1); wherein the source/drain contact hole partially exposes the source/drain (Fig.6), wherein the bottom portion is etched to be wider than top portion (WL1 next to the PMD is wider than it’s top portion; therefore the bottom portion next to the first ILD, which is where the etch stop layer located according to the Moon et al is wider than the top portion); furthermore, Hasegawa discloses etching second ILD (ILD,IFg,2), wherein the top portion of the source/drain via hole has a side surface that slopes inwards as a depth of the source/drain via hole increases (VP,Fig.2). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Moon et al according to the teachings of the Hasegawa such that etch stop layer has a wider Via hole than the second ILD layer, in order to be able to use the transistors for memory applications to process data. Moon et al does not explicitly disclose that the layer 16 is connected to the source or drain. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Moon et al such that layer 16 is connected to the source or drain, in order to make the transistor functioning so it can be used for processing data. Furthermore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Moon et al according to the teachings of the Hasegawa such that via hole has a side surface that slopes inwards as depth of the source and drain via hole increase, in order to minimize material used to fabricate the device, thereby cutting cost.
With respect to claim 12, Moon et al discloses wherein the depositing the source/drain via is performed without using a glue layer (Fig.1A), such that the source/drain via comes into direct contact with an upper surface of the source/drain contact (Fig.1A), with side surfaces of the etching-stop layer (Fg.1A), and with side surfaces of the second ILD (Fig.1A).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al (US Pub No. 20140035164), in view of Hasegawa (US Pub No. 20180277486), in view of Nakatsuji et al (US Patent No. 10355017).
With respect to claim 13, Hasegawa discloses wherein the first ILD is formed over a gate (right gate Fig.19), and wherein the method further comprises: etching a gate via hole through the second ILD (ILD), through the etching-stop layer (30 Moon et al), and through the first ILD (PMD), wherein the gate via hole partially exposes the gate (Fig.19). However, the arts cited above do not explicitly disclose depositing a glue layer on bottom and side surfaces of the gate via hole; and depositing a gate via on the glue layer, wherein the gate via completely fills the gate via hole. On the other hand, Nakatsuji et al discloses depositing a glue layer (782A,Fig.12) on bottom and side surfaces of the gate via hole (FIg.12); and depositing a gate via on the glue layer (782B), wherein the gate via completely fills the gate via hole (Fig.12). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Nakatsuji et al such that gate contact having adhesion layer is formed in order to improve contact to the gate electrode for making the device functioning for the purpose of processing data.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al (US Pub No. 20140035164), in view of Hasegawa (US Pub No. 20180277486), in view of Wu et al (US Patent No. 6821841), Sharangpani et al (US Pub No. 20160149049).
With respect to claim 14, Hasegawa discloses that VP is made out of tungsten (Para 47) ; however, the arts cited above do not explicitly disclose wherein the depositing the source/drain via is performed using a selective metal growth process in which polycrystalline tungsten is deposited as the source/drain via, and wherein the selective metal growth process is performed at a pressure in a range between about 1 Torr and about 50 Torr, and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius. On the other hand, Wu et al discloses wherein the tungsten plug (col 4, lines 55-65) is formed using selective CVD ( col 4) is performed at a pressure in a range between about 1 Torr and about 50 Torr (Col 4), and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius (Col 4). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Wu et al such that tungsten plug is formed using process parameters described in the claim 14, in order to make a uniform and defect free tungsten plug. However, still the arts cited above in view of Wu et al do not explicitly disclose polycrystalline tungsten is used. On the other hand, Sharangpani et al discloses that the plug is formed by polycrystalline tungsten (Para 103). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Sharangpani et al such that polycrystalline tungsten is used for the contact material because of it’s excellent durability.
Claim(s) 15-16,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Hsieh et al (US Pub No. 20180174904), in view of Hsu et al (US Pub No. 2017022008).
With respect to claim 15, Hasegawa discloses forming a source/drain (where CH is connected to in sub,Fig.16) and a gate (Fig.16) structure over a substrate (Sub) ; forming a first interlayer dielectric (PMD) over the source/drain and over the gate (Fig.16) forming a source/drain contact over the source/drain (CH), wherein the source/drain contact extends through the first ILD vertically (Fig.16), furthermore, Hasegawa discloses that second ILD (ILD) having via hole (where VH, ML1 is formed) that exposes source and drain contact (CH or CP), and wherein the ILD and PMD are both etched (Para 59,66). However, Hasegawa does not explicitly disclose having forming an etching-stop layer over the first ILD; forming a second ILD over the etching-stop layer; etching the second ILD and the etching-stop layer to form a first via-hole that exposes the source/drain contact; forming a source/drain via in the first via-hole, wherein the source/drain via is formed to be in direct physical contact with the source/drain contact, the etching-stop layer, and the second ILD; after the forming of the source/drain via, etching the second ILD, the etching-stop layer, and the first ILD to form a second via-hole that exposes the gate structure; and forming a gate via in the second via-hole. On the other hand, Moon et al having forming an etching-stop layer (30,Fig.1A) over the first ILD (14); forming a second ILD (32) over the etching-stop layer; etching the second ILD (Fig.1A, and was described by the primary reference) and the etching-stop layer (Fig.1A) to form a first via-hole that exposes the source/drain contact (16); forming a source/drain via in the first via-hole (Fig.1A), wherein the source/drain via is formed to be in direct physical contact with the source/drain contact (Fig.1A), the etching-stop layer (Fig.1A), and the second ILD (Fig.1A). However the arts cited above do not explicitly disclose after the forming of the source/drain via, etching the second ILD, the etching-stop layer, and the first ILD to form a second via-hole that exposes the gate structure; and forming a gate via in the second via-hole. On the other hand, Hsieh et al discloses after the forming of the source/drain via (74,Fig.14), etching the second ILD (64), the etching-stop layer ( 62), and the first ILD ( 40) to form a second via-hole (82) that exposes the gate structure (Fig.17); and forming a gate via in the second via-hole (98,Fig.21). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Hsieh et al such that the gate electrode is also wired by the via, in order to make the transistor functional, and to be used to process information. The arts cited above do not explicitly disclose wherein a barrier layer is formed between the source/drain contact and the first ILD, and the source/drain via has no barrier between it and the second ILD and the etch stop layer. On the other hand, Hsu et al discloses wherein a barrier layer (70,Fig.17) is formed between the source/drain contact (75) and the first ILD (40), and the source/drain via (110) has no barrier (fig.17) between it and the second ILD (100) and the etch stop layer (90). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Hsu et al such that the via does not have any barrier layer, in order to cut the cost of the deive.
With respect to claim 16, Moon et al discloses that the etch stop layer is made from SiCN (Para 70), and the second ILD layer is made from (silicon oxide, Para 71); however, the arts cited above do not explicitly disclose wherein the etching the second ILD and the etching-stop layer is performed using one or more etching processes in which the etching-stop layer is etched at a greater etching rate than the second ILD. On the other hand, It is known in the art than SiCN has a higher etching rate than silicon oxide specially in the dry etching process. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that silicon oxide is used for the silicon oxide and SICN is used for the etch stopper material, as a design choice.
With respect to claim 19, Hasegawa discloses that source or drain via is made from tungsten; and wherein the forming the source/drain via is performed using a selective metal growth process (Para 68).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Hsieh et al (US Pub No. 20180174904), in view of Song et al (US Pub No. 20160020148), in view of Hsu et al (US Pub No. 2017022008).
With respect to claim 17, the arts cited above do not explicitly disclose after the second via-hole has been formed but before the gate via is formed, forming a glue layer on side surfaces of the second via-hole and over the gate structure, wherein the gate via is formed over the glue layer. On the other hand, Song et al discloses after the second via-hole has been formed (Fig.17) but before the gate via is formed (Fig.21), forming a glue layer on side surfaces of the second via-hole and over the gate structure (132), wherein the gate via is formed over the glue layer (133). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Song et al such that glue layer on side surfaces of the second via-hole and over the gate structure, wherein the gate via is formed over the glue layer, in order to prevent the diffusion of the contact material into the gate structure, thereby improving the yield of the production of the transistors.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of Hsieh et al (US Pub No. 20180174904), in view of Leobundung (US Pub No. 20200006656), in view of Hsu et al (US Pub No. 2017022008).
With respect to claim 18, Hsieh et al discloses: after the forming the source/drain via (72,Fig.11), performing one or more semiconductor fabrication processes (para 24) using one or more chemicals that have corrosive properties (CMP uses chemical, this is accordance applicant’s specification); furthermore, Hasegawa discloses source/drain via is made from tungsten (para 47) and source or drain contact also is made from tungsten (Para 43); however, the arts cited above do not explicitly disclose wherein a material composition of the source/drain via is more resistant to the one or more chemicals than a material composition of the source/drain contact. Leobandung discloses that source or drain contact may be made from tungsten or cobalt (Para 32). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Leobandung et al such that instead of tungsten one would use cobalt, since they are better conductors than tungsten; furthermore, the combination of the arts above describe what applicant is describing in their specification meaning having cobalt as source contact and tungsten as source via and using processes such as CMP to level the source or drain via.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US Pub No. 20180277486), in view of Moon et al (US Pub No. 20140035164), in view of in view of Hsieh et al (US Pub No. 20180174904), in view of Zhu et al (US Pub No. 20160315248), in view of Hsu et al (US Pub No. 2017022008).
With respect to claim 20, the arts cited above do not explicitly disclose wherein the first via-hole and the second via-hole, are formed to be offset from each other in both a first lateral direction and a second lateral direction that is perpendicular to the first lateral direction. On the other hand, Zhu discloses wherein the first via-hole (V1 on the left,Fig.7) and the second via-hole (V1 on the right), are formed to be offset from each other in both a first lateral direction ( xdirection) and a second lateral direction that is perpendicular to the first lateral direction (y direction). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Zhu et al such that the first via-hole and the second via-hole, are formed to be offset from each other in both a first lateral direction and a second lateral direction that is perpendicular to the first lateral direction, in order to be able to connect the drain to a bit line so the device can be used for memory application for saving and processing data.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Furthermore, Hasegawa discloses the new limitation added to the claim 11, as has been shown above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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