DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: 1 through 4 and 23 through 24 rejected, 7 through 14 and 16 through 22 allowed
Present action: 1, 2, 4 and 23 through 25 rejected, 7 through 14 and 16 through 22 allowed
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Kim (US 2014/0213017)
Regarding claim 1.
Toh teaches:
A structure (fig 3:100[0033]) comprising: a first semiconductor material layer (fig 3:annotated[0033]), the first semiconductor material layer (fig 3:annotated[0033]) comprising a first set of through-vias (fig 3:annotated[0033,0034]), each of the first set of through-vias (fig 3:annotated[0033,0034]) having a width which expands wider from top to bottom;
a first redistribution structure (fig 3:annotated[0033,0034]) over a first side of the first semiconductor material layer (fig 3:annotated[0033]);
a first set of connectors (fig 3:annotated[0033]) extending from a surface of the first redistribution structure (fig 3:annotated[0033]);
a second set of connectors (fig 3:375[0033]) disposed under a second side of the first semiconductor material layer (fig 3:annotated[0033]);
a first semiconductor device (fig 3:annotated[0033]) coupled to the first set of connectors (fig 3:annotated[0033]);
an underfill (fig 3:annotated[0030,0033]) laterally surrounding the first set of connectors (fig 3:annotated[0033]), the underfill (fig 3:annotated[0030,0033]) being disposed between the first redistribution structure (fig 3:annotated[0033]) and the first semiconductor device (fig 3:annotated[0033]), wherein the underfill (fig 3:annotated[0030,0033]) has a width ;
an encapsulant (fig 3:190[0031]) laterally surrounding the first semiconductor device (fig 3:annotated[0033]);
a second redistribution structure (fig 3:180[0024,0033]) under and coupled to the second set of connectors;
a second set of through-vias (fig 3:176[0033]) in a second semiconductor material layer (fig 3:170[0024,0033]), the second set of through-vias (fig 3:176[0033]) having a width which expands wider from bottom to top;
and a third redistribution structure (fig 3:112[0018,0033]) coupled to the second redistribution structure (fig 3:180[0024,0033]) by the second set of through vias (fig 3:176[0033]), wherein the second set of through-vias (fig 3:176[0033]) extends from the second redistribution structure (fig 3:180[0024,0033]) to the third redistribution structure (fig 3:112[0018,0033]).
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Toh does not teach the underfill has a width which expands wider from top to bottom
Kim teaches:
a first semiconductor device (fig 12:150[0109]) coupled to the first set of connectors (fig 12:152[0111]);
an underfill (fig 12:154[0113]) laterally surrounding the first set of connectors (fig 12:152[0111]), the underfill (fig 12:154[0113])has a width which expands wider from top to bottom (fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the underfill to widen from top to bottom in order to accommodate different sized die and cover the top surface of the lower die with protective underfill material.
Regarding claim 4.
Toh in view of Kim teaches the structure of claim 1, further
Toh teaches:
a third set of connectors (fig 3:115[0017]) disposed on an underside of the third redistribution structure (fig 3:112[0018]);
and a device substrate (fig 3:annotated above) physically and electrically coupled to the third set of connectors (fig 3:115[0017]).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Kim (US 2014/0213017) as applied to claim 1, and further in view of Cheah (US 2019/0013301).
Regarding claim 2.
Toh in view of Kim teaches the structure of claim 1.
Toh in view of Kim does not teach one more additional semiconductor device.
Cheah teaches:
one or more additional semiconductor devices (fig 1:102d1; [para 0027]) coupled to the first set of connectors (fig 1:104; [para 0028]),
wherein the encapsulant (fig 1:111; [para 0028]) extends continuously between the first semiconductor device (fig 1:102c1; [para 0030])and the one or more additional semiconductor devices (fig 1:102d1; [para 0028]),
the encapsulant (fig 1:111; [para 0028]) having a first interface with a first sidewall of the first semiconductor device (fig 1:102c1; [para 0030]) and a second interface with a second sidewall of the one or more additional semiconductor devices (fig 1:102d1; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an additional semiconductor device coupled to the connectors in order to provide additional functionality to the packaged structure.
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Kim (US 2014/0213017) as applied to claim 1, and further in view of Min (US 2020/0294964)
Regarding claim 23.
Toh in view of Kim teaches the structure of claim 4, further:
Toh in view of Kim does not teach a fourth redistribution layer
Min teaches:
the device substrate (fig 1:30; [para 0034])comprises a fourth redistribution structure (fig 1:36; [para 0034]) having lateral extents greater than the first redistribution structure (fig 1:64; [para 0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device substrate to comprise a fourth redistribution layer in order to connect top and bottom connectors through the substrate.
Regarding claim 24.
Tou in view of Kim in view of Min teaches the structure of claim 23, further:
Min teaches:
device substrate (fig 1:30; [para 0034]) further comprises:
a fifth redistribution structure (fig 1:44; [para 0037]);
and a third semiconductor material layer (fig 1:30; [para 0037]) between the fourth redistribution structure (fig 1:36; [para 0034]) and the fifth redistribution structure (fig 1:44; [para 0037]),
the third semiconductor material layer (fig 1:30; [para 0037]) comprising a third set of through-vias (fig 1:35; [para 0034]) coupling the fifth redistribution structure (fig 1:44; [para 0037]) to the fourth redistribution structure (fig 1:36; [para 0034])
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Kim (US 2014/0213017) as applied to claim 1, and further in view of Min (US 2020/0294964)
Regarding claim 25.
Toh in view of Kim teaches the structure of claim 4, further:
Toh in view of Kim does not teach a fourth redistribution layer
Min teaches:
a fourth redistribution structure (fig 1:2[0031])under the second side of the first semiconductor material layer (fig 1:40[0037]), wherein the second set of connectors (fig 1:13[0030])extend from a surface of the fourth redistribution structure (fig 1:2[0031]) that is opposite to the first semiconductor material layer (fig 1:40[0037]),and wherein the first set of through-vias (fig 1:45[0037]) extends from the first redistribution structure (fig 1:36[0034]) to the fourth redistribution structure (fig 1:2[0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a fourth redistribution structure in order to provide bonding pads in the proper locations for further external mounting (paragraph 32)
Allowable Subject Matter
Claims 7 through 12, 14, and 16 through 22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7, the prior art does not teach a structure comprising: a first set of through-vias extending completely through a first semiconductor substrate, the first set of through-vias having a first tapered profile, the first tapered profile being narrower closer to the second redistribution structure and wider closer to the first redistribution structure; and a second set of through-vias extending through a second semiconductor substrate, the second semiconductor substrate interposed between the third redistribution structure and the fourth redistribution structure, the second set of through-vias having a second tapered profile that is opposite the first tapered profile of the first set of through-vias, wherein the underfill has a third taper profile that is opposite to the second tapered profile of the second set of through-vias in combination with the other elements of the claim.
Regarding claim 17, the prior art does not teach a structure comprising: a first through-via and a second through-via, each of the first through-via and second through-via extending completely through the semiconductor substrate each of the first through-via and second through-via having a first tapered profile, the first through-via being a longest through-via disposed in the semiconductor substrate, the second through-via being a shortest through-via disposed in the semiconductor substrate, a first set of connectors extending from a first surface of the first redistribution structure, the first surface opposite the semiconductor substrate; a first integrated circuit device attached to the second set of connectors; and an underfill having a second tapered profile opposite the first tapered profile in combination with other elements of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4, 23, 24 and 25 have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Toh (US 2010/0109142) in view of Kim (US 2014/0213017) as newly applied in the rejection of claim 1 above, anticipates the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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