DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and strike through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Audry (US 2014/0078704).
Regarding claim 1.
Toh teaches:
A structure comprising:
a first semiconductor material layer (fig 3:170; [para 0022]),
the first semiconductor material layer (fig 3:170; [para 0022]),comprising a first set of through-vias (fig 3:176; [para 0027]),
each of the first set of through-vias (fig 3:176; [para 0027]) having a width which expands wider from top to bottom;
a first redistribution structure (fig 3:180; [para 0024]) over a first side of the first semiconductor material layer (fig 3:170; [para 0022]);
a first set of connectors (fig 3:375; [para 0034]) extending from a surface of the first redistribution structure (fig 3:180; [para 0024]);
a second set of connectors (fig 3:115; [para 0034]) disposed under a second side of the first semiconductor material layer (fig 3:170; [para 0022]);
a first semiconductor device (fig 3:330; [para 0033]) coupled to the first set of connectors (fig 3:375; [para 0034]);
an underfill (fig 3:139; [para 0030]) laterally surrounding the first set of connectors (fig 3:375; [para 0034]),
the underfill (fig 3:139; [para 0030]) being disposed between the first redistribution structure (fig 3:180; [para 0024]) and the first semiconductor device (fig 3:330; [para 0033]),
wherein the underfill (fig 3:139; [para 0030]) has a width which expands wider from top to bottom;
an encapsulant (fig 3:139; [para 0030]) laterally surrounding the first semiconductor device (fig 3:330; [para 0033]);
a second redistribution structure (fig 3 annotated: ; [para 0033]) coupled to the second set of connectors (fig 3:115; [para 0034]);
a second set of through-vias (fig 3:376; [para 0034]) in a second semiconductor material layer (fig 3:330; [para 0033]),
the second set of through-vias (fig 3:376; [para 0034])having a width;
and a third redistribution structure (fig 3:380; [para 0033]) coupled to the second redistribution structure (fig 3 annotated: ; [para 0033])by the second set of through vias (fig 3:376; [para 0034]).
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Toh does not teach the second set of through-vias having a width which expands wider from bottom to top
Audry teaches:
a second set of through-vias (fig 1:106; [para 0022]) having a width which expands wider from bottom to top
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to minimize capacitive coupling lower in the via while providing a larger contact surface above for subsequent stacking
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Audry (US 2014/0078704) as applied to claim 1, and further in view of Cheah (US 2019/0013301).
Regarding claim 2.
Toh in view of Audry teaches the structure of claim 1.
Toh in view of Audry does not teach one more additional semiconductor device.
Cheah teaches:
one or more additional semiconductor devices (fig 1:102d1; [para 0027]) coupled to the first set of connectors (fig 1:104; [para 0028]),
wherein the encapsulant (fig 1:111; [para 0028]) extends continuously between the first semiconductor device (fig 1:102c1; [para 0030])and the one or more additional semiconductor devices (fig 1:102d1; [para 0028]),
the encapsulant (fig 1:111; [para 0028]) having a first interface with a first sidewall of the first semiconductor device (fig 1:102c1; [para 0030]) and a second interface with a second sidewall of the one or more additional semiconductor devices (fig 1:102d1; [para 0028]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an additional semiconductor device coupled to the connectors in order to provide additional functionality to the packaged structure.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Audry (US 2014/0078704) as applied to claim 1, and further in view of Yu (US 2015/0318263).
Regarding claim 3.
Toh in view of Audry teaches the structure of claim 1.
Toh in view of Audry does not teach a third set of connectors disposed on an underside of the third redistribution structure
Yu teaches:
a third set of connectors (fig 34:3408; [para 0075])disposed on an underside of the third redistribution structure (fig 34:3402; [para 0072])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a third set of connectors in order to facilitate subsequent connections to additional structures enabling improved performance (paragraph 0004)
Regarding claim 4.
Toh in view of Audry in view of Yu teaches the structure of claim 3, further:
Yu teaches
a device substrate (fig 35:3502; [para 0075]) physically and electrically coupled to the third set of connectors (fig 34:3408; [para 0075]).
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh (US 2010/0109142) in view of Audry (US 2014/0078704) in view of Yu (US 2015/0318263) as applied to claim 4, and further in view of Min (US 2020/0294964).
Regarding claim 23.
Toh in view of Audry in view of Yu teaches the structure of claim 4, further:
Toh in view of Audry in view of Yu does not teach a fourth redistribution layer
Min teaches:
the device substrate (fig 1:30; [para 0034])comprises a fourth redistribution structure (fig 1:36; [para 0034]) having lateral extents greater than the first redistribution structure (fig 1:64; [para 0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device substrate to comprise a fourth redistribution layer in order to connect top and bottom connectors through the substrate.
Regarding claim 24.
Tou in view of Audry in view of Yu in view of Min teaches the structure of claim 23, further:
Min teaches:
device substrate (fig 1:30; [para 0034]) further comprises:
a fifth redistribution structure (fig 1:44; [para 0037]);
and a third semiconductor material layer (fig 1:30; [para 0037]) between the fourth redistribution structure (fig 1:36; [para 0034]) and the fifth redistribution structure (fig 1:44; [para 0037]),
the third semiconductor material layer (fig 1:30; [para 0037]) comprising a third set of through-vias (fig 1:35; [para 0034]) coupling the fifth redistribution structure (fig 1:44; [para 0037]) to the fourth redistribution structure (fig 1:36; [para 0034])
Response to Arguments
Applicant’s arguments with respect to claim(s) s 1 through 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 7 through 12, 14, and 16 through 22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7, the prior art does not teach a structure comprising: a first set of through-vias extending completely through a first semiconductor substrate, the first set of through-vias having a first tapered profile, the first tapered profile being narrower closer to the second redistribution structure and wider closer to the first redistribution structure; and a second set of through-vias extending through a second semiconductor substrate, the second semiconductor substrate interposed between the third redistribution structure and the fourth redistribution structure, the second set of through-vias having a second tapered profile that is opposite the first tapered profile of the first set of through-vias, wherein the underfill has a third taper profile that is opposite to the second tapered profile of the second set of through-vias in combination with the other elements of the claim.
Regarding claim 17, the prior art does not teach a structure comprising: a first through-via and a second through-via, each of the first through-via and second through-via extending completely through the semiconductor substrate each of the first through-via and second through-via having a first tapered profile, the first through-via being a longest through-via disposed in the semiconductor substrate, the second through-via being a shortest through-via disposed in the semiconductor substrate, a first set of connectors extending from a first surface of the first redistribution structure, the first surface opposite the semiconductor substrate; a first integrated circuit device attached to the second set of connectors; and an underfill having a second tapered profile opposite the first tapered profile in combination with other elements of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 6, 2026
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