DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 01/16/2026, with respect to the rejection(s) of claim(s) 1-17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (CN-110517993-A – hereinafter Lin).
Regarding claim 1, Lin teaches a semiconductor package (Fig.16; ¶0076), comprising:
an interposer substrate (Fig.16 5; ¶0091);
a plurality of semiconductor dies (Fig.16 3; ¶0079) disposed on the interposer substrate (5);
a first encapsulant (Fig.16 4; ¶0084) disposed on the interposer substrate (5) and surrounding the plurality of semiconductor dies (3);
a backside metal layer (Fig.16 2, this layer can be interpreted as a metal layer because it comprises alumina; ¶0130) disposed on the first encapsulant (4) and the plurality of semiconductor dies (3);
at least one heat dissipation element (Fig.16 12; ¶0077) disposed on the backside metal layer (2);
and a second encapsulant (Fig.16 11; ¶0077) disposed on the backside metal layer (2) and laterally surrounding the at least one heat dissipation element (12),
wherein the backside metal layer (2) is in contact with the first encapsulant (4) and the second encapsulant (11).
Regarding claim 2, Lin teaches the semiconductor package according to claim 1, wherein the second encapsulant (11) overlaps the first encapsulant (4), and the second encapsulant (11) is spaced apart from the first encapsulant (4) by the backside metal layer (2).
Regarding claim 3, Lin teaches the semiconductor package according to claim 1, wherein the number of the at least one heat dissipation element (12) is one or more, and each heat dissipation element (12) covers one or more semiconductor dies (3) among the plurality of semiconductor dies (3).
Regarding claim 4, Lin teaches the semiconductor package according to claim 1, wherein rear surfaces (top surfaces) of the plurality of semiconductor dies (3) and a top surface of the first encapsulant (4) together form a plane on which the backside metal layer (2) is disposed.
Regarding claim 5, Lin teaches the semiconductor package according to claim 1, wherein a material of the at least one heat dissipation element (12) comprises metal, metal alloy or a combination thereof (¶0085).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Regarding claim 12, Lin teaches the semiconductor package according to claim 1.
Lin does not teach wherein a thickness of the at least one heat dissipation element is 50μm to 500μm.
However, it would have been obvious to form the thickness of the at least one heat dissipation element within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chu et al. (US-20080135994-A1 – hereinafter Chu).
Regarding claim 6, Lin teaches the semiconductor package according to claim 5.
Lin does not teach the semiconductor package further comprising:
a solder layer disposed between the backside metal layer and the at least one heat dissipation element.
Chu teaches a multi-layer conductive die-attach film (Fig.6 63; ¶0032 of Chu) comprising a conductive epoxy (Fig.6 78; ¶0032 of Chu) and a metal layer (Fig.6 76; ¶0032 of Chu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the composite die attach layer of Chu (63 of Chu) to be combined with the backside metal layer of Lin (2 of Lin) to arrive at the claimed invention. The existing layer of Lin (2 of Lin) is a conductive epoxy and the metal layer of Chu (76 of Chu) can be disposed on top. A practitioner would have been motivated to make this modification for the benefit of providing a low resistance conductive connection between the dies (3 of Lin) and the heat dissipation element (12 of Lin).
Regarding claim 7, the aforementioned combination of Lin in view of Chu from claim 6 teaches the semiconductor package according to claim 6, wherein the backside metal layer (2 of Lin) is in contact with the plurality of semiconductor dies (3 of Lin) and the first encapsulant (4 of Lin).
Regarding claim 8, the aforementioned combination of Lin in view of Chu from claim 6 teaches the semiconductor package according to claim 6, wherein the backside metal layer (2 of Lin) covers the plurality of semiconductor dies (3 of Lin) and the first encapsulant (4 of Lin).
Regarding claim 9, the aforementioned combination of Lin in view of Chu from claim 6 teaches the semiconductor package according to claim 6, wherein an orthogonal projection of the at least one heat dissipation element (12 of Lin) on the interposer substrate (5 of Lin) is smaller than an orthogonal projection of the backside metal layer (2 of Lin) on the interposer substrate (5 of Lin).
Regarding claim 10, the aforementioned combination of Lin in view of Chu from claim 9 teaches the semiconductor package according to claim 9, wherein an area of the solder layer (76 of Chu) is equal to the area of the at least one heat dissipation element (12 of Lin).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zhou et al. (US-20230238300-A1 – hereinafter Zhou).
Regarding claim 11, Lin teaches the semiconductor package according to claim 1.
Lin does not teach wherein a top surface of the at least one heat dissipation element is level with a top surface of the second encapsulant.
Zhou teaches a semiconductor device (Fig.1 100; ¶0022 of Zhou) comprising a heat sink (Fig.1 112; ¶0022 of Zhou) and an encapsulant (Fig.1 140; ¶0022 of Zhou) where the top surfaces of the heat sink (112 of Zhou) and encapsulant (140 of Zhou) are level.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to grind down the second encapsulant of Lin (11 of Lin) to be coplanar with the top surface of the heat dissipation element of Lin (12 of Lin) as taught by Zhou (Fig.1 of Zhou) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of improved heat dissipation off the heat dissipation element (12 of Lin) due to excess insulating encapsulant (11 of Lin) being removed.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Huang. (US-20200365486-A1).
Regarding claim 13, Lin teaches a semiconductor package (Fig.16; ¶0076), comprising:
an interposer substrate (Fig.16 5; ¶0091);
a plurality of semiconductor dies (Fig.16 3; ¶0079) disposed on the interposer substrate (5);
a first encapsulant (Fig.16 4; ¶0084) disposed on the interposer substrate (5) and surrounding the plurality of semiconductor dies (3);
a backside metal layer (Fig.16 2; ¶0130) disposed on the first encapsulant (4) and the plurality of semiconductor dies (3);
at least one metal bulk (Fig.16 12; ¶0077) disposed on the backside metal layer (2); and
a second encapsulant (Fig.16 11; ¶0077) disposed on the backside metal layer (2) and laterally surrounding the at least one metal bulk (12),
wherein the backside metal layer (2) is sandwiched between the first encapsulant (4) and the second encapsulant (11) and is in contact with the first encapsulant (4) and the second encapsulant (11).
Lin does not teach wherein an outer edge of the second encapsulant is aligned with an outer edge of the first encapsulant.
Huang teaches a semiconductor package (Fig.3 of Huang) that is filly aligned vertically at the top of the semiconductor package.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch the backside metal layer (2 of Lin) and the second encapsulant (11 of Lin) to be vertically flush with the rest of the package taught by Lin (Fig.16 of Lin) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of the package having a smaller vertical footprint and removing excess dielectric.
Regarding claim 14, the aforementioned combination of Lin in view of Huang from claim 13 teaches the semiconductor package according to claim 13, wherein rear surfaces (top surfaces) of the plurality of semiconductor dies (3) and a top surface of the first encapsulant (4) together form a plane on which the backside metal layer (2) is disposed.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Huang, and further in view of Zhou.
Regarding claim 15, the aforementioned combination of Lin in view of Huang from claim 13 teaches the semiconductor package according to claim 13.
The aforementioned combination does not teach wherein a top surface of the at least one metal bulk is level with a top surface of the second encapsulant.
Zhou teaches a semiconductor device (Fig.1 100; ¶0022 of Zhou) comprising a heat sink (Fig.1 112; ¶0022 of Zhou) and an encapsulant (Fig.1 140; ¶0022 of Zhou) where the top surfaces of the heat sink (112 of Zhou) and encapsulant (140 of Zhou) are level.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to grind down the second encapsulant of Lin (11 of Lin) to be coplanar with the top surface of the heat dissipation element of Lin (12 of Lin) as taught by Zhou (Fig.1 of Zhou) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of improved heat dissipation off the heat dissipation element (12 of Lin) due to excess insulating encapsulant (11 of Lin) being removed.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Huang, and further in view of Chu.
Regarding claim 16, the aforementioned combination of Lin in view of Huang from claim 13 teaches the semiconductor package according to claim 13.
The aforementioned combination does not teach the semiconductor device further comprising:
a solder layer disposed between the backside metal layer and the at least one metal bulk.
Chu teaches a multi-layer conductive die-attach film (Fig.6 63; ¶0032 of Chu) comprising a conductive epoxy (Fig.6 78; ¶0032 of Chu) and a metal layer (Fig.6 76; ¶0032 of Chu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the composite die attach layer of Chu (63 of Chu) to be combined with the backside metal layer of Lin (2 of Lin) to arrive at the claimed invention. The existing layer of Lin (2 of Lin) is a conductive epoxy and the metal layer of Chu (76 of Chu) can be disposed on top. A practitioner would have been motivated to make this modification for the benefit of providing a low resistance conductive connection between the dies (3 of Lin) and the metal bulk (12 of Lin).
Regarding claim 17, the aforementioned combination of Lin in view of Huang, and further in view of Chu from claim 16 teaches the semiconductor package according to claim 16, wherein an edge of the backside metal layer (2 of Lin) is vertically aligned with the outer edge of the second encapsulant (11 of Lin) and the outer edge of the first encapsulant (4 of Lin) (the existing modification in view of Huang from claim 13 already covers this limitation).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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