DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 08/25/2026, with respect to the rejection(s) of claim(s) 1-17 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Package with Backside Metal Layer and Heat Dissipation Element.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (CN-110517993-A – hereinafter Lin) in view of Tang et al. (US-20220384306-A1 – hereinafter Tang).
Regarding claim 1, Lin teaches a semiconductor package (Fig.16; ¶0076), comprising:
an interposer substrate (Fig.16 5; ¶0091);
a plurality of semiconductor dies (Fig.16 3; ¶0079) disposed on the interposer substrate (5);
a first encapsulant (Fig.16 4; ¶0084) disposed on the interposer substrate (5) and surrounding the plurality of semiconductor dies (3);
a backside metal layer (Fig.16 2, this layer can be interpreted as a metal layer because it comprises alumina; ¶0130) disposed on the first encapsulant (4) and the plurality of semiconductor dies (3);
at least one heat dissipation element (Fig.16 12; ¶0077) disposed on the backside metal layer (2);
a second encapsulant (Fig.16 11; ¶0077) disposed on the backside metal layer (2) and laterally surrounding the at least one heat dissipation element (12),
wherein the backside metal layer (2) is in contact with the first encapsulant (4) and the second encapsulant (11).
Lin does not teach a solder layer disposed between the backside metal layer and the at least one heat dissipation element and laterally surrounded by the second encapsulant.
Tang teaches a thermal interface structure (Fig.1 200; ¶0043 of Tang) comprising a backside metal layer (Fig.1 212; ¶0043 of Tang), a heat dissipation element (Fig.1 260; ¶0043 of Tang), a second encapsulant (Fig.1 230; ¶0043 of Tang) laterally surrounding the heat dissipation element (260 of Tang) and a solder layer (Fig.1 242; ¶0043 of Tang), disposed between the backside metal layer (212 of Tang) and the heat dissipation element (260 of Tang) while laterally surrounded by the second encapsulant (230 of Tang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the heat dissipation components of Lin (2, 11 and 12 of Lin) for the heat dissipation components of Tang (212, 260, 230 and 242 of Tang) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of absorbing stresses in the integrated circuit assembly or package caused by differing thermal expansions between the components (¶0004 of Tang).
Regarding claim 2, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein the second encapsulant (230 of Tang) overlaps the first encapsulant (4 of Lin), and the second encapsulant (230 of Tang) is spaced apart from the first encapsulant by the backside metal layer (212 of Tang).
Regarding claim 3, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein the number of the at least one heat dissipation element (260 of Tang) is one or more, and each heat dissipation element (260 of Tang) covers one or more semiconductor dies (3 of Lin) among the plurality of semiconductor dies (3 of Lin).
Regarding claim 4, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein rear surfaces (top surfaces) of the plurality of semiconductor dies (3 of Lin) and a top surface of the first encapsulant (4 of Lin) together form a plane on which the backside metal layer (212 of Tang) is disposed.
Regarding claim 5, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein a material of the at least one heat dissipation element (260 of Tang) comprises metal, metal alloy or a combination thereof (¶0047 of Tang).
Regarding claim 6, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 5, wherein the solder layer (242 of Tang) is separated from the first encapsulant (4 of Lin) by the backside metal layer (212 of Tang).
Regarding claim 7, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein the backside metal layer (212 of Tang) interfaces with the plurality of semiconductor dies (3 of Lin) and the first encapsulant (4 of Lin).
Regarding claim 8, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein the backside metal layer (212 of Tang) covers the plurality of semiconductor dies (3 of Lin) and the first encapsulant (4 of Lin).
Regarding claim 9, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein an orthogonal projection of the at least one heat dissipation element (260 of Tang) on the interposer substrate (5 of Lin) is smaller than an orthogonal projection of the backside metal layer (212 of Tang) on the interposer substrate (5 of Lin).
Regarding claim 10, the combination of Lin in view of Tang from claim 9 teaches the semiconductor package according to claim 9, wherein an entire area of the solder layer (242 of Tang) is equal to an entire area of the at least one heat dissipation element (260 of Tang).
Regarding claim 11, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein a top surface of the at least one heat dissipation element (260 of Tang) is level (see Fig.14 of Tang) with a top surface of the second encapsulant (230 of Tang).
Regarding claim 12, the combination of Lin in view of Tang from claim 1 teaches the semiconductor package according to claim 1, wherein a thickness of the at least one heat dissipation element is 50μm to 500μm (¶0047 of Tang).
Claim(s) 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Huang (US-20200365486-A1), and further in view of Tang.
Regarding claim 13, Lin teaches a semiconductor package (Fig.16; ¶0076), comprising:
an interposer substrate (Fig.16 5; ¶0091);
a plurality of semiconductor dies (Fig.16 3; ¶0079) disposed on the interposer substrate (5);
a first encapsulant (Fig.16 4; ¶0084) disposed on the interposer substrate (5) and surrounding the plurality of semiconductor dies (3);
a backside metal layer (Fig.16 2; ¶0130) disposed on the first encapsulant (4) and the plurality of semiconductor dies (3);
at least one metal bulk (Fig.16 12; ¶0077) disposed on the backside metal layer (2);
a second encapsulant (Fig.16 11; ¶0077) disposed on the backside metal layer (2) and laterally surrounding the at least one metal bulk (12),
wherein the backside metal layer (2) is sandwiched between the first encapsulant (4) and the second encapsulant (11) and is in contact with the first encapsulant (4) and the second encapsulant (11).
Lin does not teach wherein an outer edge of the second encapsulant is aligned with an outer edge of the first encapsulant.
Huang teaches a semiconductor package (Fig.3 of Huang) that is fully aligned vertically at the top of the semiconductor package.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch the backside metal layer (2 of Lin) and the second encapsulant (11 of Lin) to be vertically flush with the rest of the package taught by Lin (Fig.16 of Lin) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of the package having a smaller vertical footprint and removing excess dielectric.
Lin in view of Huang does not teach a solder layer disposed between the backside metal layer and the at least one metal bulk and laterally surrounded by the second encapsulant.
Tang teaches a thermal interface structure (Fig.1 200; ¶0043 of Tang) comprising a backside metal layer (Fig.1 212; ¶0043 of Tang), a heat dissipation element (Fig.1 260; ¶0043 of Tang), a second encapsulant (Fig.1 230; ¶0043 of Tang) laterally surrounding the heat dissipation element (260 of Tang) and a solder layer (Fig.1 242; ¶0043 of Tang), disposed between the backside metal layer (212 of Tang) and the heat dissipation element (260 of Tang) while laterally surrounded by the second encapsulant (230 of Tang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the heat dissipation components of Lin (2, 11 and 12 of Lin) for the heat dissipation components of Tang (212, 260, 230 and 242 of Tang) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of absorbing stresses in the integrated circuit assembly or package caused by differing thermal expansions between the components (¶0004 of Tang).
Regarding claim 14, the combination of Lin in view of Huang, and further in view of Tang from claim 13 teaches the semiconductor package according to claim 13, wherein rear surfaces (top surfaces) of the plurality of semiconductor dies (3 of Lin) and a top surface of the first encapsulant (4 of Lin) together form a plane on which the backside metal layer (212 of Tang) is disposed.
Regarding claim 15, the combination of Lin in view of Huang, and further in view of Tang from claim 13 teaches the semiconductor package according to claim 13, wherein a top surface of the at least one metal bulk (260 of Tang) is level (see Fig.14 of Tang) with a top surface of the second encapsulant (230 of Tang).
Regarding claim 16, the combination of Lin in view of Huang, and further in view of Tang from claim 13 teaches the semiconductor package according to claim 13, wherein the solder layer (242 of Tang) is separated from the first encapsulant (4 of Lin) by the backside metal layer (212 of Tang).
Regarding claim 17, the combination of Lin in view of Huang, and further in view of Tang from claim 13 teaches the semiconductor package according to claim 13, wherein an edge of the backside metal layer (212 of Tang) is vertically aligned (the existing modification in view of Huang from claim 13 already covers this limitation) with the outer edge of the second encapsulant (230 of Tang) and the outer edge of the first encapsulant (4 of Lin).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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