Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et. Al. (US 20220052168 A1 hereinafter Chang) and further in view of Bohr et. Al. (US 20170004998 A1 hereinafter Bohr).
Regarding claim 1, Chang teaches in Figs. 18-19 with associated text a semiconductor device, comprising: a source region 205-2 and a drain region 205-1 over a substrate 202 (Figs. 18-19, [0020]); a first source contact 2200 disposed on the source region and extending along a first direction (Y-direction or Z-direction) (the source contact is a three dimensional structure and therefore extends all direction including the first directions Fig. 18, [0020]); a first drain contact 220 disposed on the drain region and extending along the first direction ((the drain contact is a three dimensional structure and therefore extends in all directions Fig. 19, [0020]); a first gate structure (206 on the left of 205-2) and a second gate structure (206 on the left of 205-2) located on two sides of the first source contact and respectively extending along the first direction; a first drain via 230 connected to the first drain contact, wherein the first drain via includes a barrier-less body portion 230 (230 is formed by a metal deposition process [0023] without a barrier in the final structure Figs. 5-12 [0023]); and a first source via 248 connected to the first source contact, wherein the first source via includes a body portion 246 and a barrier layer 244 surrounding the body portion, and a size of the first source via is greater than a size of the first drain via (width is greater Fig. 18-19, [0027]-[0028]) , and wherein the first source via is extending along a second direction (X-direction) perpendicular to the first direction and is overlapped with the first gate structure (Fig. 18)
Chang does not specify the first source via is overlapped with the second gate structure however Chang discloses the first source via extends from the first source contact towards the second gate structure (Fig. 18).
Bohr teaches in Fig. 3F a device similar to that of Chang wherein a first source via 340 is overlapped with a first gate structure 308D and a second gate structure however Chang discloses the first source via extends from the first source contact towards the second gate structure (Fig. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first source via of Chang to be overlapped with the second gate structure as taught by Bohr because according to Bohr such a structure is suitable for such a source via [0059], It would have been obvious to one of ordinary skill in the art, in view of the teachings of Chang and Bohr, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use a source via overlapped with the second gate structure with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S, 82 USPQ2d 1385 (2007)..
Regarding claim 2, Chang teaches a ratio of a top surface area of the first drain via to a top surface area of the first source via is in a range of 1:1.1 to 1:50.
Regarding claim 3, Chang teaches the first drain contact and the first source contact are extending in a first direction, and a width of the first source via in the first direction is greater than a width of the first drain via in the first direction (Figs. 18-19).
Regarding claim 4, Chang teaches sidewalls of the first source via extends beyond sidewalls of the first source contact (Fig. 18).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Bohr as applied to claim 1 and further in view of Cho et. Al. (US 20180366463 A1 hereinafter Cho).
Regarding claim 7, Chang teaches in Figs. 21-22 with associated text the semiconductor device according to claim 1.
Chang does not specify a first metal line disposed on and connected to the first drain via; and a second metal line disposed on and connected to first source via, wherein a width of the second metal line is greater than a width of the first metal line.
Cho discloses in Fig. 4 with associated text a first metal line PL2 disposed on and connected to a first drain via VP2 (Fig. 2, [0052]); and a second metal line CP disposed on and connected to a first source via VP1 similar to that of Chang (Fig. 2, [0049]), wherein a width of the second metal line is greater than a width of the first metal line (full width of CP in D2 direction is greater than the width of PL2 in the D2 direction Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use first and second metal lines similar to those of Cho in the device of Chang because according to Cho such a structure may be provided thereon to form a plurality of standard cells SC [0023] which may be used for a basic cell (e.g., an AND gate, an OR gate, a NOR, or an inverter), a complex cell (e.g., OAI (OR/AND/Inverter) gates and AOI (AND/OR/Inverter) gates), or a storage element (e.g., a master-slave flip-flop and a latch) [0020].
Claim(s) 8-11 and 13 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Wang et. Al. (US 20220223517 A1 hereinafter Wang) and further in view of Cho et. Al. (US 20180366463 A1 hereinafter Cho).
Regarding claim 8, Wang teaches in Figs. 21-22 with associated text a semiconductor device, comprising: a gate structure 228c located on a substrate and extending in a first direction (y-direction) (Fig. 21, [0025]; a first source contact 250b and a first drain contact (see annotated figure below) located on a first side of the gate structure and extending in the first direction wherein the first source contact has a first inner sidewall facing the first side of the gate structure and a first outer sidewall facing away from the gate structure, wherein the second source contact has a second inner sidewall facing the second side of the gate structure and a second outer sidewall facing away from the gate structure (see annotated figure below, [0039]); a second source contact 250c and a second drain contact (see annotated Fig. below , [0039]), located on a second side of the gate structure and extending in the first direction; a first drain via connected to the first drain contact (see annotated Fig. below , [0039]); a second drain via connected to the second drain contact (see annotated Fig. below , [0039]); and a first shared source via 262 connected to and extending from the first source contact to the second source contact (Figs. 21-22, [0039]), wherein the first shared source via extends from a position beyond the first outer sidewall (Fig. 21) of the first source contact, and extends continuously across the first inner sidewall, and the gate structure (Fig. 21).
Wang does not specify the first shared source via the second inner sidewall, and extends beyond the second outer sidewall of the second source contact as the first shared source via has a smaller width than the second source contact.
Cho discloses in Figs. 4-5 with associated text a device similar to that of Wang wherein a first shared source via VP1 is wider than a source contact so that by making the first shared source via of Wang wider than the second source contact as taught by Cho first shared source via would extend beyond the second inner sidewall, and extends beyond the second outer sidewall of the second source contact.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first shared source via of Wang wider than the second source contact as taught by Cho because according to Cho such a structure may be provided thereon to form a plurality of standard cells SC [0023] which may be used for a basic cell (e.g., an AND gate, an OR gate, a NOR, or an inverter), a complex cell (e.g., OAI (OR/AND/Inverter) gates and AOI (AND/OR/Inverter) gates), or a storage element (e.g., a master-slave flip-flop and a latch) [0020].
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Regarding claim 9, Wang teaches a ratio of a top surface area of the first drain via to a top surface area of the first shared source via is in a range of 1:1.1 to 1:50 (areas shown in Fig. 21 are well within the claimed range).
Regarding claim 10, Wang teaches the first shared source via is extending in a second direction perpendicular to the first direction from the first source contact to the second source contact, and the first shared source via extends over the gate structure (Figs. 21-22).
Regarding claim 11, Wang teaches from a top view of the semiconductor device, the first shared source via has a first quadrilateral-shaped portion overlapped with the first source contact, and a second quadrilateral-shaped portion joined with the first quadrilateral-shaped portion and overlapped with the second source contact, and sidewalls of the first quadrilateral-shaped portion are misaligned with sidewalls of the second quadrilateral-shaped portion (see annotated figure above).
Regarding claim 13, Wang teaches a source contact surface area of the first shared source via to the first source contact and the second source contact, is greater than a sum of the drain contact surface areas of the first drain via to first drain contact and the second drain via to the second drain contact (Fig. 22).
Regarding claim 15, Wang in view of Cho teaches the semiconductor device according to claim 1.
Wang does not specify a first metal line disposed on and connected to the first drain via; and a second metal line disposed on and connected to first source via, wherein a width of the second metal line is greater than a width of the first metal line.
Cho discloses in Fig. 4 with associated text a first metal line PL2 disposed on and connected to a first drain via VP2 (Fig. 2, [0052]); and a second metal line CP disposed on and connected to a first source via VP1 similar to that of Wang (Fig. 2, [0049]), wherein a width of the second metal line is greater than a width of the first metal line (full width of CP in D2 direction is greater than the width of PL2 in the D2 direction Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use first and second metal lines similar to those of Cho in the device of Wang because according to Cho such a structure may be provided thereon to form a plurality of standard cells SC [0023] which may be used for a basic cell (e.g., an AND gate, an OR gate, a NOR, or an inverter), a complex cell (e.g., OAI (OR/AND/Inverter) gates and AOI (AND/OR/Inverter) gates), or a storage element (e.g., a master-slave flip-flop and a latch) [0020].
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cho as applied to claim 8 and further in view of Liaw et. Al. (US 20110222332 A1 hereinaftewr Liaw ).
Regarding claim 14, Wang in view of Cho teaches the semiconductor device according to claim 8 further comprising a second gate 228c located aside the second source contact and the second drain contact and extending in the first direction (Fig. 21); and a third source contact 228d located aside the second gate, wherein the second gate is located in between the third source contact and the second source contact (Fig. 21).
Wang does not specify the first shared source via is connected to and further extends towards the third source contact.
Liaw discloses in Figs. 9 with associated text first shared source line Vss ([0023]) similar to the first shared source via of Wang is connected to a first and second source contact (contacts for 148 and 152 for example) (Figs. 3 and 9 [0018] and [0019]) and is connected further extends towards a third source contact 170 (Figs. 3 and 9, [0019] and [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the first shared source via of Wang to be connected to and further extends towards the third source contact as taught by Liaw because according to Liaw the Vss connections (152 and 154) and various landing pads (156, 158, . . . , 172 and 174) are formed by the local interconnect as well, in one embodiment. Other proper local interconnect technology may be utilized for the above routing [0021].
Allowable Subject Matter
Claims 5-6 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
After completing a thorough search of dependent claim 5, the prior art of record, alone or in combination does not disclose, teach or fairly suggest a semiconductor device, comprising: a first drain via connected to the first drain contact, wherein the first drain via includes a barrier-less body portion; and a first source via connected to the first source contact, wherein the first source via includes a body portion and a barrier layer surrounding the body portion, and a size of the first source via is greater than a size of the first drain via, and a second source contact located aside the first source contact, wherein the first source via extends from the first source contact towards the second source contact, and is electrically connected to the second source contact and wherein the first source via is extending along a second direction perpendicular to the first direction and is overlapped with the first gate structure and the second gate structure in combination with the rest of the limitations of the claim.
After completing a thorough search of dependent claim 12, the prior art of record, alone or in combination does not disclose, teach or fairly suggest a semiconductor device, comprising: a first drain via connected to the first drain contact; a second drain via connected to the second drain contact; and a first shared source via connected to and extending from the first source contact to the second source contact, wherein the first shared source via extends from a position beyond the first outer sidewall of the first source contact, and extends continuously across the first inner sidewall, the gate structure, the second inner sidewall, and extends beyond the second outer sidewall of the second source contact, wherein the first shared source via includes a body portion and a barrier layer surrounding the body portion, and the first drain via and the second drain via respectively includes a barrier- less body portion in combination with the rest of the limitations of the claim.
Claim 6 is also allowed being dependent on allowable claim 5.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897