Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed November 7th, 2025, have been fully considered but they are not persuasive.
Applicant argues (pgs. 10-11, “Remarks”) that Lee doesn’t teach the limitations of amended Claim 1.
However, as seen below, Claim 1 is now rejected by the combination of Lee, Liu, and Katagiri.
Therefore, applicant’s arguments are not persuasive and moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1-5, 8, 25, and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2008/0081459 A1; hereinafter Lee) in view of Liu et al. (2020/0176397 A1; hereinafter Liu) and Katagiri et al. (2016/0027754 A1; hereinafter Katagiri).
Regarding Claim 1, Lee (annotated fig. 7) teaches:
A chip structure (see annotated fig. 7), comprising: a substrate ([0017], 105);
a conductive line ([0017], 120) over the substrate (105);
a first passivation layer ([0017], 125) over the substrate (105) and the conductive line (120);
a conductive pad ([0017], 135) over the first passivation layer (125) covering the conductive line (120), wherein the conductive pad (135) is thicker and wider (see annotated fig. 7) than the conductive line (120);
a first conductive via structure ([0017], 130) and a second conductive via structure passing through the first passivation layer (125) and directly connected between the conductive pad (135) and the conductive line (120);
a conductive pillar ([0029], 165) over the conductive pad (135); and
a second passivation layer ([0022], 140) conformally covering the first passivation layer (125) and the conductive pad (135), wherein the conductive pillar (165) is over the second passivation layer (140) and has a protruding bottom portion ([0029], 170) passing through the second passivation layer (140),
the second passivation layer (140) conformally covers a first top surface (top of 135) and a first sidewall (sidewalls of 135) of the conductive pad (135) and a second top surface (top of 125) of the first passivation layer (125), and
the conductive pillar (165) comprises a seed layer ([0029], 160) conformally covering (160 indirectly covers the top of 140) a first convex curved top surface (top of 140) of the second passivation layer (140) over the conductive pad (135),
the conductive pillar (165) has a lower surface (lower surface, see annotated fig. 7) and a second sidewall (second sidewall, see annotated fig. 7) connected to the lower surface (lower surface), and an angle between the second sidewall and the lower surface is less than 90 degrees.
Lee doesn’t explicitly teach a second conductive via structure passing through the first passivation layer.
However, Liu (annotated fig. 15) teaches a first conductive via structure ([0046], left 138A, see annotated fig. 15) and a second conductive via structure (right 138A, see annotated fig. 15) passing through the first passivation layer ([0032], 136). Liu also teaches that additional vias may help buffer mechanical stresses ([0051]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the chip structure of Lee to include the multiple conductive vias of Liu to buffer mechanical stress.
Lee doesn’t explicitly teach an angle between the second sidewall and the lower surface is less than 90 degrees.
However, Katagiri (fig. 10) teaches an angle between the second sidewall ([0055], 112b) and the lower surface (bottom surface of 112) is less than 90 degrees ([0055], forms an acute angle, see fig. 10). Katagiri teaches this helps prevent solder from wrapping around onto the sidewall of the pillar ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the chip structure of Lee to include acutely angled conductive pillar of Katagiri to help prevent solder spillover.
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Annotated Figure 7
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Annotated Figure 15
Regarding Claim 2, Liu (annotated fig. 15) teaches the chip structure as claimed in claim 1, wherein the first conductive via structure (left 138A) and a center portion (center portion, see annotated fig. 15) of the conductive pad ([0047], 138B) are misaligned (left 138A is left of center portion) in a direction perpendicular (up and down in annotated fig. 15) to a top surface of the substrate ([0021], top of 102, see fig. 2).
Regarding Claim 3, Liu (annotated fig. 15) teaches the chip structure as claimed in claim 2, wherein the second conductive via structure (right 138A) and the center portion (center portion) of the conductive pad (138B) are misaligned (right 138A is right of center portion) in the direction perpendicular (up and down) to the top surface of the substrate (top of 102).
Regarding Claim 4, Liu (annotated fig. 15) teaches the chip structure as claimed in claim 3, wherein the center portion (center portion) is between the first conductive via structure (left 138A) and the second conductive via structure (right 138A).
Regarding Claim 5, Lee (annotated fig. 7) teaches the chip structure as claimed in claim 1, wherein the conductive pad (135) has a convex top surface (top of 135 is curved, see annotated fig. 7), and the first conductive via structure (Liu, left 138A) and the second conductive via structure (Liu, right 138A) are both under the convex top surface (left 138A and right 138A from Liu would replace 130 from Lee and be under the top surface of 135).
Regarding Claim 8, the combination of Lee and Liu teaches the chip structure as claimed in claim 1, wherein the first conductive via structure (Liu, left 138A) and the second conductive via structure (Liu, right 138A) are under the protruding bottom portion (Lee, 170).
Regarding Claim 29, Lee (annotated fig. 7) teaches the chip structure as claimed in claim 1, wherein the lower surface (lower surface) of the conductive pillar (165) is a concave curved lower surface (see annotated fig. 7).
Regarding Claim 30, Lee (annotated fig. 7) teaches the chip structure as claimed in claim 29, wherein the lower surface (lower surface) of the conductive pillar (165) is connected (165 is connected to 140 through 160) to the second passivation layer (140).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Liu as applied to Claim 1 above, and further in view of Takei et al. (2020/0312806 A1; hereinafter Takei).
Regarding Claim 25, Lee doesn’t teach the chip structure as claimed in claim 1, wherein the seed layer of the conductive pillar has a second convex curved top surface overlapping the first convex curved top surface of the second passivation layer, and the first convex curved top surface and the second convex curved top surface face away from the substrate.
However, Takei (annotated fig. 17) teaches the seed layer ([0128], 17) of the conductive pillar ([0123], 18) has a second convex curved top surface (curved portion of 17) overlapping the first convex curved top surface (curved portion of 23) of the second passivation layer ([0128], 23), and the first convex curved top surface (curved portion of 17) and the second convex curved top surface (curved portion of 23) face away from the substrate ([0071], 212). Takei teaches that the shape of the conductive pillar can change as needed while maintaining the function of electrical connection. One of ordinary skill in the art could have substituted the conductive pillar of Takei for the conductive pillar of Lee and yielded the predictable results of providing electrical connection.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the conductive pillar of Takei for the conductive pillar of Lee, since simple substitution of conductive pillars for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 9-14, 18-19, 21, and 28 are allowed.
The following is an examiner’s statement of reasons for allowance. None of the references, either singly or in combination, teach or render obvious the limitations presented in Claim 9 wherein “the conductive pillar further has a sidewall connected to the concave curved lower surface, and an angle between the sidewall and the concave curved lower surface is less than 90 degrees” and in Claim 14 wherein “the passivation layer has an inner wall surrounding a protruding bottom portion of the conductive pillar, the inner wall is over a top surface of the conductive pad, and the inner wall surrounds the first conductive via structure, the second conductive via structure, the third conductive via structure, and the fourth conductive via structure in a top view of the passivation layer, the first conductive via structure, the second conductive via structure, the third conductive via structure, and the fourth conductive via structure”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 31 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. None of the references, either singly or in combination, teach or render obvious the limitations presented in Claim 31 wherein “the conductive pillar has a third sidewall, the lower surface is connected between the third sidewall and the second sidewall, and the third sidewall is connected to an inner wall of the second passivation layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
2022/0230978 A1 refers to bumps, redistribution lines, and passivation layers and the relationships of these features (see fig. 15, for example).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 30, 2026