Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 21, 2025 has been entered.
Election/Restrictions
Claims 1-8, 10-13, 15, and 21-27 are pending in this application.
Applicant elected without traverse of Species 1, claims 1-8, 10-13, 15, and 21-27 in the reply filed on February 26, 2025.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed October 22, 2025, 2025. Claims 1, 4, 10, 21, and 23, are amended. The Examiner notes that claims 1-8, 10-13, 15, and 21-27 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-8, 10-13, 15, and 21-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng (US 2020/0075717 A1).
With respect to claim 1, Cheng teaches:
A method for forming a semiconductor device structure, comprising:
forming a fin structure (elongated nanosheet structure 110-1) over a substrate (substrate 105), wherein the fin structure comprises a plurality of first semiconductor layers (semiconductor layers 111, 113, 115, 117) and a plurality of second semiconductor layers (semiconductor layers 112, 114, 116) in an alternating manner;
forming a protection layer (etch stop layer 120) over a topmost layer of the plurality of first semiconductor layers (117);
forming a dummy gate structure (dummy gate 130) over the protection layer (120);
forming gate spacers (gate sidewall spacer 134) over sidewalls of the dummy gate structure (130);
forming a contact etch stop layer (interlayer dielectric layer 150) adjacent to the gate spacers (134),
wherein an interface (see annotated Fig. 4 below) between the contact etch stop layer (150) and the protection layer (120) is aligned with a sidewall surface of the gate spacers (134)
removing the dummy gate structure (see Fig. 5A) and the plurality of first semiconductor layers to form a trench (empty space between left and right 134 and left and right 136, called open gate region 130-1 and recess region 162-1 at various stages of manufacture);
removing the first semiconductor layers to form nanostructures (nanosheet stack was patterned to form nanostructures between Fig. 1 and Fig. 2B);
and forming a metal gate structure (work function metal 162) in the trench, wherein the protection layer (120) is surrounded by the metal gate structure (162) (see Fig. 6A-6B).
wherein a topmost nanostructure (116) is separated from the protection layer (120) by a portion of the metal gate structure (162 between 120 and 116).
Although Cheng does not use the term “contact etch stop layer (CESL)” to describe interlayer dielectric 150, the Examiner takes the position that the interlayer dielectric serves the purpose of a CESL and therefore reads on the claim limitation. The ordinary artisan would understand that a CESL is a layer that protects a source, drain, or gate during the formation of contacts. As shown in Fig. 7A, interlayer dielectric 150 protects the S/D during the etching of recess region 162-1 which is subsequently filled by the gate electrode. Cheng further teaches that the interlayer dielectric 150 may comprise for example “silicon oxide, silicon nitride, silicon oxynitride, SiCOH, SiCH, SiCNH” (see Fig. 61) which includes the same materials taught in the written description of the instant application (see para. [0058] of the instant application).
PNG
media_image1.png
667
692
media_image1.png
Greyscale
With respect to claim 2, Cheng further teaches:
wherein the protection layer is partially etched during the step of forming the trench (120, para. 71 “some material of the etch stop layer 120 may be etched during the high-k etch process to remove the exposed portions of the gate dielectric layer 160”),
and wherein the protection layer (120) has a first portion (portion directly under 134) covered by the gate spacers (134) and a second portion (top portion) covered by the metal gate structure (162 before it is etched back) after the metal gate structure is formed,
a first height of the first portion is greater than a second height of the second portion (120 is partially etched during the high-k etch described in para. 71. Although changes in height are not shown in the drawings, the first portion is protected by 134 during the etch process and is therefore thicker than the height of the second portion).
With respect to claim 4, Cheng further teaches:
The method for forming the semiconductor device structure as claimed in claim 1, further comprising:
laterally etching the plurality of first semiconductor layers (111, 113, 115, 117) before the dummy gate structure is removed (para. 55 “In one embodiment, the inner spacers 136 are formed by a process which comprises laterally recessing exposed sidewall surfaces of sacrificial nanosheet layers 111, 113, 115, and 117 of the nanosheet stack structure 110 - 2 (shown in FIG. 3B) to form recesses in the sidewalls of the nanosheet stack structure 110 – 2.”)
and forming inner spacers (inner spacers 136) over sidewalls of remaining portions of the plurality of first semiconductor layers (111, 113, 115, 117) after the laterally etching.
With respect to claim 5, Cheng further teaches:
forming a gate spacer layer (gate sidewall spacer 134) over the sidewalls of the dummy gate structure (130) and covering a top surface of the protection layer (120);
and partially removing the gate spacer layer such that the gate spacers are formed (para. 51 “The conformal layer of dielectric material is then patterned by performing an anisotropic dry etch process, such as RIE, to etch down the conformal layer of dielectric material in a vertical direction”.)
With respect to claim 6, Cheng further teaches: wherein a sidewall of the protection layer is (120) in direct contact with the gate spacers (134) (para. 51 “The gate sidewall spacer 134 is then formed by depositing a conformal layer of dielectric material over the entire surface of the semiconductor structure”. Although not shown in the drawings, Cheng teaches that before etching the gate spacers cover the sidewall of the protection layer 120)
With respect to claim 7, Cheng further teaches:
forming a gate spacer layer (para. 51 “conformal layer” that becomes gate sidewall spacer) over the sidewalls of the dummy gate structure (130) (para. 51 “The gate sidewall spacer 134 is then formed by depositing a conformal layer of dielectric material over the entire surface of the semiconductor structure”)
wherein the gate spacer layer (conformal layer that is etched into the gate sidewall spacer) is in direct contact with the topmost layer of the plurality of first semiconductor layers (117, forming the conformal layers over the entire surface of the structure in Fig. 2A and 2B, which includes exposed parts of first semiconductor layers);
and partially removing the gate spacer layer such that the gate spacers are formed (para. 51 “The conformal layer of dielectric material is then patterned by performing an anisotropic dry etch process, such as RIE, to etch down the conformal layer of dielectric material in a vertical direction”.)
With respect to claim 8, Cheng further teaches:
The method for forming the semiconductor device structure as claimed in claim 1,
wherein forming the metal gate structure comprises:
forming a high-k dielectric layer (gate dielectric 160), between one of the second semiconductor layers (116) and the protection layer (120) (para. 65 “The gate dielectric layers 160 are preferably formed of a high-k dielectric material having a dielectric constant of about 3.9 or greater.”)
With respect to claim 10, Cheng teaches:
A method for forming a semiconductor device structure, comprising:
forming a fin structure (elongated nanosheet structure 110-1) over a substrate (substrate 105), wherein the fin structure comprises a plurality of first semiconductor layers (semiconductor layers 111, 113, 115, 117) and a plurality of second semiconductor layers (semiconductor layers 112, 114, 116) in an alternating manner;
forming a hard mask layer (etch stop layer 120) over the fin structure (105);
etching a portion of the first semiconductor layers to form an opening (para. 56 “n isotropic dry plasma etch process can be performed to laterally etch the exposed sidewall surfaces of the sacrificial nanosheet layers 111 , 113 , 115 , and 117”);
forming an inner spacer (inner spacer 136) in the opening (para. 57 “The recesses are then filled with dielectric material to the form inner spacers 136”), wherein the hard mask layer (120) is in direct contact with the inner spacer (136) (see Fig. 4);
wherein a topmost surface of the inner spacer (top of 136) is lower than a top surface of the hard mask layer (top of 120)
and forming a gate structure over the fin structure (gate structure 162 and gate dielectric 160), wherein a portion of the gate structure is directly below the hard mask layer (portion between 116 and 120); and
forming a conductive cap layer (metallic gate electrode layer 170) on the gate structure (160 and 162).
With respect to claim 11, Cheng:
forming a dummy gate structure (dummy gate 130) over the fin structure (110-1);
and forming a gate spacer (gate spacer 134) adjacent to the dummy gate structure (130), wherein the gate spacers (134) is in direct contact with the hard mask layer (210) (see Fig. 6A).
With respect to claim 12, Cheng further teaches:
forming a contact etch stop layer (interlayer dielectric layer 150) adjacent to the gate spacers (134),
wherein the contact etch stop layer (150) is in direct contact with the hard mask layer (120) (see Fig. 7A).
With respect to claim 13, Cheng further teaches:
removing a portion of the hard mask layer (120) (120 is recessed between Fig. 1 and Fig. 2B);
and forming a gate spacer (gate sidewall spacer 134) over the hard mask layer (120) (see Fig. 6A).
With respect to claim 15, Cheng further teaches:
forming a high-k dielectric layer (gate dielectric layers 160, formed from high-k materials per para. 65), between one of the second semiconductor layers (116) and the hard mask layer (120) (see Fig. 6A)
With respect to claim 21, Cheng teaches in Figs. 1-8:
A method for forming a semiconductor device structure, comprising:
forming a fin structure (elongated nanosheet structure 110-1) over a substrate (substrate 105), wherein the fin structure comprises a plurality of first semiconductor layers (semiconductor layers 111, 113, 115, 117) and a plurality of second semiconductor layers (semiconductor layers 112, 114, 116) in an alternating manner;
forming a protection layer (etch stop layer 120) over the fin structure (110-1);
forming a dummy gate structure (dummy gate 130) over the protection layer (120);
forming a gate spacer (gate sidewall spacer 134 and inner spacers 136) adjacent to the dummy gate structure (130);
forming a contact etch stop layer (interlayer dielectric layer 150) adjacent to the gate spacers (134),
removing the dummy gate structure (see Fig. 5A) and the plurality of first semiconductor layers to form a trench (empty portion between gate sidewall spacers 134 and/or inner spacers 134, which is part of open gate region 130-1 or recess region 162-1 depending on step in process);
removing a portion of the protection layer (120, para. 71 “some material of the etch stop layer 120 may be etched during the high-k etch process to remove the exposed portions of the gate dielectric layer 160”), wherein a height of a first portion of the protection layer directly below the gate spacer is greater than a height of a second portion of the protection layer exposed by the trench (the removal of 120 during the high-k etch process occurs where 120 while the portion of 120 under 134 is protected during the etch process)
forming a gate structure (gate dielectric 160, work function setting metal 162) in the trench, wherein the protection layer is surrounded by the gate structure (see Fig. 7B, 120 is surrounded in the X direction by 162 and 160); and
forming a conductive cap layer (gate electrode layer 170) on the gate structure (162 and 160), wherein the gate spacer (134) is between the conductive cap layer (170) and the contact etch stop layer (150).
With respect to claim 22, Cheng further teaches:
wherein a bottom surface of the gate spacer (bottom surface of the lowermost part of inner spacers 136) is lower than a top surface of the protection layer (120).
With respect to claim 23, Cheng further teaches:
wherein the contact etch stop layer (150) is in direct contact with the hard mask layer (120) (see Fig. 7A).
With respect to claim 24, Cheng further teaches:
wherein a sidewall surface of the protection layer (120) is covered by the gate spacer (para. 51 “The gate sidewall spacer 134 is then formed by depositing a conformal layer of dielectric material over the entire surface of the semiconductor structure” During this step the gate spacer covers the sidewalls of 120”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 is rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Cheng (US 2020/0075717 A1).
With respect to claim 3, Cheng teaches all limitations of claim 2 upon which claim 3 depends. Cheng further teaches that a portion of the protection layer (etch stop/hard mask layer 120) is etched during the high-k etch process (para. 71) but that the thickness of 120 prevents it from being etched enough to damage the underlying layers. Although Cheng does not teach a specific ratio, the Examiner takes the position that the small amount of 120 etched from the second portion meets the limitation:
wherein a ratio of the second height to the first height is greater than or equal to about 0.1 and less than 1.
In the event that Cheng does not teach the above limitation, which the Examiner does not concede, it would be obvious to etch an amount of 120 during the high-k etch step that causes the ratio to be met. It would be obvious to the ordinary examiner to limit the amount of the protection layer is etched such that the height is at least 0.1 in order to protect the underlying materials from exposure damage (para. 71)
Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 2020/0105872 A1) as applied to independent claims 1 and 21 above and in view of Chang (US 2016/0240650 A1).
With respect to claim 25, Cheng teaches all limitations of claim 1 upon which claim 25 depends. Cheng does not teach:
wherein the protection layer has U-shaped structure
Chang teaches:
wherein the protection layer (isolation layer 114) has U-shaped structure
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chang into the device of Cheng to partially etch the protection layer while forming the trench. The ordinary artisan would have been motivated to modify Cheng in the manner set forth above for the purpose of enlarging the effective area of the gate structure (para. 44 of Chang).
With respect to claim 26, Cheng teaches all limitations of claim 10 upon which claim 25 depends. Cheng does not teach:
wherein the protection layer has U-shaped structure
Chang teaches:
wherein the protection layer (isolation layer 114) has U-shaped structure
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chang into the device of Cheng to partially etch the protection layer while forming the trench. The ordinary artisan would have been motivated to modify Cheng in the manner set forth above for the purpose of enlarging the effective area of the gate structure (para. 44 of Chang).
With respect to claim 27, Cheng teaches all limitations of claim 21 upon which claim 25 depends. Cheng does not teach:
wherein the protection layer has U-shaped structure
Chang teaches:
wherein the protection layer (isolation layer 114) has U-shaped structure
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chang into the device of Cheng to partially etch the protection layer while forming the trench. The ordinary artisan would have been motivated to modify Cheng in the manner set forth above for the purpose of enlarging the effective area of the gate structure (para. 44 of Chang).
Response to Arguments
Applicant's arguments filed October 22, 2025 have been fully considered but they are not persuasive.
With respect to the argument that Cheng fails to disclose a contact etch stop layer, which was rejected under Chang in a previous office action, the Examiner has reconsidered the interpretation of a broadest reasonable interpretation of contact etch stop layer and determined that the interlayer dielectric layer 150 of Cheng reads on the limitations related to the CESL. A more thorough explanation can be found under the rejection of claim 1 above.
With respect to the argument that Cheng fails to disclose a conductive cap, the Examiner determines that under a broadest reasonable interpretation, a “conductive cap layer on the gate structure” as claimed can be any conductive layer deposited on a gate structure. The metallic gate structure 170 of Cheng is a “metallic material such as tungsten, ruthenium, cobalt, copper, aluminum, gold” (para. 73) that is deposited over the gate layers 160 and 162 and therefore reads on the claim limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897