Prosecution Insights
Last updated: August 17, 2026
Application No. 17/874,366

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING

Non-Final OA §103
Filed
Jul 27, 2022
Priority
May 21, 2020 — divisional of 16/880,038
Examiner
LIN, JOHN
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
5 (Non-Final)
60%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
69%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
256 granted / 427 resolved
-8.0% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
16 currently pending
Career history
453
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.6%
+16.6% vs TC avg
§102
21.6%
-18.4% vs TC avg
§112
19.3%
-20.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 427 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office Action is in response to Applicant’s reply filed 29 April 2026. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 5, 6, 8, 9, 11, 18, 19 and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (U.S. Pub. 2016/0112614) in view of Lee et al. (U.S. Pub. 2017/0047367). Claim 1: Masuda et al. discloses a method for forming a semiconductor arrangement, in Figs. 3 and 4 and in paragraphs 54, 58-61, 69 and 70, comprising: forming a first recess (48) in a substrate (12), wherein the first recess (48) overlies a first component (left PD) in the substrate (12); forming a first trench (middle 47) in the substrate (12), wherein the first trench (middle 47) is between the first component (left PD) and a second component (right 42) in the substrate (12); forming a buffer layer (45) in the first recess and the first trench (middle 47); and forming a gap fill layer (46) in the first recess (48) over the buffer layer (45) and in the first trench (middle 47) over the buffer layer (45) such that a first portion (portion of 46 in the first recess) of the gap fill layer and a first portion (portion of 45 above left 47) of the buffer layer overlies the first component (left PD) and a second portion (portion of 46 in the first trench) of the gap fill layer is between the first component (left PD) and the second component (right 42), wherein: wherein the gap fill layer (46) comprises a metal (46 can be hafnium oxide (paragraph 61), which comprises the metal hafnium), wherein the gap fill layer (46) has a homogenous composition, and wherein the metal of the gap fill layer (46) overlies the first component (left PD). PNG media_image1.png 730 526 media_image1.png Greyscale Masuda et al. appears not to explicitly disclose wherein the second portion of the gap fill layer defines a first void in the first trench between the first component and the second component Lee et al., however, in Fig. 4 and in paragraphs 5 and 35, discloses the second portion (104b) of the gap fill layer (104b and 302) defines a first void (middle AG) in the first trench (trench in which middle 104 is formed in) between the first component (second 110 from the left) and the second component (second 110 from the right), in order to reduce crosstalk. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. with the disclosure of Lee et al. to have made the second portion of the gap fill layer pinches to create a void in the first trench between the first component and the second component in order to reduce crosstalk (paragraph 5 of Lee et al.). Claim 2: Masuda et al. in view of Lee et al. discloses the method of claim 1. Masuda et al. in view of Lee et al, as applied to claim 1, appears not to explicitly disclose wherein forming the first recess comprises forming the first recess to have a tapered sidewall. Masuda et al., however, in Fig. 11, further discloses forming the first recess (48) comprises forming the first recess (48) to have a tapered sidewall. PNG media_image2.png 437 588 media_image2.png Greyscale Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Masuda et al. that is in the same field of endeavor with Masuda et al. in view of Lee et al, as applied to claim 1, before the effective filing date of the claimed invention in order to substitute forming the first recess comprises forming the first recess to have a tapered sidewall as further disclosed by Masuda et al. for the first recess disclosed by Masuda et al. in view of Lee et al, as applied to claim 1. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of forming the first recess comprises forming the first recess to have a tapered sidewall further disclosed by Masuda et al. for the first recess disclosed by Masuda et al. in view of Lee et al, as applied to claim 1, would have yielded predictable results, namely providing a suitable configuration for the anti-reflection portion. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Claim 3: Masuda et al. in view of Lee et al. discloses the method of claim 2, and, in Fig. 3, Masuda et al. further discloses comprising: forming a second recess (48) in the substrate (12), wherein the second recess (48) overlies the first component (left PD); and forming the gap fill layer (46) in the second recess (48) such that a third portion (portion of 46 in the second recess) of the gap fill layer (48) overlies the first component (left PD). Masuda et al. in view of Lee et al., as applied above, appears not to explicitly disclose the second recess has a tapered sidewall. Masuda et al., however, in Fig. 11, further discloses forming the second recess (48) has a tapered sidewall. Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Masuda et al. that is in the same field of endeavor with Masuda et al. in view of Lee et al, as applied above, before the effective filing date of the claimed invention in order to substitute the second recess has a tapered sidewall as further disclosed by Masuda et al. for the second recess disclosed by Masuda et al. in view of Lee et al, as applied above. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the second recess has a tapered sidewall further disclosed by Masuda et al. for the second recess disclosed by Masuda et al. in view of Lee et al, as applied above, would have yielded predictable results, namely providing a suitable configuration for the anti-reflection portion. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Claim 5: Masuda et al. in view of Lee et al. discloses the method of claim 1, and, in Fig. 3 and in paragraphs 70 and 71, Masuda et al. further discloses wherein forming the first recess (48) comprises: forming a hard mask layer (81) over the substrate (12); patterning (lithography technique to pattern 81) the hard mask layer to generate a patterned hard mask layer (81); and etching (dry etching process) the substrate (12) using the patterned hard mask layer (81) to form the first recess (48). Claim 6: Masuda et al. in view of Lee et al. discloses the method of claim 1, and, in Fig. 3 and in paragraph 57, Masuda et al. further discloses comprising: forming one or more structures (Tr) on a first surface (lower surface of 12) of the substrate (12) prior to forming the first recess (48), wherein: forming the first recess (48) comprises forming the first recess (48) through a second surface (upper surface of 12) of the substrate (12), and the second surface (upper surface of 12) is a backside surface of the substrate (12). Claim 8: Masuda et al. in view of Lee et al. discloses the method of claim 1, and, in Fig. 3 and in paragraph 72, Masuda et al. further discloses comprising, before forming the first trench (middle 47): forming a photoresist (82) in the first recess (48); and patterning (lithography technique to pattern 82) the photoresist (82) to expose a portion (middle opening in 82) of the substrate (12), wherein the photoresist (82) remains in the first recess (48) after patterning the photoresist (82). Claim 9: Masuda et al. in view of Lee et al. discloses the method of claim 1, and, in Fig. 4, Masuda et al. further discloses wherein the gap fill layer (46) is separated from the substrate (12) by the buffer layer (45). Claim 11: Masuda et al. in view of Lee et al. discloses the method of claim 1, and, in Fig. 12, Masuda et al. further discloses wherein: the first recess (48) extends from a surface (upper surface of 12) of the substrate (12) a first depth (depth of 48) into the substrate (12), the first trench (middle 47) extends from the surface (upper surface of 12) of the substrate (12) a second depth (depth of middle 47) into the substrate (12), and the second depth (depth of middle 47) is greater than the first depth (depth of 48). Claim 18: Masuda et al. discloses a method for forming a semiconductor arrangement, in Figs.3 and 4 and in paragraphs 54, 58-61, 64, 66, 69 and 70-73, comprising: etching (dry etching process) a substrate (12) to define a recess (48 above left PD) overlying a first photodiode (left PD) disposed within the substrate (12); forming a photoresist (82) to cover the recess (48 above left PD); etching (anisotropic dry etching process) the substrate (12) to define a first trench (middle 47) between the first photodiode (left PD) and a second photodiode (right PD) and a second trench (left 47) between the first photodiode (left PD) and a third photodiode (PD, which would correspond to the red pixel photodiode, to the left of the first photodiode) while the photoresist (82) covers the recess (48 above left PD); removing the photoresist (82); forming a buffer layer (45) in the recess (48 above left PD), the first trench (middle 47) and the second trench (left 47); forming a gap fill layer (46) in the recess (48 above left PD), the first trench (middle 47), and the second trench (left 47), wherein the only materials present in the first trench (middle 47) and the second trench (left 47 are the buffer layer (45) and the gap fil layer (46); forming a grid structure (49) over the gap fill layer (46). Masuda et al., in the embodiment of Figs. 3 and 4, appears not to explicitly disclose wherein the recess is defined by a tapered sidewall of the substrate. Masuda et al., however, in Fig. 11, further discloses forming the recess (48) is defined by a tapered sidewall of the substrate (12). Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Masuda et al. that is in the same field of endeavor with Masuda et al., in the embodiment of Figs. 3 and 4, before the effective filing date of the claimed invention in order to substitute the recess is defined by a tapered sidewall of the substrate as further disclosed by Masuda et al. for recess disclosed by Masuda et al., in the embodiment of Figs. 3 and 4. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the recess is defined by a tapered sidewall of the substrate further disclosed by Masuda et al. for the recess disclosed by Masuda et al., in the embodiment of Figs. 3 and 4, would have yielded predictable results, namely providing a suitable configuration for the anti-reflection portion. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Masuda et al. also appears not to explicitly disclose wherein the gap fill layer defines a first void in the first trench and a second void in the second trench, and wherein the first photodiode is laterally separated from the first void by the gap fill layer. Lee et al., however, in Fig. 4 and in paragraphs 5, 35 and 41, discloses the gap fill layer (104b and 302) defines a first void (middle AG) in the first trench (middle trench in which 104 is formed in) and a second void (right AG) in the second trench (right trench in which 104 is formed in), the first photodiode (second 110 from the left) is laterally separated from the first void (middle AG) by the gap fill layer (104b and 302) in order to reduce crosstalk. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. with the disclosure of Lee et al. to have made the gap fill layer defines a first void in the first trench and a second void in the second trench, and the first photodiode is laterally separated from the void by the gap fill layer in order to reduce crosstalk (paragraph 5 of Lee et al.). Claim 19: Masuda et al. in view of Lee et al. discloses a method of claim 18, and, in Fig. 4, Masuda et al. further discloses wherein: wherein forming the grid structure (49) comprises forming the grid structure (49) to overlie a portion (portion of 12 between left PD and right PD) of the substrate (12) between the first photodiode (left PD) and the second photodiode (right PD). Claim 21: Masuda et al. in view of Lee et al. discloses the method of claim 18, and, in Fig. 4 and in paragraph 61, Masuda et al. further discloses wherein the gap fill layer (46) has a homogenous composition. Claim 22: Masuda et al. in view of Lee et al. discloses the method of claim 18, and, in Fig. 4, Masuda et al. further discloses wherein: the buffer layer (45) is between the gap fill layer (46) and the first photodiode (left PD). Since Lee et al. discloses the gap fill layer (104b and 302) defines a first void (middle AG) in the first trench (middle trench in which 104 is formed in), Masuda et al. in view of Lee et al. would disclose the first photodiode is laterally separated from the first void by the buffer layer. Claim 23: Masuda et al. in view of Lee et al. discloses the method of claim 18. Masuda et al. in view of Lee et al., as applied to of claim 18, appears not to explicitly disclose a bottom of the first void is above a bottom surface of the first photodiode. Lee et al., however, in Fig. 4 and in paragraph 5, further discloses a bottom of the first void (middle AG) is above a bottom surface of the first photodiode (second 110 from the left) in order to reduce crosstalk. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. in view of Lee et al., as applied to claim 18, with the further disclosure of Lee et al. to have made a bottom of the void is above a bottom surface of the first photodiode in order to reduce crosstalk (paragraph 5 of Lee et al.). Claim 24: Masuda et al. in view of Lee et al. discloses the method of claim 1, and Masuda et al., in Figs.3 and 4 and in paragraphs 54 and 66, further discloses comprising: forming a second trench (left 47) in the substrate (12) between the first component (left PD) and a third component (PD, which would correspond to the red pixel photodiode, to the left of the first photodiode) in the substrate (12), wherein: the first component (left PD) is a first photodiode, the second component (right PD) is a second photodiode, and the third component is a third photodiode, forming the buffer layer (45) comprises forming the buffer layer (45) in the second trench (left 47), forming the gap fill layer (46) comprises forming the gap fill layer (46) in the second trench (left 47) over the buffer layer (56), a third portion (portion of 46 in left 47) of the gap fill (46) layer in the second trench (left 47), there are no photodiodes intervening between the first photodiode (left PD) and the second photodiode (right PD), and there are no photodiodes intervening between the first photodiode (left PD) and the third photodiode (PD, which would correspond to the red pixel photodiode, to the left of the first photodiode). Masuda et al. in view of Lee et al., as applied above, appears not to explicitly disclose wherein the third portion of the gap fill layer defines a second void in the second trench between the first photodiode and the third photodiode. Lee et al., however, in Fig. 4 and in paragraphs 5, 33 and 35, further discloses the third portion (portion of 104 between the first and third photodiode) of the gap fill layer (104b ad 302) defines a second void (AG in third portion) in the second trench (trench in which third portion is in) between the first photodiode and the third photodiode in order to reduce crosstalk. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. in view of Lee et al. with the further disclosure of Lee et al. to have made the third portion of the gap fill layer defines a second void in the second trench between the first photodiode and the third photodiode in order to reduce crosstalk (paragraph 5 of Lee et al.). Claim 25: Masuda et al. in view of Lee et al. discloses the method of claim 24, and Masuda et al., in Fig., further discloses a line drawn in a lateral direction from the first photodiode (left PD) to the second photodiode (right PD) intersects merely the substrate (12), the buffer layer (45), the gap fill layer (46). Since Lee et al., in Fig. 4, discloses the first void (middle AG) is between the first photodiode (second 110 from the left) and the second photodiode (second 110 from the right), Masuda et al. in view of Lee et al. would disclose the line intersects merely the substrate, the buffer layer, the gap fill layer, and the first void between the first photodiode and the second photodiode. Claim(s) 7 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Lee et al. as applied to claim 1 above, and further in view of Cheng et al. (U.S. Pub. 2019/0148422), hereinafter referred to as Cheng 422. Claim 7: Masuda et al. in view of Lee et al. discloses the method of claim 1. Masuda et al. in view of Lee et al. appears not to explicitly disclose wherein forming the first recess comprises: etching the substrate to define a first partial recess having a first cross-sectional profile; and etching the substrate to modify the first partial recess to form the first recess having a second cross-sectional profile different than the first cross-sectional profile. Cheng 422, however, discloses, in Figs. 5E and 5F and in paragraphs 56 and 57, wherein forming the first recess (left 216) comprises: etching the substrate (210) to define a first partial recess (282) having a first cross-sectional profile; and etching the substrate to modify the first partial recess to form the first recess (left 216) having a second cross-sectional profile different than the first cross-sectional profile. Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the teachings of Cheng 422 in the same or in a similar field of endeavor with Masuda et al. in fiew of Lee et al. before the effective filing date of the claimed invention in order to substitute forming the first recess comprises: etching the substrate to define a first partial recess having a first cross-sectional profile; and etching the substrate to modify the first partial recess to form the first recess having a second cross-sectional profile different than the first cross-sectional profile of Cheng 422 for the method of forming the first recess of Matsuda et al. in view of Lee et al. The substituted methods were known in the art, one of ordinary skill could have substituted the methods, and the simple substitution of forming the first recess comprises: etching the substrate to define a first partial recess having a first cross-sectional profile; and etching the substrate to modify the first partial recess to form the first recess having a second cross-sectional profile different than the first cross-sectional profile of Cheng 422 for the method of forming the first recess of Masuda et al. in view of Lee et al. would have yielded predictable results, namely the forming the recess by etching the substrate to define a first partial recess and etching first partial recess. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Claim 26: Masuda et al. in view of Lee et al. discloses the method of claim 1. Masuda et al. in view of Lee et al. appears not to explicitly disclose, comprising: forming a dielectric layer over the gap fill layer and directly contacting the gap fill layer; and forming a grid structure over the dielectric layer, wherein a bottom surface of the grid structure directly contacts the dielectric layer. Cheng 422, however, discloses, in Fig. 5J and in paragraphs 30, 46, 61 and 63, forming a dielectric layer (300) over the gap fill layer (292) and directly contact the gap fill layer (292); and forming a grid structure (310) over the dielectric layer (300), wherein a bottom surface (bottom surface of 310) of the grid structure (310) directly contacts the dielectric layer (300). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Li et al. in view of Cheng 951 in view of Lee et al. with the disclosure of Cheng 422 to have formed a dielectric layer over the gap fill layer and directly contacting the gap fill layer; and formed a grid structure over the dielectric layer, wherein a bottom surface of the grid structure directly contacts the dielectric layer in order to prevent optical interference between pixel regions (paragraph 30 of Cheng 422). Claim(s) 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. (U.S. Pub. 2016/0112614) in view of Cheng et al. (U.S. Pub. 2019/0096951), hereinafter referred to as Cheng 951 in view of Lee et al. (U.S. Pub. 2017/0047367). Claim 12: Masuda et al. discloses a method for forming a semiconductor arrangement, in Figs. 3 and 4 and in paragraphs 54, 58-61, 69 and 71-73, comprising: etching (dry etching process) a surface (upper surface of 12) of a substrate (12) to define a recess (48 above left PD) over a first photodiode (left PD) disposed within the substrate (12); forming a photoresist (82) in the recess (48 above left PD), wherein a portion (middle opening in 82) of the surface (upper surface of 12) of the substrate (12) is exposed after forming the photoresist (82); and etching (anisotropic dry etching process) the portion (middle opening in 82) of the surface (upper surface of 12) to define a trench (middle 47) between the first photodiode (left PD) and a second photodiode (right PD), wherein: the trench (middle 47) extends from the surface (upper surface of 12) to a first depth (depth of middle 47) in the substrate (12), the first photodiode (left PD) is spaced apart from the surface (upper surface of 12) of the substrate (12) by a first distance (distance between upper surface of 12 and upper surface of left 42), the first distance (distance between upper surface of 12 and upper surface of left 42) is less than the first depth (depth of middle 47), and forming a buffer layer (45) in the recess (48 above left PD) and in the trench (middle 47); and forming a gap fill layer (46) in the recess (48 above left PD) and in the trench (middle 47) over the buffer layer (45), wherein: the gap fill layer (46) comprises a metal (46 can be hafnium oxide (paragraph 61), which comprises the metal hafnium), the gap fill layer (46) has a homogenous composition, and a line drawn in a lateral direction from the first photodiode (left PF) to the second photodiode (right PF) intersects merely the substrate (12), the buffer layer (45), and the gap fill layer (46). Masuda et al. appears not to explicitly disclose wherein a depth of the recess from the surface of the substrate to a bottom of the recess is 500 to 10,000 angstroms. Cheng 951, however, discloses a depth (d1) of the recess (408) from the surface of the substrate (404) to a bottom of the recess is about 20 nm to about 500 nm (200 to 5000 angstroms) in order to increase the amount of light absorbed. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. with the disclosure of Cheng 951 to have made a depth of the recess from the surface of the substrate to a bottom of the recess 500 to 10,000 angstroms in order to increase the amount of light absorbed (paragraph 33 of Cheng 951). Also, in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists (M.P.E.P. § 2144.05). Masuda et al. in view of Chang 951 appears not to explicitly disclose wherein a void is defined in the trench by the gap fill layer and a bottom of the void is above a bottom surface of the first photodiode, wherein the line drawn in a lateral direction from the first photodiode to the second photodiode intersects merely the substrate, the buffer layer, the gap fill layer, and the void between the first photodiode and the second photodiode. Lee et al., however, in Fig. 4 and in paragraphs 5, 35 and 41, discloses a void (AG) is defined in the trench (trench in which 104b is formed in) by the gap fill layer (104b) and a bottom of the void (AG) is above a bottom surface of the first photodiode (second 110 from the left), wherein the line drawn in a lateral direction from the first photodiode (second 110 from the left) to the second photodiode (second 110 from the right) intersects merely the substrate (100), the buffer layer (104a), the gap fill layer (104b), and the void (AG) between the first photodiode (second 110 from the left) and the second photodiode (second 110 from the right) in order to reduce crosstalk. It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. in view of Cheng 951 with the disclosure of Lee et al. to have made a void is defined in the trench by the gap fill layer and a bottom of the void is above a bottom surface of the first photodiode, wherein the line drawn in a lateral direction from the first photodiode to the second photodiode intersects merely the substrate, the buffer layer, the gap fill layer, and the void between the first photodiode and the second photodiode in order to reduce crosstalk (paragraph 5 of Lee et al.). Claim 17: Masuda et al. in view of Cheng 951 in view of Lee et al. discloses the method of claim 12. Masuda et al. in view of Cheng 951 in view of Lee et al., as applied to claim 12, appears not to explicitly disclose wherein the recess is defined by a tapered sidewall of the substrate. Masuda et al., however, in Fig. 11, further discloses forming the recess (48) is defined by a tapered sidewall of the substrate (12). Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the further disclosure of Masuda et al. that is in the same field of endeavor with Masuda et al. in view of Cheng 951 in view of Lee et al., as applied to claim 12, before the effective filing date of the claimed invention in order to substitute the recess is defined by a tapered sidewall of the substrate as further disclosed by Masuda et al. for the recess disclosed by Masuda et al. in view of Cheng 951 in view of Lee et al., as applied to claim 12. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the recess is defined by a tapered sidewall of the substrate further disclosed by Masuda et al. for the recess disclosed by Masuda et al. in view of Cheng 951 in view of Lee et al., as applied to claim 12, would have yielded predictable results, namely providing a suitable configuration for the anti-reflection portion. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Cheng 951 in view of Lee et al. as applied to claim 12 above, and further in view of Cheng et al. (U.S. Pub. 2019/0148422), hereinafter referred to as Cheng 422. Claim 14: Masuda et al. in view of Cheng 951 in view of Lee et al. discloses the method of claim 13. Masuda et al. in view of Cheng 951 in view of Lee et al. appears not to explicitly disclose comprising: forming a dielectric layer over the gap fill layer and directly contacting the gap fill layer; and forming a grid structure over the dielectric layer, wherein a bottom surface of the grid structure directly contacts the dielectric layer. Cheng 422, however, discloses, in Fig. 5J and in paragraphs 30, 46, 61 and 63, forming a dielectric layer (300) over the gap fill layer (292) and directly contact the gap fill layer (292); and forming a grid structure (310) over the dielectric layer (300) wherein a bottom surface (bottom surface of 310) of the grid structure (310) directly contacts the dielectric layer (300). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Masuda et al. in view of Cheng 951 in view of Lee et al. with the disclosure of Cheng 422 to have formed a dielectric layer over the gap fill layer and directly contacting the gap fill layer; and formed a grid structure over the dielectric layer, wherein a bottom surface of the grid structure directly contacts the dielectric layer in order to prevent optical interference between pixel regions (paragraph 30 of Cheng 422). Response to Arguments Applicant’s arguments with respect to claim(s) 1-3, 5-9, 11, 12, 14, 17-19 and 21-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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Prosecution Timeline

Show 6 earlier events
May 14, 2025
Response after Non-Final Action
Jun 16, 2025
Non-Final Rejection mailed — §103
Sep 23, 2025
Response Filed
Dec 29, 2025
Final Rejection mailed — §103
Feb 26, 2026
Response after Non-Final Action
Apr 29, 2026
Request for Continued Examination
May 04, 2026
Response after Non-Final Action
Jul 29, 2026
Non-Final Rejection mailed — §103 (current)

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SEMICONDUCTOR DEVICE STRUCTURE
3y 9m to grant Granted May 19, 2026
Patent 12635124
VERTICALLY STACKED STORAGE NODES AND ACCESS DEVICES WITH VERTICAL ACCESS LINES
3y 9m to grant Granted May 19, 2026
Patent 12624993
SENSING DEVICE AND METHOD FOR FABRICATING THE SAME
3y 8m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
60%
Grant Probability
69%
With Interview (+8.7%)
3y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 427 resolved cases by this examiner. Grant probability derived from career allowance rate.

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