Prosecution Insights
Last updated: October 02, 2026
Application No. 17/874,582

COMPUTATIONAL METROLOGY BASED CORRECTION AND CONTROL

Non-Final OA §103
Filed
Jul 27, 2022
Priority
Dec 19, 2017 — provisional 62/607,777 +3 more
Examiner
WHITESELL, STEVEN H
Art Unit
1759
Tech Center
1700 — Chemical & Materials Engineering
Assignee
ASML Holding N.V.
OA Round
5 (Non-Final)
82%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
799 granted / 975 resolved
+16.9% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
41 currently pending
Career history
1016
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 975 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 15, 2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 16-21, 23, 25 and 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over O'Donoghue et al. [US 5,497,381] in view of Satya et al. [US 2002/0187582]. For claims 16 and 31, O'Donoghue teaches a computer program product comprising a non-transitory computer-readable medium having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system (analysis performed by computer 68, see Fig. 7) to at least: obtain a plurality of qualities associated with one or more parameters of an electronic device manufacturing process (serial data bitstreams that are encoded with signature defect patterns 82 associated with functional tests, see col. 7 line 49-col. 9 line 25), each quality being a separate set of data (different bitstreams for different signature defect), each quality associated with a different apparatus or apparatus component and/or with a different characteristic of an apparatus or apparatus component (corresponding defect patterns associated with different fault in manufacturing equipment or processing technique, see col. 5 lines 34-65); filter the plurality of qualities to identify as spatially systematic or non-systematic (systematic or random defect patterns, see col. 7 lines 7-45) one or more contributors of a plurality of contributors, to the one or more parameters, associated with one or more apparatuses used in the device manufacturing process (correlation of defect patterns with different fault in manufacturing equipment or processing technique, see col. 5 lines 34-65), wherein at least one of the contributors is spatially systematic (determined systematic defect, see col. 7 line 49-col. 8 line 4); and map the plurality of contributors to a performance parameter (functional test for different parameters for identifying process faults, see col. 8 line 5 - col. 9 line 25) associated with one or more substrates subject to the device manufacturing process; and cause physical configuration or physical modification of the device manufacturing process based on a result of the mapping and/or output a signal representing, or based on, a result of the mapping to a tool or system for enabling the physical configuration or physical modification of the device manufacturing process (feedback 86 for correction, col. 7 line 49- col. 8 line 4). O'Donoghue fails to teach each quality being a combination of, or derived from, data from a plurality of substrates. Satya teaches each quality being a combination of, or derived from, data from a plurality of substrates (the defect data maps from several wafers across several lots can be stored in a database, and signature analysis applied across the large data set, see [0215]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the signature derived from a plurality of wafer as taught by Satya in the signature defect pattern data as taught by O'Donoghue in order to detect low level signatures in the data that are indicative of systematic process yield problems. For claims 17, 18, and 32, O'Donoghue teaches wherein the plurality of qualities comprise metrology data or are derived from metrology data (bitstreams generated at tester, see Fig. 7), wherein the instructions configured to cause the computer system to filter the plurality of qualities to remove one or more non-systematic contributors to the metrology data (random defects do not trigger flag 76, see Fig. 7 and col. 7 lines 38-47). For claim 19, O'Donoghue teaches each contributor out of the plurality of contributors is a systematic contributor to the metrology data (known systematic defect patterns for different processing faults, see col. 5 lines 35-65 and col. 7 line 49-col. 8 line 5). For claims 20 and 33, O'Donoghue teaches each quality out of the plurality of qualities relates to an individual contributor to the parameter (defect pattern analyses could be performed for each different level of functional tests, see col. 9 lines 15-25). For claims 21 and 34, O'Donoghue teaches the performance parameter is the same as the parameter of the device manufacturing process (functional tests determine defects and generate bitstream, see Figs. 1-5 and 8-10). For claim 23, O'Donoghue fails to teach the performance parameter is selected from: overlay, critical dimension (CD), edge placement error (EPE), focus, and/or dose. Satya teaches the performance parameter is selected from: overlay (see [0171]-[0176]), critical dimension (CD), edge placement error (EPE), focus, and/or dose. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide overlay performance parameters as taught by Satya in the functional testing as taught by O'Donoghue in order to classify defects associated with patterning between layers. For claim 25, O'Donoghue teaches the instructions are further configured to cause the computer system to determine a control metric based on the mapping of the contributors to the performance parameter, wherein the control metric is configured to be used in a control loop of the device manufacturing process (feedback control based on defect analysis, see Fig. 7 and col. 7 line 49- col. 8 line 4). Claims 22, 27-30, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over O'Donoghue in view of Satya as applied to claims 16 and 31 above, and further in view of Hu et al. [US 2018/0173110]. For claims 22, 27-30, and 35, O'Donoghue fails to teach the instructions configured to cause the computer system to filter the plurality of qualities are further configured to cause the computer system to filter the plurality of qualities based on prior contributor information or prior qualities associated with one or more prior substrates processed by the device manufacturing process, the plurality of qualities is one or more corrections corresponding to a plurality of parameter maps of the device manufacturing process for a lot of substrates processed during the device manufacturing process, each parameter map of the plurality of parameter maps being generated from metrology data and from data of the one or more apparatuses used in the device manufacturing process, wherein the parameter maps each relate to an individual contributor to the device manufacturing process, and the instructions are further configured to cause the computer system to determine a consistency characteristic for each parameter map based on a comparison of parameter maps relating to different layers and/or substrates processed during the device manufacturing process, wherein the instructions are further configured to cause the computer system to determine whether a contributor is systematic based on the consistency characteristic. Hu teaches the instructions configured to cause the computer system (see Figs. 1 and 2) to filter the plurality of qualities are further configured to cause the computer system to filter the plurality of qualities based on prior contributor information or prior qualities associated with one or more prior substrates processed by the device manufacturing process (reference overlay error from previous measurements used for filtering, see [0018] and [0042] and Fig. 2), the plurality of qualities is one or more corrections corresponding to a plurality of parameter maps of the device manufacturing process for a lot of substrates processed during the device manufacturing process (generated correction maps, see [0018] and Fig. 5), each parameter map of the plurality of parameter maps being generated from metrology data and from data of the one or more apparatuses used in the device manufacturing process (overlay error maps, see [0018]-[0020] Fig. 5), wherein the parameter maps each relate to an individual contributor to the device manufacturing process (reticle effects, see [0035] and [0036]), and the instructions are further configured to cause the computer system to determine a consistency characteristic for each parameter map based on a comparison of parameter maps relating to different layers and/or substrates processed during the device manufacturing process (identifying non-systematic noise error in overlay between layers for wafer to wafer inconsistency, see [0037]), wherein the instructions are further configured to cause the computer system to determine whether a contributor is systematic based on the consistency characteristic (identifying the consistent characteristics that are systematic and those which are not, see [0035]-[0037]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the overlay error mapping as the qualities for determining contributions to overlay error as taught by Hu in the correlation of contributing process systems as taught by O'Donoghue, because the overlay error allows for determining reticle alignment error between exposures and using that information to separate systematic error and non-systematic error to perform wafer to wafer or batch to batch corrections. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over O'Donoghue in view of Satya as applied to claim 16 above, and further in view of Jeong [US 2015/0043803]. For claim 24, O'Donoghue fails to teach the instructions configured to cause the computer system to map the plurality of contributors to the performance parameter are further configured to cause the computer system to weight each contributor out of the plurality of contributors based on its degree of being systematic. Jeong teaches the instructions configured to cause the computer system to map the plurality of contributors to the performance parameter are further configured to cause the computer system to weight each contributor out of the plurality of contributors based on its degree of being systematic (assign larger weights to the terms with low noise measured images and smaller weights to the terms with noisy measured images, see [0136]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to assign different weights based on the contribution of the element as taught by Jeong in the determined contributors as taught by O'Donoghue in order to increase the accuracy and impact of the correction. Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over O'Donoghue in view of Satya as applied to claim 16 above, and further in view of Ten Berge [WO 2017/067765]. For claim 26, O'Donoghue teaches the instructions configured to cause the computer system to filter the plurality of qualities are configured to cause the computer system to filter the plurality of qualities based on a correction potential in the device manufacturing process (the bin distribution is also useful in recategorizing a specific die which satisfies some but not all of the various tests, and can be used for applications which have relaxed specifications, see col. 2 lines 55-65 and col. 8 lines 56-60), but fails to teach the instructions configured to cause the computer system to filter the plurality of qualities are configured to cause the computer system to filter the plurality of qualities based on a correction potential of an apparatus used in the device manufacturing process. Ten Berge teaches the instructions configured to cause the computer system to filter the plurality of qualities are configured to cause the computer system to filter the plurality of qualities based on a correction potential of an apparatus used in the device manufacturing process (certain modification apparatuses of the patterning system 300 may be better able to correct certain types of error and so the error correction is appropriately weighted or apportioned among the suitable different modification apparatuses of the patterning system 300, see [0088]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to assign different weights based ability to perform correction as taught by Ten Berge in the filtered defects as taught by O'Donoghue in order to ensure that the error correction can be adequately performed and thereby increase accuracy. Response to Arguments Applicant’s arguments with respect to claims 16 and 31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Guldi et al. [US 2007/0038325], Kulkarni et al. [US 5,991,699], Steffan et al. [US 6,303,394], Shibuya et al. [US 2002/0181756], Tanaka et al. [US 2003/0054573], Buckheit et al. [US 2003/0055592], Luu et al. [US 7,229,845], Lin et al [US 2014/0355867], Hauptmann et al. [WO 2016/087069], and Milligan et al. [US 2018/0330493] each teach systems for identifying systematic defects based on pattern maps. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven H Whitesell whose telephone number is (571)270-3942. The examiner can normally be reached Mon - Fri 9:00 AM - 5:30 PM (MST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Curt Mayes can be reached at 571-272-1234. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Steven H Whitesell/Primary Examiner, Art Unit 1759
Read full office action

Prosecution Timeline

Show 4 earlier events
Jan 09, 2025
Request for Continued Examination
Jan 13, 2025
Response after Non-Final Action
Apr 15, 2025
Non-Final Rejection mailed — §103
Oct 10, 2025
Response Filed
Dec 23, 2025
Final Rejection mailed — §103
Jun 15, 2026
Request for Continued Examination
Jun 16, 2026
Response after Non-Final Action
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
82%
Grant Probability
95%
With Interview (+12.9%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 975 resolved cases by this examiner. Grant probability derived from career allowance rate.

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