Prosecution Insights
Last updated: May 29, 2026
Application No. 17/874,582

COMPUTATIONAL METROLOGY BASED CORRECTION AND CONTROL

Final Rejection §101§103
Filed
Jul 27, 2022
Priority
Dec 19, 2017 — provisional 62/607,777 +3 more
Examiner
WHITESELL, STEVEN H
Art Unit
1759
Tech Center
1700 — Chemical & Materials Engineering
Assignee
ASML Netherlands B.V.
OA Round
4 (Final)
82%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
782 granted / 956 resolved
+16.8% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
37 currently pending
Career history
1004
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
78.8%
+38.8% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 956 resolved cases

Office Action

§101 §103
DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 16-23 and 25-35 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. [US 2004/0167748] in view of Hu et al. [US 2018/0173110]. For claims 16 and 31, Zhang teaches a computer program product comprising a non-transitory computer-readable medium (see Fig. 2 and [0040]) having instructions therein, the instructions, when executed by a computer system, configured to cause the computer system to at least: obtain a plurality of qualities associated with a one or more parameter of an electronic device manufacturing process (error associated with metrology data set collected by the data collector 130 associated with exposure of the wafer 28, see [0026]-[0030]), each quality from data associated with a different apparatus or apparatus component and/or with a different characteristic of an apparatus or apparatus component (source error from wafer set data associated with source 20 signature and lens error of the data associated with the lens 22 signature, see [0047]); filter the plurality of qualities to obtain a plurality of contributors, to the one or more parameters, (filtered data from the data filter 132 used to isolate errors associated with specific apparatus element in the slit direction, see [0031]-[0039] and [0044]) associated with one or more apparatuses used in the device manufacturing process, wherein at least one of the contributors is spatially systematic (scan invariant illumination source and lens vary across the slit direction, see [0016], [0018], and [0039]); map the plurality of contributors to a performance parameter associated with one or more substrates subject to the device manufacturing process (correlating critical dimension errors of wafer 38 to causal factors such as scan dynamics, illumination uniformity, and lens aberrations, see [0013], [0025], [0028], [0039], and [0044]); and cause physical configuration or physical modification of the device manufacturing process based on a result of the mapping and/or output a signal representing, or based on, a result of the mapping to a tool or system for enabling the configuration or modification of the device manufacturing process (system 110 may be used to provide real-time analysis of exposure tool 10 that may be used to monitor and adjust production processes, see [0044]). Zhang fails to teach the plurality of qualities is obtained from data from a plurality of substrates. Hu teaches the plurality of qualities is obtained from data from a plurality of substrates (using overlay errors from previous measurements from a single or a plurality of wafers in one lot, see [0018]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use measurement data form a plurality of wafers as taught by Hu in the correlation of contributing process systems as taught by Zhang in order to capture variations in error over time or to generate combination error maps that emphasize error distribution to identify system error trend. For claims 17, 18, and 32, Zhang teaches wherein the plurality of qualities comprise metrology data or are derived from metrology data (see [0026]-[0030] and Figs. 1 and 2), wherein the instructions configured to cause the computer system to filter the plurality of qualities are configured to cause the computer system to remove non-systematic contributors to the metrology data (reduces the data to the slit direction in accordance with the image field errors, and separates errors caused by other factors in order to determine across-slit errors such as errors associated with lens 22 or source 20, see [0039]). For claim 19, Zhang teaches each contributor out of the plurality of contributors is a systematic contributor to the metrology data (scan variant errors, errors that occur in the scan direction are reduced and may be dealt with separately, see [0025], [0039], and [0044]). For claims 20 and 33, Zhang teaches each quality out of the plurality of qualities relates to an individual contributor to the parameter (CD errors in X and Y direction relate to different contributors, see [0013], [0025], and [0039]). For claims 21 and 34, Zhang teaches the performance parameter is the same as the parameter of the device manufacturing process (critical dimension, see [0025], [0039], and [0044]). For claim 23, Zhang teaches the performance parameter is selected from: overlay, critical dimension (CD) (see [0013], [0025], [0039], and [0044]), edge placement error (EPE), focus, and/or dose. For claim 25, Zhang teaches the instructions are further configured to cause the computer system to determine a control metric based on the mapping of the contributors to the performance parameter, wherein the control metric is configured to be used in a control loop of the device manufacturing process (system 110 may be used to provide real-time analysis of exposure tool 10 that may be used to monitor and adjust production processes in order to reduce critical dimension errors, see [0044]). For claim 26, Zhang teaches the instructions configured to cause the computer system to filter the plurality of qualities are configured to cause the computer system to filter the plurality of qualities based on a correction potential of an apparatus used in the device manufacturing process (weighted based on data quality increases correction potential, see [0032], weighting iteration stop when correction potential converges, see [0038]). For claims 22, 27-30, and 35, Zhang fails to teach the instructions configured to cause the computer system to filter the plurality of qualities are further configured to cause the computer system to filter the plurality of qualities based on prior contributor information or prior qualities associated with one or more prior substrates processed by the device manufacturing process, the plurality of qualities is one or more corrections corresponding to a plurality of parameter maps of the device manufacturing process for a lot of substrates processed during the device manufacturing process, each parameter map of the plurality of parameter maps being generated from metrology data and from data of the one or more apparatuses used in the device manufacturing process, wherein the parameter maps each relate to an individual contributor to the device manufacturing process, and the instructions are further configured to cause the computer system to determine a consistency characteristic for each parameter map based on a comparison of parameter maps relating to different layers and/or substrates processed during the device manufacturing process, wherein the instructions are further configured to cause the computer system to determine whether a contributor is systematic based on the consistency characteristic. Hu teaches the instructions configured to cause the computer system (see Figs. 1 and 2) to filter the plurality of qualities are further configured to cause the computer system to filter the plurality of qualities based on prior contributor information or prior qualities associated with one or more prior substrates processed by the device manufacturing process (reference overlay error from previous measurements used for filtering, see [0018] and [0042] and Fig. 2), the plurality of qualities is one or more corrections corresponding to a plurality of parameter maps of the device manufacturing process for a lot of substrates processed during the device manufacturing process (generated correction maps, see [0018] and Fig. 5), each parameter map of the plurality of parameter maps being generated from metrology data and from data of the one or more apparatuses used in the device manufacturing process (overlay error maps, see [0018]-[0020] Fig. 5), wherein the parameter maps each relate to an individual contributor to the device manufacturing process (reticle effects, see [0035] and [0036]), and the instructions are further configured to cause the computer system to determine a consistency characteristic for each parameter map based on a comparison of parameter maps relating to different layers and/or substrates processed during the device manufacturing process (identifying non-systematic noise error in overlay between layers for wafer to wafer inconsistency, see [0037]), wherein the instructions are further configured to cause the computer system to determine whether a contributor is systematic based on the consistency characteristic (identifying the consistent characteristics that are systematic and those which are not, see [0035]-[0037]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the overlay error mapping as the qualities for determining contributions to overlay error as taught by Hu in the correlation of contributing process systems as taught by Zhang, because the overlay error allows for determining reticle alignment error between exposures and using that information to separate systematic error and non-systematic error (see [0035]-[0037] of Zhang). Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Jeong [US 2015/0043803]. For claim 24, Zhang fails to teach the instructions configured to cause the computer system to map the plurality of contributors to the performance parameter are further configured to cause the computer system to weight each contributor out of the plurality of contributors based on its degree of being systematic. Jeong teaches the instructions configured to cause the computer system to map the plurality of contributors to the performance parameter are further configured to cause the computer system to weight each contributor out of the plurality of contributors based on its degree of being systematic (assign larger weights to the terms with low noise measured images and smaller weights to the terms with noisy measured images, see [0136]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to assign different weights based on the contribution of the element as taught by Jeong in the determined contributors as taught by Zhang in order to increase the accuracy and impact of the correction. Response to Arguments Applicant’s arguments with respect to the rejection under 35 U.S.C. 101 of claims 16-35 on pages 7-11 of the Remarks, filed on October 10, 2025, have been considered but are moot. The claimed application of the abstract idea, “cause physical configuration or physical modification of the device manufacturing process based on a result of the mapping and/or output a signal representing, or based on, a result of the mapping to a tool or system for enabling the physical configuration or physical modification of the device manufacturing process” as recited in claim 16 and “applying a result of the mapping to configure or modify the device manufacturing process and/or outputting a signal representing, or based on, a result of the mapping to a tool or system for enabling the configuration or modification of the device manufacturing process” as recited in claim 31, provides for the disclosed improvement of accuracy and consistency of patterning of the substrates in successive lots. The rejection under 35 U.S.C. 101 of claims 16-35 has been withdrawn. Applicant's arguments on pages 11-13 regarding the prior art rejections of claims 16 and 31 have been fully considered but they are not persuasive. The Applicant argues that Zhang and Hu fails to teach the claim limitation: obtain a plurality of qualities associated with one or more parameters of a device manufacturing process, each quality from data from a plurality of substrates and associated with a different apparatus or apparatus component and/or with a different characteristic of an apparatus or apparatus component; and that Hu does not teach a single overlay correction map is from "a plurality of wafers in one lot." The Examiner respectfully disagrees. Zhang teaches in Figs. 1 and 3 an error is derived from measurement data and the error is associated with lens error and source error, where the lens 22 and source 20 are components of a lithographic apparatus. Hu is currently not relied upon to teach a single overlay correction map. Hu is relied upon to teach corrections based on errors extracted from measurements from a plurality of wafers. Further, there is no claim limitation to a single overlay correction map. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kamo [US 2012/0141927] teaches recognition of systematic errors based on an overlay map. Amit et al. [US 2015/0316490] teaches estimating systematic error and determining the source. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven H Whitesell whose telephone number is (571)270-3942. The examiner can normally be reached Mon - Fri 9:00 AM - 5:30 PM (MST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Duane Smith can be reached at 571-272-1166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Steven H Whitesell/Primary Examiner, Art Unit 1759
Read full office action

Prosecution Timeline

Show 1 earlier event
Mar 14, 2024
Non-Final Rejection mailed — §101, §103
Apr 30, 2024
Response Filed
Aug 15, 2024
Final Rejection mailed — §101, §103
Jan 09, 2025
Request for Continued Examination
Jan 13, 2025
Response after Non-Final Action
Apr 15, 2025
Non-Final Rejection mailed — §101, §103
Oct 10, 2025
Response Filed
Dec 23, 2025
Final Rejection mailed — §101, §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
82%
Grant Probability
95%
With Interview (+13.3%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 956 resolved cases by this examiner. Grant probability derived from career allowance rate.

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