Prosecution Insights
Last updated: October 27, 2026
Application No. 17/874,709

BUILT-IN TEMPERATURE SENSORS

Non-Final OA §103§112
Filed
Jul 27, 2022
Examiner
FARMER, EMILY NICOLE
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries U S Inc.
OA Round
4 (Non-Final)
90%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
46 granted / 51 resolved
+22.2% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
19 currently pending
Career history
71
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
56.3%
+16.3% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 51 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-5, 7-13, and 15-20 are pending. Claims 1, 2, 4, 7-13, and 15-20 are amended. Claims 6 and 14 are cancelled. Claim 20 is withdrawn. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/12/2026 has been entered. Specification The amendment filed 08/12/2026 and entered 08/27/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Replacement Fig. 4 introduces new matter into the disclosure. Replacement Fig. 4 appears to show two side-by-side built-in temperature sensors, only one of which was pictured in any of the prior figures. Additionally, where all prior figures have only shown a single horizontal wiring line across the top and bottom of the temperature sensing device, the replacement figure shows two horizontal wiring lines across both the top and bottom of the device. Additionally, over the right-most and left-most wiring lines (24h), a new feature has been added in the center of the source/drain area that is not present in any previously presented figures. Additionally, replacement Fig. 4 appears to change the right-most and left-most “floating gate structures” 24a, which previously directly connected to the force line, sensing line, current supply, and current discharge with a vertical wiring line 24h disposed to connect 24a’ to the force line, sensing line, current supply, and current discharge. These amendments are not found nor supported by the prior disclosure of the invention. Applicant is required to cancel the new matter in the reply to this Office Action. Drawings The drawing objections of the final rejection mailed 06/15/2026 are maintained. The drawings are objected to under 37 CFR 1.83(a) because they fail to show metal wiring lines as described in the specification. The metal wiring line terminals (shown in Fig. 4 as 24c) of the figures appear to be visually obstructed by the wiring lines (for example, 24e and 24d of Figs. 1-4). Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Amendment of claims 1, 2, 4, 5, 7-13, and 15-19 to remove the term “floating” overcomes the rejection of claims 1-5, 7-13, and 15-19 under 35 U.S.C. 112(b) of 06/15/2026. The rejection is withdrawn. Claims 1-5, 7-13, and 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “gate structures” in claims 1 and 10 are used by the claim to mean “polysilicon or conductive material used for a resistive temperature sensor,” while the accepted meaning is “conductive material formed above the channel of a transistor which controls current flow through a transistor, allowing transistors to function as electronic switches.” The term is indefinite because the specification does not clearly redefine the term. The specification of the instant application reads, paragraph 0016, wherein optional floating gate structures may be planar structures and/or finFET structures using bulk substrate or SOI technologies, however these do not refer to the “floating gate structures” which are used to form the temperature sensor. Paragraph 0018 reads that those floating gate structures 24a, which refer to the gate structures used to form the temperature sensor “may comprise polysilicon material and may be fabricated during the fabrication processes of the active gate structures 12 and optional floating gate structures 22,” but no disclosure is made which would lead one of ordinary skill in the art to the conclusion that the “gate structures” (24a) are, in any way, gates. Additionally, no further disclosure is made to appropriately redefine the term from its known meaning in the art. For the purposes of examination, the temperature-sensing “gate structures” will be interpreted as polysilicon or otherwise conductive structures formed on a same device level as the active and optional floating gate structures, as disclosed by at least paragraph 0018 of the specification. Response to Arguments/Amendments Applicant's arguments filed 08/12/2026 and entered 08/27/2026 have been fully considered but they are not persuasive. Specifically, amendment of the independent claims 1 and 10 to include the claim limitation “to provide an electrical current path through the multiple temperature-sensing gate structures” and “electrically separated from the at least one active gate structure” fails to overcome the prior art rejection of record. Mahon (US PGPub 2019/0028065) in view of Feng (2018/0038742) teach wherein width-spanning temperature sensing structures would be electrically connected in order to measure temperature across the length of a device at desired intervals. Connection by wiring lines of the sensors of Mahon would not create an unexpected result, and one of ordinary skill would be motivated to connect them in this way to achieve the serpentine structure of Feng in order to enable measurement of the heating effect of the entire device, as described by Feng. Additionally, Mahon teaches wherein the temperature sensing gate structure is separated from the active gate by an insulating layer. The rejections of 06/15/2026 are maintained. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 8-12, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mahon et al. (US PGPub 2019/0028065), herein Mahon, and further in view of Feng et al. (US PGPub 2018/0038742), herein Feng. Regarding claim 1, Mahon teaches (Fig. 2B) a structure comprising: at least one active gate structure (145); and a built-in temperature sensor (147) adjacent to and on a same device level as the at least one active gate structure (145, [0060]), the built-in temperature sensor further comprising force lines (210a, 210b) and sensing lines (212a, 212b), wherein the built-in temperature sensor comprises temperature-sensing gate structures (147, [0062]) electrically separated from the at least one active gate structure (separated by insulating layer 122, [0060]) surrounding multiple active gate structures (145, [0062]), and wiring lines (210a, 210b, 212a, 212b, [0063]) connecting to the multiple temperature-sensing gate structures to provide an electrical current path through the multiple temperature-sensing gate structures and the wiring line ([0066]). Mahon does not explicitly teach in a serpentine configuration. Feng teaches (Fig. 2) a built-in temperature sensor (208, [0026]) in a serpentine configuration ([0030]), wherein force and sensing lines (2091, 2091, [0049]) are located at end points of the serpentine structure (4-point Kelvin detection is described as an appropriate embodiment, [0049]). Because Mahon and Feng are both directed toward built-in temperature sensing of semiconductor devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mahon and Feng to include a serpentine configuration, in order to allow for resistive temperature measurement across extended device features (i.e. the gate lines of Feng, [0030]). Regarding claim 2, Mahon in view of Feng teaches (Mahon, Fig. 2B) the structure of claim 1, wherein the built-in temperature sensor comprises temperature-sensing gate structures (147, [0060]) which are connected to the force lines (210a, 210b, [0063]) and sensing lines (212a, 212b, [0063]). Regarding claim 3, Mahon in view of Feng teaches (Mahon, Fig. 2B) the structure of claim 1, wherein the built-in temperature sensor (147) is parallel to the at least one active gate structure (145, [0054]). Regarding claim 8, Mahon in view of Feng teaches the structure of claim 1, but does not explicitly teach wherein the built-in temperature sensor comprises multiple temperature-sensing gate structures surrounding inner active gate structures. Mahon teaches a further embodiment wherein multiple temperature-sensing gate structures (147) may be formed along an array of a few transistors in a device ([0062]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Mahon to include wherein the built-in temperature sensor comprises multiple temperature-sensing gate structures surrounding inner active gate structures for the purpose of sampling more representative temperatures across the gate array ([0062]). Regarding claim 9, Mahon in view of Feng teaches the structure of claim 8, wherein the force lines (210a, 210b) and the sense lines (212a, 212b) connect to a single (147) of the multiple temperature-sensing gate structures ([0062]). Regarding claim 10, Mahon teaches (Fig. 2B, adjacent structures not pictured) a structure comprising: a plurality of adjacent active gate structures (145, [0062]); and a built-in temperature sensor comprising a plurality of temperature-sensing gate structures (147, [0062]) electrically separated from the at least one active gate structure (separated by insulating layer 122, [0060]) within source/drain regions (162, 160, [0054]) of selective active gates of the plurality of active gate structures, and wiring lines (210a, 210b, 212a, 212b, [0063]) connecting to the multiple temperature-sensing gate structures to provide an electrical current path through the multiple temperature-sensing gate structures and the wiring line ([0066]). Mahon does not explicitly teach in a serpentine configuration. Feng teaches (Fig. 2) a built-in temperature sensor (208, [0026]) in a serpentine configuration ([0030]), wherein force and sensing lines (2091, 2091, [0049]) are located at end points of the serpentine structure (4-point Kelvin detection is described as an appropriate embodiment, [0049]). Because Mahon and Feng are both directed toward built-in temperature sensing of semiconductor devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mahon and Feng to include a serpentine configuration, in order to allow for resistive temperature measurement across extended device features (i.e. the gate lines of Feng, [0030]). Regarding claim 11, Mahon in view of Feng teaches (Mahon, Fig. 2B) the structure of claim 10, wherein at least one of the temperature-sensing gate structures (147) connect to the force lines (210a, 210b) and sensing lines (212a, 212b, [0063]). Regarding claim 12, Mahon in view of Feng teaches (Mahon, Fig. 2B, adjacent structures not pictured) the structure of claim 10, wherein the plurality of temperature-sensing gate structures (147, [0062]) are parallel to and surround the plurality of adjacent active gate structures (145, [0062]). Regarding claim 16, Mahon in view of Feng teaches (Mahon, Fig. 2A, cross-section of Fig. 2B) the structure of claim 10, wherein the plurality of temperature-sensing gate structures (147, [0060]) and the plurality of active gate structures (145, [0060]) are on a same device level ([0060]). Regarding claim 17, Mahon in view of Feng teaches (Mahon, Fig. 2B) the structure of claim 10, wherein the force lines (210a, 210b, [0063]) and sensing lines (212a, 212b, [0063]) extend from a same temperature-sensing gate structure (147, [0062]) of the plurality of temperature-sensing gate structures ([0062]). Regarding claim 19, Mahon in view of Feng teaches (Mahon, Fig. 2B) the structure of claim 10, wherein the built-in temperature sensor comprises multiple temperature-sensing gate structures (147, [0062]) surrounding inner active gate structures (145, [0062]). Claims 4, 5, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mahon in view of Feng as applied to claims 1 and 10 above, and further in view of Pihet et al. (US PGPub 2003/0210507), herein referred to as Pihet. Regarding claim 4, Mahon in view of Feng teaches the structure of claim 1, but does not explicitly teach wherein the built-in temperature sensor comprises two temperature-sensing gate structures surrounding a single active gate structure. Pihet teaches (Fig. 5) wherein the built-in temperature sensor comprises two temperature-sensing gate structures (Ga, Gc, [0044]) surrounding a single active gate structure (Gb, [0044]). Because Mahon in view of Feng and Pihet are both directed toward resistive temperature sensing of a memory device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mahon in view of Feng and of Pihet in order to allow for temperature sensing at temperature-critical locations of the transistor (Pihet, [0044]). Regarding claim 5, Mahon in view of Feng and Pihet teaches the structure of claim 4, and further teaches (Mahon, Fig. 2B) wherein the two temperature-sensing gate structures are located between source/drain regions (162, 160, [0054]) of the single active gate structure (145, [0062]). Regarding claim 13, Mahon in view of Feng teaches the structure of claim 10, but does not explicitly teach wherein the plurality of temperature-sensing gate structures surround a single active gate structure. Pihet teaches (Fig. 5) wherein the plurality of temperature-sensing gate structures (Ga, Gb, Gd, Ge, [0044]) surrounds a single active gate structure (Gc, [0044]). Pihet teaches wherein the number and position of temperature-sensing gate structures surrounding an active gate can be chosen for appropriate temperature measurement ([0044]). A person of ordinary skill in the art would understand that this would include a configuration in which multiple temperature-sensing gates surrounded an single active gate structure. Because Mahon in view of Feng and Pihet are both directed toward resistive temperature measurement of memory devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mahon in view of Feng and of Pihet to include wherein the plurality of temperature-sensing gate structures surround a single active gate structure in order to provide temperature sensing at particularly temperature-critical locations of the transistor (Pihet, [0044]). Regarding claim 18, Mahon in view of Feng teaches the structure of claim 10, but does not explicitly teach wherein the plurality of temperature-sensing gate structures are provided at opposing ends of the plurality of active gate structures. Pihet teaches (Fig. 5) wherein the plurality of temperature-sensing gate structures (Ga, Gn, [0044]) are provided at opposing ends of the plurality of active gate structures (Gb, Gc, Gd, Ge [0044]). Pihet teaches wherein the number and position of temperature-sensing gate structures surrounding an active gate can be chosen for appropriate temperature measurement ([0044]). A person of ordinary skill in the art would understand that this would include a configuration in which temperature-sensing gate structures are provided at opposing ends of a plurality of active gate structures. Because Mahon in view of Feng and Pihet are both directed toward resistive temperature measurement of memory devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mahon in view of Feng and of Pihet to include wherein the plurality of temperature-sensing gate structures surround a single active gate structure in order to provide temperature sensing at particularly temperature-critical locations of the transistor (Pihet, [0044]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Mahon in view of Feng as applied to claim 10 above, and further in view of Steinmann et al. (US PGPub 2019/0319180), herein referred to as Steinmann. Regarding claim 15, Mahon in view of Feng teaches the structure of claim 10, but does not explicitly teach further comprising wiring lines connecting the plurality of temperature-sensing gate structures. Mahon in view of Feng also teaches (Mahon, Fig. 3, a circuit view of the embodiments of Fig. 2B), the temperature-sensing gate structure (147) in electrical series with resistive elements for temperature sensing. Mahon in view of Feng teaches wherein multiple temperature-sensing gate structures can be arranged on a single device for temperature sensing and shows in Fig. 3 where only one input/output line is provided for temperature-sensing gates, but does not explicitly depict wiring lines connecting the plurality of temperature-sensing gate structures. Steinmann teaches (Fig. 2) use of conductive strips or connections (24, [0023]) for electrical connection of conductive silicon elements (16, 18, [0023]) in a transistor device (22, [0023]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the conductive strips of Steinmann to provide electrical connections to the multiple temperature-sensing gate structures of Mahon in view of Feng for the predictable result of creating electrical bridging between multiple conductive structures. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY FARMER/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Show 6 earlier events
Dec 15, 2025
Non-Final Rejection (signed) — §103, §112
Jan 16, 2026
Non-Final Rejection mailed — §103, §112
Apr 16, 2026
Response Filed
Jun 15, 2026
Final Rejection mailed — §103, §112
Aug 12, 2026
Response after Non-Final Action
Aug 27, 2026
Request for Continued Examination
Sep 02, 2026
Response after Non-Final Action
Oct 14, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772590
IMAGE SENSOR AND METHOD OF FABRICATING THE SAME
2y 10m to grant Granted Oct 20, 2026
Patent 12765026
INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Oct 13, 2026
Patent 12757403
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
3y 2m to grant Granted Oct 06, 2026
Patent 12751028
LASER RECOVERY OF A CORE LAYER OF A TEMPORARY CARRIER STRUCTURE
3y 6m to grant Granted Sep 29, 2026
Patent 12733324
MICRO LIGHT-EMITTING DIODE (LED) STRUCTURE
2y 6m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.2%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 51 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month