DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0226349 A1 (Yu) further in view of US 2018/0076112 A1 (Dabral).
Re claim 1, Yu teaches a method, comprising:
forming a redistribution layer (RDLS in redistribution structure 114 [0019-0020]) on a device die (Fig. 3);
encasing the redistribution layer in an encapsulant ([0020]) to form a redistribution circuit structure (redistribution structure 114) of the device die;
forming electrical connectors (conductive connectors 122) on a first surface of the device die (Fig. 5);
connecting the electrical connectors to a second surface of the device die by a through-silicon via (TSV) (TSVs 126) in the device die to form an interconnection device die (Fig. 6);
and arranging a plurality of system on integrated chip (SOIC) device dice (integrated device die 104A, 104B) on the first surface of the interconnection device die, wherein arranging the plurality of SOIC device dice comprises arranging a memory cell and a processor coupled to each other ([0013] Fig. 10).
Yu does not explicitly teach wherein arranging the plurality of SOIC device dice comprises arranging a memory cell, a first processor and a second processor coupled to each other. However, Yu does teach that more of the integrated circuit dies may be adhered to the carrier substrate and that the integrated device die are connected to each other.
Dabral teaches a memory system wherein a memory chip is mounted and connected to a first processor (CPU) and second processor (GPU) and wherein the first and second processor are connected to each other.
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It would have been obvious to one of ordinary skill in the art to form the package of Yu having the memory connected to multiple processors. The motivation to do so is that CPUs implement general purpose instruction sets and GPUs implement graphics instruction sets and both are connected to the memory which holds the data required to implement any instruction set. Furthermore, the courts have found that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04 (VI)(B)).
Re claim 2, Yu teaches wherein connecting the electrical connectors to the second surface of the device die comprises forming a connection path between the second surface of the interconnection device die and one or more of the electrical connector and the redistribution circuit structure (Fig. 10).
Re claim 3, Yu teaches wherein connecting the electrical connectors to the second surface of the device die comprises forming a channel in the device die to couple the electrical connectors to the second surface of the device die opposite to the first surface of the interconnection device die (Fig. 10).
Re claim 4, Tsai teaches wherein arranging the plurality of SOIC device dice comprises arranging at least one three dimensional integrated circuit (3DIC) die (104B can be a HBM which is a 3DIC of stacked memory dies [0013]) on the first surface of the interconnection device die (Fig. 10).
Re claim 8, Yu teaches a method, comprising:
forming an interconnection device die (see annotated Fig. 10) comprising a redistribution circuit structure (RDLS in redistribution structure 114 [0019-0020]) and a plurality of electrical connectors (bumps 134) coupled by a through-silicon via (TSV) (TSVs 126);
arranging a plurality of device dice (integrated device die 104A, 104B) on the interconnection device die, wherein the plurality of device dice comprises a memory die and processor dice ([0011-0013]); and
coupling the plurality of device dice to the interconnection device die via the electrical connectors (Fig. 10).
Yu does not explicitly teach wherein arranging the plurality of SOIC device dice comprises arranging a memory cell, a first processor and a second processor wherein the plurality of device dice comprises a memory die and first and second processer dice, and wherein arranging the plurality of device dice comprises arranging the first processer die between the memory die and the second processer die. However, Yu does teach that more of the integrated circuit dies may be adhered to the carrier substrate and that the integrated device die are connected to each other.
Dabral teaches a memory system wherein a memory chip is mounted and connected to a first processor (GPU) and second processor (CPU) and wherein the first and second processor are connected to each other.
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It would have been obvious to one of ordinary skill in the art to form the package of Yu having the memory connected to multiple processors. The motivation to do so is that CPUs implement general purpose instruction sets and GPUs implement graphics instruction sets and both are connected to the memory which holds the data required to implement any instruction set. Furthermore, the courts have found that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04 (VI)(B)).
Re claim 9, Yu teaches insulating the redistribution circuit structure by embedding conductors therein in an encapsulant (RDLS in redistribution structure 114 [0019-0020]).
Re claim 10, Yu teaches connecting the conductors to conductive terminals (topmost conductors in RDL 114 bonded to die connectors 108) arranged on a first surface (top) of the interconnection device die.
Re claim 11, Yu teaches bonding an electrical connector (die connectors 108) of a three dimensional integrated circuit (3DIC) (integrated device die 104B can be a HBM which is a 3DIC of stacked memory dies [0013]) of the plurality of device dice to a corresponding one of the plurality of electrical connectors of the interconnection device die (Fig. 10).
Re claim 13, Yu teaches connecting the TSV between at least one of the device die at a first surface of the interconnection device die and a second surface of the interconnection device die (Fig. 10).
Re claim 16, Yu teaches wherein the plurality of electrical connectors comprise one or more of ball-type electrical connectors, bump electrical connectors, metal pad electrical connectors, and combinations thereof ([0034] Fig. 10).
Claim(s) 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0226349 A1 (Yu) in view of US 2018/0076112 A1 (Dabral) and further in view of “Three-dimensional integrated circuits”, A.W. Topol et al., IBMJ. Res. & Dev., Vol 50, No. 4/5, July/Sept. 2006 (Topol).
Re claims 5 and 17, Yu and Dabral teach the methods of claims 1 and 8, however Yu is silent with regards to the bonding configuration of the memory dies in the HBM stack.
Topol teaches that stacked die may either be in face-to-face or face-to-back configuration.
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It would have been obvious to one of ordinary skill in the art at the time of the invention to bond the dies in the memory stack using face to back configuration.
The motivation to do so is that the alignment requirements are more relaxed and only requires standard connection lengths for the connecting vias.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0226349 A1 (Yu) in view of US 2018/0076112 A1 (Dabral) and further in view of US 2015/0123270 A1 (Tsukiyama).
Re claims 14 and 15, Yu teaches the method according to claim 8, however, Yu does not explicitly teach wherein a pitch between adjacent electrical connectors in the plurality of electrical connectors is less than or equal to about 9 μm (claim 14), nor wherein a width of each electrical connector of the plurality of electrical connectors is between about 2 μm and about 30 μm (claim 15).
Tsukiyama teaches a pitch for bumps between 10 – 100 μm and the width being between 5 – 50 μm ([0003]).
It would have been obvious to one of ordinary skill in the art at the time of filing to form the bump pitch and width of Yu having the values recited by Tsukiyama.
The motivation to do so is that such pitch and width values allow for miniaturization and high functionality of semiconductor devices for the purposes of scaling while maintaining function.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005); See also In re Baird, 16 F.3d 380, 29 USPQ2d 1550 (Fed. Cir. 1994); In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992) (MPEP 2144.05 (I)).
Allowable Subject Matter
Claims 21-23 are allowed.
Claims 24-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art teaches a method, comprising:
forming a redistribution layer (114) in a device die;
forming a through-silicon via (TSV) (126) in the device die;
forming electrical connectors (topmost conductors in RDL 114) on a first surface of the device die and coupled to the redistribution layer and the TSV;
stacking a first memory die (104B right) on the first surface of the device die, wherein stacking the first memory die comprises coupling first and second terminals of the first memory die with the electrical connectors (Fig. 10);
stacking a second memory die (104B left) on the first surface of the device die, wherein stacking the second memory die comprises coupling a third terminal of the second memory die with the electrical connectors (Fig. 10);
stacking a first processor die (104A) on the first surface of the device die, wherein stacking the first processor die comprises coupling fourth and fifth terminals of the first processor die with the electrical connectors, such that the first and fourth terminals are coupled through the redistribution layer (Fig. 10) (US 2018/0226349 A1 Yu).
However the prior art does not explicitly teach nor render obvious all of the limitations above and additionally stacking a second processor die on the first surface of the device die, wherein stacking the second processor die comprises coupling sixth, seventh, and eighth terminals of the second processor die with the electrical connectors, such that the second and sixth terminals are coupled through the redistribution layer, the third and seventh terminals are coupled through the redistribution layer, and the fifth and eighth terminals are coupled through the redistribution layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on the references as they are being applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896