DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/5/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 8-11, 13, 15-16, 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130285257 A1 (Lee) further in view of US 20150106547 A1 (King).
Re claim 1, Lee teaches a method, comprising:
forming a redistribution layer (metallization structure 112) on a first side (bottom surface) of a device die (device wafer 100);
encasing the redistribution layer in an encapsulant (hermetic barrier formed by passivation layer 120 [0024]) to form a redistribution circuit structure of the device die;
forming electrical connectors (conductive pads 108) on the redistribution layer;
forming, after forming the redistribution layer, a through-silicon via (TSV) (TSVs 142 evolution of method from Figs. 1-21) in the device die to form an interconnection device die (3D interconnect structure 160), wherein the TSV electrically couples the redistribution layer to a second side of the device die (Fig. 21); and
arranging a plurality of system on integrated chip (SOIC) device dice on the first surface of the interconnection device die (Fig. 23 [0034]), wherein arranging the plurality of SOIC device dice comprises arranging memory cells (memory chips 180), and processors (logic chip 160) coupled to each other (Figs. 1-21, 23).
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Lee does not explicitly teach wherein the SOIC comprises a memory cell and a first processor and a second processor coupled to each other. However, Lee does teach that the system on chip can include a variety of chip to chip configurations with suitable chips including a single example of a memory chips 180 coupled to a logic chip 160 (Fig. 23 [0034-0037]).
King teaches a layout of a system on chip wherein there are a memory cell (memory storage device 150), a first processor (memory control device 110) and second processor (memory control device 120) coupled to each other (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time of the invention to make the system layout of King on the interconnect device of Lee.
The motivation to do so is that Lee teaches the details of the interconnection device which facilitates the connection of the chips making up the module/system while providing a single example layout and King teaches an optional module/system layout having high data storage capacity.
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Re claim 2, Lee teaches wherein connecting the electrical connectors to the second surface of the device die comprises forming a connection path between the second surface of the interconnection device die and one or more of the electrical connector and the redistribution circuit structure (Fig. 21).
Re claim 3, Lee teaches wherein connecting the electrical connectors to the second surface of the device die comprises forming a channel in the device die to couple the electrical connectors to the second surface of the device die opposite to the first surface of the interconnection device die (Fig. 21).
Re claim 4, Lee and King further teaches wherein arranging the plurality of SOIC device dice comprises arranging at least one three dimensional integrated circuit (3DIC) die on the first surface of the interconnection device die (Lee teaches stacked memory dies Fig. 23 [0034-0037] and King teaches that at least one of the memory storage devices comprises a vertical stack of memory storage dies [0018]).
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Re claim 8, Lee teaches a method, comprising:
forming an interconnection device die (3D interconnect structure 160) comprising a redistribution circuit structure (metallization structure 112) and a plurality of electrical connectors (landing pads 152) coupled by a through-silicon via (TSV) (TSVs 142);
arranging a plurality of device dice on the interconnection device die, wherein the plurality of device dice comprises first and second memory dice (memory chips 180) and processor die (logic chip 160) (Fig. 23), and coupling the plurality of device dice to the interconnection device die via the electrical connectors ([0034-0037]) (Figs. 1-21 and 23).
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Lee does not explicitly teach wherein arranging the plurality of device dice comprises: arranging the first processor die between the first memory die and the second processor die; and arranging the second processor die between the first processor die and the second memory die.
However, Lee does teach that the system on chip can include a variety of chip to chip configurations with suitable chips including a single example of a memory chips 180 coupled to a logic chip 160 (Fig. 23 [0034-0037]).
King teaches a layout of a system on chip wherein there are a memory cell (memory storage device 150), a first processor (memory control device 110) and second processor (memory control device 120) coupled to each other (Fig. 1).
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It would have been obvious to one of ordinary skill in the art at the time of the invention to make the system layout of King on the interconnect device of Lee.
The motivation to do so is that Lee teaches the details of the interconnection device which facilitates the connection of the chips making up the module/system while providing a single example layout and King teaches an optional module/system layout having high data storage capacity.
Re claim 9, Lee teaches further comprising insulating the redistribution circuit structure by embedding conductors therein in an encapsulant (passivation layer 113).
Re claim 10, Lee teaches further comprising connecting the conductors to conductive terminals (conductive pads 108) arranged on a first surface (bottom surface) of the interconnection device die.
Re claim 11, Lee and King teach further comprising bonding an electrical connector of a three dimensional integrated circuit (3DIC) (Lee teaches stacked memory dies Fig. 23 [0034-0037] and King teaches that at least one of the memory storage devices comprises a vertical stack of memory storage dies [0018]) of the plurality of device dice to a corresponding one of the plurality of electrical connectors of the interconnection device die (Lee [0034-0037]).
Re claim 13, Lee teaches further comprising connecting the TSV between at least one of the device die at a first surface of the interconnection device die and a second surface of the interconnection device die (the TSV facilitates vertical redistribution of the signal routing lines through the interconnection device Fig. 21 and 23 [0034-0037]).
Re claim 15, Lee teaches wherein a width of each electrical connector of the plurality of electrical connectors is between about 2 μm and about 30 μm (20 μm diameter [0033]).
Re claim 16, Lee teaches wherein the plurality of electrical connectors comprise one or more of ball-type electrical connectors, bump electrical connectors, metal pad electrical connectors, and combinations thereof (Fig. 21).
Re claim 28, Lee teaches wherein forming the interconnection device die comprises: forming the redistribution circuit structure in the interconnection device die; and forming the TSV through the interconnection device die (Figs. 1-21).
Claim(s) 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130285257 A1 (Lee) further in view of US 20150106547 A1 (King) and further in view of “Three-dimensional integrated circuits”, A.W. Topol et al., IBMJ. Res. & Dev., Vol 50, No. 4/5, July/Sept. 2006 (Topol).
Re claims 5 and 17, Yu and Dabral teach the methods of claims 1 and 8, however Yu is silent with regards to the bonding configuration of the memory dies in the HBM stack.
Topol teaches that stacked die may either be in face-to-face or face-to-back configuration.
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It would have been obvious to one of ordinary skill in the art at the time of the invention to bond the dies in the memory stack using face to back configuration.
The motivation to do so is that the alignment requirements are more relaxed and only requires standard connection lengths for the connecting vias.
Allowable Subject Matter
Claims 21-23 are allowed.
Claims 24-25 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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