Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 9, 2025 has been entered.
Election/Restrictions
Claims 14-19 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the restriction by telephone conversation on November 19, 2024.
The Examiner notes that claims 1-13 and 20 are examined and claims 14-19 remain withdrawn.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed March 10, 2025. Claims 1-13 and 20 are amended. Claims 14-19 remain withdrawn. The Examiner notes that claims 1-13 and 20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Fong (US Pub 2018/0082989) in view of Burns (US 6,194,247) and Min (US Pub 2015/0048493).
With respect to claim 1, Fong teaches:
A method for mitigating warpage on stacked wafers, the method comprising:
depositing a first warpage compensating layer (Fig. 17B, paragraphs 216-219, “stress compensating layers”) in direct contact with a backside of a first wafer (Fig. 11, paragraph 79, “special wafer 1102” attached to “IC layer n+1 1104” with 1102 of the simplified process flow acting as the “transfer device layer” of paragraph 219, “The stress compensating layers can be formed by direct layer transfer to the transfer device layer backside”);
stacking an active side (1104) of the first wafer (1102 and 1104) on an active side (paragraph 80, layers 1 to n of “Wafer Scale Processing stack 1106”) of the second wafer (1106) to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer (paragraph 81, “Shown last in FIG. 11 is the performance of steps to such as interconnect processing”);
and removing the first warpage compensating layer (“stress compensating layers” attached to 1102) from the backside of the first wafer (paragraph 80 “After bonding, the wafer 1102 can be released”)
Fong is silent to:
removing the second warpage compensating layer from the backside of the second wafer prior to dicing the wafer stack.
depositing a second warpage compensating layer in direct contact with a backside of a second wafer
such that the first warpage compensating layer and the second warpage compensating layer are on opposed ends of the wafer stack;
and removing the second warpage compensating layer from the backside of the second wafer
Burns teaches:
depositing a first warpage compensating layer (material 41) on a backside of a wafer (26)
depositing a second warpage compensating layer (material 44) a backside of the wafer (26).
By combining the teaching of Burns to deposit warpage compensating layers on both sides of a device with the teaching of Fong in which warpage compensating layers are deposited by depositing them in direct contact with a wafer,
Fong/Burns teaches:
depositing a second warpage compensating layer in direct contact with a backside of a second wafer
and removing the second warpage compensating layer from the backside of the second wafer (para. 216-219 of Fong teaches that stress compensating layers are attached to temporary bonding structures to facilitate a bonding process and can be removed after bonding)
such that the first warpage compensating layer and the second warpage compensating layer are on opposed ends of the wafer stack (Burns teaches including warpage structures on both sides of a wafer to prevent warpage when it cools from the formation temperature, Fong teaches bonding multiple wafers.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Burns into the method of Fong to deposit a stress compensating layer onto the second wafer as claimed in the device of Fong and to then remove the second warpage compensating layer from the backside of the second wafer. The ordinary artisan would have been motivated to modify Fong in the manner set forth above for the purpose of retaining a thermal balance throughout the integrated circuit package (column 8, lines 45-54 of Burns) and to minimize the size of the device by removing layers that are no longer necessary.
Min teaches:
dicing the wafer stack (paragraph 84, a sawing process may be performed to dice the resulting structure and form the plurality of the semiconductor packages.)
Although Min does not teach warpage compensating layers and therefore does not explicitly teach removal of warpage compensating layers prior to dicing the wafer stack, it would be obvious to the ordinary artisan when combining the method of Fong/Burns with Min to insert the step of dicing taught by Min after the warpage compensating layers have been removed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Min into the method of Fong/Burns to dice the wafer stack after removing the stress compensating layer. The ordinary artisan would have been motivated to modify Fong in the manner set forth above for the purpose of forming a plurality of semiconductor packages (paragraph 84 of Min), because it would be simpler to remove the warpage compensating layer from one large wafer prior to dicing as compared to removing warpage compensating layers from many small dies, and/or because “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” (MPEP 214.04(IV)(C)).
With respect to claim 5, Fong/Burns/Min further teaches:
wherein a width of the first warpage compensating layer is equal to a width of the first wafer. (Fig. 17B of Fong shows that the stress compensating layer is equal to a width of the surface upon which it is deposited)
In the event that Fong/Burns/Min does not teach the limitation “wherein a width of the first warpage compensating layer is equal to a width of the first wafer,” which the Examiner does not concede, it would be obvious to the ordinary artisan to adjust the width of the warpage compensating layer to be equal to a width of the wafer through optimization within prior art condition or through routine experimentation (MPEP 2144.05(II)(A)) and or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)). The ordinary artisan would know that the warpage compensating characteristics are affected by the amount of area at the interface of the warpage compensating layer and wafer and would be motivated to optimize the width of the layers in relation to each other to tune the stress characteristics of the package during bonding.
With respect to claim 6, Fong/Burns/Min further teaches:
wherein a width of the second warpage compensating layer is equal to a width of the second wafer. (Fig. 17B of Fong shows that the stress compensating layer is equal to a width of the surface upon which it is deposited)
In the event that Fong/Burns/Min don’t teach the limitation “wherein a width of the first warpage compensating layer is equal to a width of the first wafer,” which the Examiner does not concede, it would be obvious to the ordinary artisan to adjust the width of the warpage compensating layer to be equal to a width of the wafer through optimization within prior art condition or through routine experimentation (MPEP 2144.05(II)(A)) and or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)). The ordinary artisan would know that the warpage compensating characteristics are affected by the amount of area at the interface of the warpage compensating layer and wafer and would be motivated to optimize the width of the layers in relation to each other to tune the stress characteristics of the package during bonding.
With respect to claim 7, Fong/Burns/Min further teaches:
wherein a width of the first warpage compensating layer is equal to a width of the first wafer. (Fig. 17B of Fong shows that the stress compensating layer is equal to a width of the surface upon which it is deposited)
In the event that Fong/Burns/Min does not teach the limitation “wherein a width of the first warpage compensating layer is equal to a width of the first wafer,” which the Examiner does not concede, it would be obvious to the ordinary artisan to adjust the width of the warpage compensating layer to be equal to a width of the wafer through optimization within prior art condition or through routine experimentation (MPEP 2144.05(II)(A)) and or because it has been ruled that changes of thickness are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(IV)(A)). The ordinary artisan would know that the warpage compensating characteristics are affected by the amount of area at the interface of the warpage compensating layer and wafer and would be motivated to optimize the width of the layers in relation to each other to tune the stress characteristics of the package during bonding.
With respect to claim 8, Fong further teaches:
stacking an active side of a third wafer (paragraph 81, layer n+2) on the backside of the second wafer (layer n+1) to add to the wafer stack (1106), the circuitry of the third wafer electrically connected to circuitry of the second wafer (paragraph 81 “the performance of steps to such as interconnect processing”)
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fong (US Pub 2018/0082989) in view of Burns (US 6,194,247) and Min (US Pub 2015/0048493) as applied to claim 1 above and further in view of Chen (US 2021/0091022 A1).
With respect to claim 2, Fong/Burns/Min teaches all limitations of the independent claim 1 upon which claim 2 depends.
Fong/Burns/Min is silent to:
Wherein the first warpage compensating layer and the second warpage compensating layer include different materials
Chen teaches in the abstract and Fig. 5:
Wherein the first warpage compensating layer (first dielectric layer 220 of warpage control portion 20A) and the second warpage compensating layer (metal pattern 224 and second dielectric layer 222 of warpage control portion 20A) include different materials (dielectric layer 220 and metal pattern 224)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen into the method of Fong/Burns/Min to make the warpage compensating layers out of different materials. The ordinary artisan would have been motivated to modify Fong/Burns/Min in the manner set forth above for the purpose of tuning the warpage characteristics of the IC portion to be bonded (paragraph 43 of Chen) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 3, Fong/Burns/Min teaches all limitations of the independent claim 1 upon which claim 3 depends.
Fong/Burns/Min is silent to:
Wherein the first warpage compensating layer and the second warpage compensating layer include silicon nitride
Chen teaches in para. 42:
Wherein the first warpage compensating layer (first dielectric layer 220 of warpage control portion 20A) and the second warpage compensating layer (second dielectric layer 222 of warpage control portion 20A) include silicon nitride (“The first dielectric layer 220 and the second dielectric layer 222 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen into the method of Fong/Burns/Min to make the warpage compensating layers with silicon nitride. The ordinary artisan would have been motivated to modify Fong/Burns/Min in the manner set forth above for the purpose of tuning the warpage characteristics of the IC portion to be bonded (paragraph 43 of Chen) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
With respect to claim 4, Fong/Burns/Min teaches all limitations of the independent claim 1 upon which claim 4 depends.
Fong/Burns/Min is silent to:
Wherein the first warpage compensating layer and the second warpage compensating layer include silicon oxide
Chen teaches in para. 42:
Wherein the first warpage compensating layer (first dielectric layer 220 of warpage control portion 20A) and the second warpage compensating layer (second dielectric layer 222 of warpage control portion 20A) include silicon oxide (“The first dielectric layer 220 and the second dielectric layer 222 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen into the method of Fong/Burns/Min to make the warpage compensating layers with silicon oxide. The ordinary artisan would have been motivated to modify Fong/Burns/Min in the manner set forth above for the purpose of tuning the warpage characteristics of the IC portion to be bonded (paragraph 43 of Chen) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 9, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fong (US Pub 2018/0082989) in view of Burns (US 6,194,247) and Min (US Pub 2015/0048493) as applied to independent claim 1 above and further in view of Cheng (US 2009/0212362 A1).
With respect to claim 9, Fong/Burns/Min teach all limitations of claim 1 upon which claim 9 depends. Fong/Burns/Min is silent to:
wherein the first warpage compensating layer and the second warpage compensating layer are configured to be deposited using plasma enhanced physical vapor deposition
Cheng teaches in para. 60 that plasma enhanced physical vapor deposition is a known technique for depositing dielectric materials such as silicon oxide and silicon nitride, materials used as warpage compensating materials in the instant application. Therefore, modifying the method of Fong/Burns/Min with Cheng teaches:
wherein the first warpage compensating layer and the second warpage compensating layer are configured to be deposited using plasma enhanced physical vapor deposition
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of forming warpage compensation materials of Fong/Burns/Min for the plasma enhanced physical vapor deposition method taught by Cheng because they are known equivalents and it would have yielded the predictable result of providing a dielectric layer. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 12, Fong/Burns/Min/Cheng further teaches:
the wafer stack is diced into multiple stacked integrated circuits (ICs) (para. 84 of Min “a sawing process may be performed to dice the resulting structure and form the plurality of the semiconductor packages 192.”)
With respect to claim 13, Fong/Burns/Min/Cheng further teaches:
at least one of the multiple stacked ICs (see Fig. 12 of Min, semiconductor chips 110, 120, 130 make up stacked IC after dicing) is mounted onto a substrate (circuit substrate 100) to form a chip package.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Fong (US Pub 2018/0082989) in view of Burns (US 6,194,247), Min (US Pub 2015/0048493) and Cheng (US 2009/0212362 A1) as applied to claim 9 above and further in view of Thiel (Proceedings of the International Wafer-Level Packaging Conference 2019).
With respect to claim 10, Fong/Burns/Min/Cheng teach all limitations of claim 9 upon which claim 10 depends. Fong/Burns/Min/Cheng fails to teach:
wherein the first wafer and the second wafer are configured to undergo a hybrid bonding process.
Theil teaches bonding semiconductor wafers together using a hybrid bonding process (see Fig. 2 for hybrid bond formation schematic, abstract “While hybrid bonding exists today in wafer-to-wafer (W2W) format in high volume manufacturing, the proliferation of this technology continues to accelerate”)
Modifying the method of Fong/Burns/Min/Cheng with the teaching of Thiel such that the wafers are hybrid bonded together teaches:
wherein the first wafer and the second wafer are configured to undergo a hybrid bonding process.
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the method of bonding wafers together of Fong/Burns/Min/Cheng for the hybrid bonding method taught by Theil because they are known equivalents and it would have yielded the predictable result of bonding semiconductor wafers together. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 11, Fong/Burns/Min/Cheng/Theil further teaches:
wherein the hybrid bonding process includes bonding dielectric layers (“dielectric” see Fig. 2 of Theil) surrounding bond pads (“metal” see Fig. 2 of Theil) to secure the second wafer to the first wafer, followed by an interfusion of conductive materials of the bond pads (dielectrics bonded in Fig. 2(b) followed by interfusion in Fig. 2(c)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fong (US Pub 2018/0082989) in view of Burns (US 6,194,247), Min (US Pub 2015/0048493) and Clemenceau (US Pub 2023/0230874 A1).
With respect to claim 20 Fong teaches:
A method for mitigating warpage on stacked wafers, the method comprising:
stacking an active side (1104) of the first wafer (1102 and 1104) on an active side (paragraph 80, layers 1 to n of “Wafer Scale Processing stack 1106”) of a second wafer (1106) to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer (paragraph 81, “Shown last in FIG. 11 is the performance of steps to such as interconnect processing”);
depositing a first dielectric warpage compensating layer (Fig. 17B, paragraphs 216-219, “stress compensating layers”) in direct contact with a backside of a first wafer (Fig. 11, paragraph 79, “special wafer 1102” attached to “IC layer n+1 1104” with 1102 of the simplified process flow acting as the “transfer device layer” of paragraph 219, “The stress compensating layers can be formed by direct layer transfer to the transfer device layer backside”);
removing the first and second warpage compensating layer (“stress compensating layers” attached to 1102) from the backside of the first and second wafers (paragraph 80 “After bonding, the wafer 1102 can be released”)
stacking an active side of a third wafer (paragraph 81, layer n+2) on the backside of the second wafer (layer n+1) to add to form a second wafer stack (1106) comprising the first (layer n), second (layer n+1) and third wafers (layer n+2), the third wafer having circuitry electrically connected to circuitry of the second wafer (paragraph 81 “the performance of steps to such as interconnect processing”)
Fong is silent to:
a first dielectric warpage compensating layer
depositing a second dielectric warpage compensating layer in direct contact with a backside of the second wafer;
removing the second warpage compensating layer from the backside of the and second wafer
such that the first warpage compensating layer and the second warpage compensating layer are on opposed ends of a first wafer stack;
dicing the wafer stack.
Burns teaches:
depositing a first warpage compensating layer (material 41) on a backside of a wafer (26)
depositing a second warpage compensating layer (material 44) a backside of the wafer (26).
By combining the teaching of Burns to deposit warpage compensating layers on both sides of a device with the teaching of Fong in which warpage compensating layers are deposited by depositing them in direct contact with a wafer,
Fong/Burns teaches:
depositing a second dielectric warpage compensating layer in direct contact with a backside of a second wafer
and removing the second warpage compensating layer from the backside of the second wafer (para. 216-219 of Fong teaches that stress compensating layers are attached to temporary bonding structures to facilitate a bonding process and can be removed after bonding)
such that the first warpage compensating layer and the second warpage compensating layer are on opposed ends of the wafer stack (Burns teaches including warpage structures on both sides of a wafer to prevent warpage when it cools from the formation temperature, Fong teaches bonding multiple wafers.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Burns into the method of Fong to deposit a stress compensating layer onto the second wafer as claimed in the device of Fong and to then remove the second warpage compensating layer from the backside of the second wafer. The ordinary artisan would have been motivated to modify Fong in the manner set forth above for the purpose of retaining a thermal balance throughout the integrated circuit package (column 8, lines 45-54 of Burns) and to minimize the size of the device by removing layers that are no longer necessary.
Min teaches:
dicing the wafer stack (paragraph 84, a sawing process may be performed to dice the resulting structure and form the plurality of the semiconductor packages.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Min into the method of Fong/Burns to dice the wafer stack after removing the stress compensating layer. The ordinary artisan would have been motivated to modify Fong in the manner set forth above for the purpose of forming a plurality of semiconductor packages (paragraph 84 of Min).
Clemenceau teaches in paragraphs 37-38:
depositing a dielectric warpage compensating layer (“bow compensating layer 32 is made of silicon oxide or of silicon nitride”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Clemenceau into the method of Fong/Burns/Min to make the stress compensating layer out of a dielectric such as silicon oxide or silicon nitride. The ordinary artisan would have been motivated to modify Fong in the manner set forth above for the purpose of compensating for future deformations of the substrate (paragraph 37 of Clemenceau) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Response to Arguments
Applicant’s arguments, see page 6-7, filed June 9, 2025, with respect to claim objections, drawing objections, and objection to the specification have been fully considered and are persuasive in view of amendments. The objections have been withdrawn or are moot.
Applicant's arguments filed June 9, 2025 regarding prior art rejections of claims 1 and 20 have been fully considered but they are not persuasive.
Applicant argues that the combination of Burns and Fong would not yield a structure having warpage-compensating layers on opposite ends of the wafer stack because Burns teaches a single wafer and that Fong allegedly does not teach an external compensating layer on the stack at all.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Although Burns teaches a single wafer, Fong is relied upon for the use of a wafer stack. Further, Fong does teach the use of a stress compensating layer on a temporary bonding structure in para. 219 “The stress compensating layers can be formed by direct layer transfer to the transfer device layer backside while the transfer device layer is attached to temporary bonding structure.” Fong, however, is silent to the use of a stress compensating layer on both sides of the stack as it is being formed.
Applicant further argues that “such a combination would require significant redesign, not merely a substitution or extension of known methods. That weighs against obviousness under KSR Int'l Co. v. Teleflex Inc., particularly where the art does not show a predictable path or express motivation. As such, Burns and Fong address different problems at different levels of integration, and their teachings are not readily combinable without impermissible hindsight.” Although Burns teaches that the warpage compensation is for a single wafer and that the warpage compensation remains in the final package, the motivation for including warpage compensation on both sides during the formation of the package is applicable to the method of Fong. Burns teaches in col. 4, lns. 3-19 that “unless warpage is controlled, the molded package will bend unacceptably upon cooling from its bonding temperature to cooler storage and operational temperatures” and “each material layer, upon cooling, seeks its new dimensions according to its CTE, but is restrained by the presence of the other material layers which make up the assembly. The forces produced by these restraining layers, if not minimized and balanced by proper design, materials selection, and construction, can produce undesirable warpage.” Burns solves this problem by depositing warpage control layers on both sides of an integrated circuit package in order to minimize differential thermal expansion forces on either side of an assembly. The Examiner takes the position that the teachings of Burns are applicable whether the assembly is a single integrated circuit die as taught by Burns or a stack of wafers such as the stack taught by Fong, as Fong teaches that stress compensation during bonding is desirable in para. 215 by teaching “Even with the use of a stiff temporary bond holder to form a stress-containing layer into a planar form suitable for bonding, un-compensated stresses in a complex bonded stack can lead to bond failures and IC device degradation from thermal stress during subsequent fabrication steps.” Therefore, it would be obvious to compensate for stress from both sides of the wafer stack as taught by Burns to minimize differential forces on either side of the assembly. Therefore, the argument is found not persuasive.
Conclusion
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897