Prosecution Insights
Last updated: August 15, 2026
Application No. 17/875,395

TRANSISTOR STRUCTURE

Final Rejection §103§112
Filed
Jul 27, 2022
Priority
Jul 29, 2021 — provisional 63/226,787
Examiner
SCHODDE, CHRISTOPHER A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Invention And Collaboration Laboratory Pte. Ltd.
OA Round
4 (Final)
52%
Grant Probability
Moderate
5-6
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 52% of resolved cases
52%
Career Allowance Rate
46 granted / 89 resolved
-16.3% vs TC avg
Strong +36% interview lift
Without
With
+35.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
44 currently pending
Career history
124
Total Applications
across all art units

Statute-Specific Performance

§103
54.4%
+14.4% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
28.3%
-11.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 89 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings In view of Applicant’s amendments, the prior drawing objection is withdrawn. Claim Rejections - 35 USC § 112 The prior rejection for lack of written description is withdrawn in view of Applicant’s amendments. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-3, 5-6, and 9-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Amended claim 1 now recites “wherein the sheet channel layer does not cover a top surface of the fin structure”. This is a negative limitation which does not have support in the original disclosure. Nowhere is the sheet channel layer described as “does not cover” a top surface of the fin structure; and when the drawings are rotated 90° the sheet channel layer does appear to cover a top surface of the fin structure (see e.g., Fig. 12 or 21). Any negative limitation or exclusionary proviso must have basis in the original disclosure; and any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement. Claims 2-3, 5-6, and 9-12 inherit this rejection for an unsupported negative limitation. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. In view of Applicant’s amendments, some of the 112(b) rejections are withdrawn. Claims 1-3, 5-6, 9-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (Claim 1) As the sheet channel layer was not originally shown or described as “does not cover a top surface of the fin structure”, the relationship between parts is unclear. During examination, “does not cover a top surface of the fin structure” was understood to require that an orthographic projection of a top surface of the fin structure is outside of an orthographic projection of the sheet channel layer on the substrate. Claims 2-3, 5-6, and 9-12 inherit these rejections for indefiniteness. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 3, and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2013/0248948), Oh et al. (US 2013/0249003), Brask et al. (US 2005/0266692), and Guo et al. (US 2015/0318211), all of record. (Re Claim 1) Ma teaches a transistor structure comprising: a substrate (2+4; Fig. 4A) with a body region (4; Fig. 4A), and the body region comprising a fin structure (4; Fig. 4A), wherein the fin structure has a top surface (topmost surface; Fig. 4A); a gate conductive region (10; Fig. 6A) of a gate region (4; Fig. 4A) above the body region (Fig. 6A and 13); and a gate dielectric layer (8; Fig. 6A and 13) of the gate region (Fig. 4A) between the gate conductive region and the body region, where a top surface (topmost as seen in Fig. 6A) of the fin structure is totally covered by the gate region (Fig. 6A). Ma does not explicitly teach a sheet channel layer disposed between the body region and the gate dielectric layer and not covering the top surface of the fin structure corresponding to the gate region, and the gate dielectric layer contacts the top surface of the fin structure; wherein a doping concentration of the body region is higher than a doping concentration of the sheet channel layer. Oh teaches a transistor structure comprising: a sheet channel layer (134; Fig. 35) disposed between a body region (F) and a gate dielectric (145), wherein the sheet channel layer is independent from a substrate (100+F; Fig. 35). Oh additionally teaches an embodiment where a sheet channel layer (131; Fig. 2 and 4) is doped such that a doping concentration of a body region (F; Fig. 4) is higher than a doping concentration of the sheet channel layer (¶49). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form through selective growth a sheet channel layer 134 of Oh around the body region of Ma such that a doping concentration of the body region 4 of Ma is higher than a doping concentration of the sheet channel layer 134 of Oh, as having a sheet channel layer surrounding the body region with such a relative doping concentration increases carrier mobility (Oh: ¶50). Guo teaches epitaxially growing a sheet channel layer (6a+6b; Fig. 4) such that the sheet channel layer does not cover a top surface (topmost; Fig. 4) of a fin structure (5; Fig. 4) as the epitaxial growth process is selective, and does not cause growth on the dielectric materials, and so the top surface of the fin structure is not covered by the sheet channel layer (3; Fig. 4; “the epitaxially deposited undoped epitaxial semiconductor material 6a, 6b may not be deposited on a dielectric material. For example, the undoped epitaxial semiconductor material 6a, 6b is not formed on the sacrificial gate cap 12, the dielectric fin cap 3 and the gate sidewall spacer 13.”; ¶32; see also ¶30). The dielectric fin cap 3 layer serves as a hard mask during formation of the fin structure (¶¶21-23; “dielectric fin cap 3 may be removed by a selective etch”; ¶22). As PHOSITA would find it obvious to form the fin structures of modified Ma using the hard mask process of Guo (Guo: ¶¶21-23), as etching using a hard mask allows for forming smaller device features (Brask: ¶4). This results in the fin structure of modified Ma being the combination of Ma’s 4 (Ma: Fig. 4A) and the dielectric fin cap 3 of Guo (Guo: Fig. 4). Furthermore, a PHOSITA would find it obvious to form the sheet channel layer of modified Ma (Oh: 134; Fig. 35) such that it is not covering a top surface of the fin structure as a consequence of epitaxially forming the sheet channel layer using a hard mask process according to Guo (Guo: selective formation of the sheet channel layer 6a+6b on the sides of the fin structure 5; Fig. 4, ¶32). As the sheet channel layer of modified Ma is then only on the sides of the fin structure, modified Ma teaches a transistor structure wherein the gate dielectric material contacts a top surface (now the top of Guo’s cap 3 on the structure 4 of Ma) of the fin structure. (Re Claim 3) Modified Ma teaches the transistor structure in claim 1, wherein the sheet channel layer comprises a first sheet channel layer (left portion of 134 of Oh, contacting the left sidewall of Ma’s fin structure 4, seen in a cross-section perpendicular to the channel, such as in Fig. 35 of Oh) and a second sheet channel layer (right portion of 134 of Oh, contacting the right sidewall of Ma’s fin structure 4, seen in a cross-section perpendicular to the channel, such as in Fig. 35 of Oh), the first sheet channel layer contacts to a first sidewall of the fin structure (left sidewall of the fin structure; Oh: Fig. 35), and the second sheet channel layer contacts to a second sidewall of the fin structure (right sidewall of the fin structure; Oh: Fig. 35). (Re Claim 9) Modified Ma teaches the transistor structure in claim 1, further comprising a first conductive region (26+28; Fig. 13) abutting against the sheet channel layer and the body region, wherein the first conductive region is independent from the substrate. (Re Claim 10) Modified Ma teaches the transistor structure in claim 9, wherein the first conductive region comprises a lightly doped region (¶32) and a highly doped region (¶34) vertically stacked on the lightly doped region. (Re Claim 11) Modified Ma teaches the transistor structure in claim 10, wherein the lightly doped region and the highly doped region are formed by selective growth (¶¶32, 34). Claim 11 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed lightly and highly doped regions need not be formed by the process of selective growth. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983). (Re Claim 12) Modified Ma teaches the transistor structure in claim 1, wherein the sheet channel layer is formed by selective growth (Oh: ¶76). Claim 12 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed sheet channel layer need not be formed by the process of selective growth. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2013/0248948), Oh et al. (US 2013/0249003), Brask et al. (US 2005/0266692), and Guo et al. (US 2015/0318211) all of record, as applied to claim 1 above, and further in view of JangJian et al. (US 2016/0322473) and Liu (US 2021/0135006), both of record. (Re Claim 2) Modified Ma teaches the transistor structure in claim 1, but does not explicitly teach the transistor structure wherein the substrate further comprises a well region underneath the body region, and the doping concentration of the sheet channel layer is higher than a doping concentration of the well region. JangJian teaches forming a well region (within 40; Fig. 4A) underneath a body region (42; Fig. 4A) within a substrate (Fig. 4A, ¶¶17-19). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a well region underneath the body region within the substrate of modified Ma in order to tune device performance (Liu: ¶33). As JangJian teaches a doping concentration of the well region that is lower than the doping concentration of the sheet channel region of modified Ma (JangJian: ¶18; Oh: “the preliminary semiconductor layer 130 may be doped with additional dopants in a dopant-concentration equal to or less than about a tenth of that of the inner fin portion F”; ¶66; see also ¶¶50, 63), modified Ma teaches the claimed limitations. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2013/0248948), Oh et al. (US 2013/0249003), Brask et al. (US 2005/0266692), and Guo et al. (US 2015/0318211) all of record, as applied to claim 3 above, and further in view of Lee et al. (US 2008/0073730), of record. (Re Claim 5) Modified Ma teaches the transistor structure in claim 3, but does not explicitly teach the transistor structure further comprising a spacer layer attaching to the first sheet channel layer and the second sheet channel layer. Lee teaches transistor structure further comprising a spacer layer (109+111; Fig. 3B). A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form a spacer layer as taught by Lee conformal to the sheet channel layer of modified Ma, as taught by Lee, in order to reduce stress and prevent oxidation of the sheet channel layer and body region (Lee: ¶39). This results in modified Ma teaching a spacer layer attaching to the first and second sheet channel layer due to deposition after formation of the sheet channel layer. (Re Claim 6) Modified Ma teaches the transistor structure in claim 5, wherein the spacer layer comprises a nitride layer (Lee: 111; ¶39). Response to Arguments Applicant's arguments filed 6/4/2026 have been fully considered but they are not persuasive. For support, Applicant cites ¶96, but this only says “but the top surface of the Fin does not have the SCL, so this is the new Type B finFET”. “the top surface…does not have the SCL” (¶96) and “the sheet channel layer does not cover a top surface of the fin structure” (amended claim 1) are of different scope, and so Applicant does not appear to have support for “does not cover a top surface”. From the left or the right direction, the SCL appears to cover the top surface of the fin structure while from the top the fin structure is totally covered by the gate region. See the 112(a) rejection above. Applicant also argues that Guo does not teach the claimed invention (remarks, p. 11). However, the rejection was made with respect to Ma in view of Guo. It is Ma that supplies the gate dielectric layer (Ma: 8; Fig. 6A and 13). In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The remainder of Applicant’s arguments are moot. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
Read full office action

Prosecution Timeline

Show 1 earlier event
Aug 07, 2025
Non-Final Rejection mailed — §103, §112
Nov 05, 2025
Response Filed
Dec 10, 2025
Final Rejection mailed — §103, §112
Mar 09, 2026
Request for Continued Examination
Mar 12, 2026
Response after Non-Final Action
Mar 20, 2026
Non-Final Rejection mailed — §103, §112
Jun 04, 2026
Response Filed
Jun 22, 2026
Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

5-6
Expected OA Rounds
52%
Grant Probability
87%
With Interview (+35.6%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 89 resolved cases by this examiner. Grant probability derived from career allowance rate.

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