DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 02/10/2026, with respect to the rejection(s) of claim(s) under 35 USC 102 and 103 have been fully considered and are persuasive, the amendments made overcome the rejections as written. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection of claim 16 and dependent claims is made in view of the embodiment of fig. 11A-11B of US 20200365687 A1 Xi et al.
Applicant's arguments filed 02/10/2026 have been fully considered but they are not persuasive. The applicant argues that Xie does not teach “Therefore, Xie fails to teach "a gate stack over the first spacer layer and the substrate, wherein the gate stack comprises a work function metal layer a second nanostructure between the first spacer layer and the substrate, wherein the second nanostructure is made of a semiconductor material, and the work function metal layer overlaps the second nanostructure" as recited in amended claim 16.” After additional consideration the examiner agrees that the embodiment of Xie fig. 7 relied upon in prior office action does not teach the newly amended limitation, however Fig. 11A sufficiently teaches both work function metal layer [The gates 1102 can include a high-k dielectric material(s) (not shown) and a work function metal stack (not shown) Paragraph 0072] and semiconductive material [“SiC” paragraph 0070] under broadest reasonable interpretation and/or in view of the embodiments of fig. 7 and fig. 11A it would be obvious to modified Xie in view of the teachings of Xie such that the limitation is met under MPEP 2144.07 as shown below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 17, 19, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200365687 A1 Xie et al here after “Xie”.
Claim 16 Xie teaches A semiconductor device structure, comprising:
a substrate (comprising 204 fig. 11A-B);
a first spacer layer (comprising 504 and 702 fig. 11A-B, met under broadest reasonable interpretation wherein the first spacer comprises a plurality of spacer layers [an isolation layer and a buffer layer] and a spacer layer spaces and/or separates other layers) over the substrate;
a gate stack (comprising 1102 fig. 11A-B) over the first spacer layer and the substrate, wherein the gate stack comprises a work function metal layer [explicitly disclosed but not illustrated Paragraph 0072 in “The gates 1102 can include a high-k dielectric material(s) (not shown) and a work function metal stack (not shown)”];
a first nanostructure (214 fig. 11A and 11B) passing through the gate stack [illustrated fig. 11B]; and
a source/drain structure (comprising 702 and 704 fig. 11A) over the first spacer layer and connected to the first nanostructure [illustrated fig. 11A].
a second nanostructure (1002 fig. 11A) between the first spacer layer and the substrate [illustrated fig. 7], wherein the second nanostructure is made of a semiconductor material [“SiC” disclosed with sufficient specificity in paragraph 0070] and the work function metal layer overlaps the second nanostructure [sufficiently illustrated fig. 11A-11B in view paragraph 0072].
Claim 17 Xie teaches as shown above the semiconductor device structure as claimed in claim 16, wherein the first spacer layer separates the gate stack, the first nanostructure, and the source/drain structure from the substrate [illustrated within the cross section of fig. 11A, under broadest reasonable interpretation the source/drain structure is diagonally separated from the substrate by the first spacer layer, see annotation below].
PNG
media_image1.png
586
796
media_image1.png
Greyscale
Annotated fig. 11A-B Xie: highlighting the separation between the substrate and the source/drain structure
Claim 19 Xie teaches as shown above the semiconductor device structure as claimed in claim 16, further comprising:
a second spacer layer (506 fig. 11A) between the second nanostructure and the substrate.
Claim 22 Xie teaches as shown above the method for forming the semiconductor device structure as claimed in claim 19, wherein the second spacer layer is made of an insulating material [“nitride” and/or “SiN” sufficiently disclosed paragraph 0079 in “The bottom isolation structure can include a tri-layer stack in a first region of the substrate and a bi-layer stack in a second region of the substrate, in a similar manner as the bottom isolation structure 202 discussed previously herein with respect to FIG. 11A. In some embodiments of the invention, the tri-layer stack of the bottom isolation structure includes a nitride-oxide-nitride stack (e.g., SiN/SiO.sub.2/SiN)”].
Allowable Subject Matter
Claims 1-9, 11, 14, 21, 24, 25, and 26 allowed.
Claim 27 comprises allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 and dependent claims recite the limitation “after forming the first spacer layer in the first gap, partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack”.
Claim 11 and dependent claims recite the limitation “wherein after the spacer layer is formed in the first gap, the second nanostructure is connected between the spacer layer and the third nanostructure”.
Claim 27 recites the limitation “the first spacer layer is a single-layer structure, the entire first spacer layer is made of an insulating material, and a portion of the first spacer layer is between the source/drain structure and the second nanostructure”
Prior art of record although it teaches partially removing the nanostructure stack and the nanostructure is connected between the spacer layer and the third nanostructure, it does not teach doing so “after the formation of the first spacer layer in the first” nor that “the first spacer layer is a single-layer structure” in conjunction with “a portion of the first spacer layer is between the source/drain structure and the second nanostructure”. During the course of search the examiner has not found prior art that teaches this step in the context of the claims and/or claim language nor a reason to modify the prior art of record such that it would include the claimed limitation.
Claim 27 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights