Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/28/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 21, 25, 27-32 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over JangJian et. Al. (US 20130234202 A1 hereinafter Jang) and further in view of Hsu et. Al. (US 20150145096 A1 hereinafter Hsu) and still further in view of Cole et. Al. (US 20050184291 A1 hereinafter Cole).
Regarding claim 1, Jang teaches in Figs. 1-6 with associated text a method for forming a device comprising at least one pixel cell 101, comprising: providing a substrate 10 comprising a first semiconductor material (silicon [0009]); forming a pixel region (any sub-region of entire region between adjacent portions 14) inside the substrate (Fig. 1); forming a transfer gate (30 and 32) over the substrate (Fig. 6, [0016]), forming a trench 16 extending into the substrate and within a proximity of the pixel region (Fig. 2, [0010]); and epitaxially growing a heterogeneous layer 18 on a bottom surface of the trench (Fig. 3, [0011]), wherein the heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material (SiGe [0011]).
Jang does not specify the heterogeneous layer fills an entirety of the trench in a cross-sectional view..
Hsu teaches in Fig. 2 with associated text a trench structure (126 and 108) similar to that of Jiang and in Fig. 9 with associated text a trench structure (trench filled with 308), wherein the trench structure is not in contact with a pixel region 106 and wherein a heterogeneous layer 308 fills an entirety of the trench in a cross-sectional view (Fig. 9, paragraph [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a trench structure similar to that taught by Hsu for the trench structure of Jang because according to Hsu the epitaxial isolation features 308 may form a P-N junction with the radiation-sensing region 106A to prevent lateral current leakage and therefore would be suitable to prevent current leakage in the device of Jang.
Jang does not specify the steps of forming a trench extending into the substrate and within a proximity of the pixel region; and epitaxially growing a heterogeneous layer on a bottom surface of the trench are preformed after forming the transfer gate.
Cole teaches a method similar to that of Jang in view of Hsu wherein an isolation trench 340 extending into the substrate and within a proximity of a pixel region 421 is formed and before or after forming the transfer gate 460 so that by choosing to form the trench of Jang in view of Hsu after forming the transfer gate as taught by Cole the method would comprise after forming the transfer gate forming a trench extending into the substrate and within a proximity of the pixel region; and after forming the transfer gate epitaxially growing a heterogeneous layer on a bottom surface of the trench.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the steps of forming a trench extending into the substrate and within a proximity of the pixel region; and epitaxially growing a heterogeneous layer on a bottom surface of the trench of Jang in view of Hsu after forming the transfer gate as taught by Cole because according to Cole such an order of steps is a suitable alternative order. One of ordinary skill in the art at the time of the invention would have been motivated to look to analogous art teaching alternative suitable or useful methods of performing the disclosed steps, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 4, Jang teaches epitaxially growing the heterogeneous layer comprises: epitaxially growing the second semiconductor material with a dopant in the trench [0011].
Regarding claim 21, Jang teaches in Figs. 1-6 with associated text a method, comprising: forming a photodiode region (region between adjacent portions 14) in a substrate 10; forming a transfer gate 30 in vicinity of a first side of the photodiode region; forming a heterogeneous layer 18 extending within the substrate (Fig. 3, [0011]), the heterogeneous layer being in vicinity of a second side of the photodiode region (Fig. 3), wherein forming the heterogeneous layer comprises etching a trench (Fig. 2, [0010]) in the substrate, and epitaxially growing a semiconductor material 18 in the trench (Fig. 3, [0011]); and forming an isolation region 14 around the heterogeneous layer (Fig. 3).
Jang does not specify an entirety of the trench is filled by the semiconductor material.
Hsu teaches in Fig. 2 with associated text a trench structure (126 and 108) similar to that of Jiang Jian and in Fig. 9 with associated text a trench structure (trench in which 308 is formed), wherein an entirety of the trench is filled by a semiconductor material 308 (Fig. 9, paragraph [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a trench structure similar to that taught by Hsu for the trench structure of Jang because according to Hsu the epitaxial isolation features 308 may form a P-N junction with the radiation-sensing region 106A to prevent lateral current leakage and therefore would be suitable to prevent current leakage in the device of Jiang.
Jang does not specify the steps of forming a heterogeneous layer extending within the substrate are preformed after forming the transfer gate.
Cole teaches a method similar to that of Jang in view of Hsu wherein an isolation trench 340 extending into the substrate and within a proximity of a pixel region 421 is formed and before or after forming the transfer gate 460 so that by choosing to form the trench of Jang in view of Hsu after forming the transfer gate as taught by Cole the method would comprise after forming the transfer gate forming a heterogeneous layer extending within the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the steps of forming a heterogeneous layer extending within the substrate of Jang in view of Hsu after forming the transfer gate as taught by Cole because according to Cole such an order of steps is a suitable alternative order. One of ordinary skill in the art at the time of the invention would have been motivated to look to analogous art teaching alternative suitable or useful methods of performing the disclosed steps, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 25, Jang teaches the heterogeneous layer is formed after forming the photodiode region (region between adjacent portions 14 which is for forming a photodiode the claim wouldn’t necessarily require the heterogeneous layer is formed after forming a photodiode) in the substrate (Figs. 1-3).
Regarding claim 27, Jang teaches the semiconductor material epitaxially grown in the trench has a lattice constant different from a lattice constant of the substrate ([0011]).
Regarding claim 28, Jang teaches the heterogeneous layer is spaced apart from the photodiode region by the isolation region (Fig. 6).
Regarding claim 29, Jang teaches in Figs. 1-6 with associated text a method, comprising: forming a pixel region (region between adjacent portions 14) in a substrate; forming a transfer gate 30 over the substrate [0016]; forming a gate spacer 36 alongside the transfer gate, the gate spacer overlapping with a first side of the pixel region (Fig. 6 , [0016]); and forming a heterogeneous structure 18 embedded in the substrate (Fig. 3, [0011]), the heterogeneous structure being adjacent to a second side of the pixel region (Fig. 6), the heterogeneous structure having a lattice constant different from a lattice constant of the substrate ([0011]).
Jang does not specify the heterogeneous structure is separated from the pixel region.
Hsu teaches in Fig. 2 with associated text a trench structure 308, wherein the trench structure is separated from a pixel region 106 (Fig. 9, paragraph [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the trench structure of Jang to be separated from a pixel region as taught by Hsu for the trench structure of Jang because according to Hsu the epitaxial isolation features 308 may form a P-N junction with the radiation-sensing region 106A to prevent lateral current leakage and therefore the arrangement would be suitable to prevent current leakage in the device of Jiang.
Jang does not specify the steps of forming a heterogeneous structure embedded in the substrate are preformed after forming the gate spacer alongside the transfer gate.
Cole teaches a method similar to that of Jang in view of Hsu wherein an isolation trench 340 extending into the substrate and within a proximity of a pixel region 421 is formed and before or after forming the after forming a transfer gate 460 so that by choosing to form the trench of Jang in view of Hsu after forming the transfer gate as taught by Cole the method would comprise after forming the transfer including the gate spacer alongside the transfer gate forming a heterogeneous layer extending within the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the steps of forming a heterogeneous layer extending within the substrate of Jang in view of Hsu after forming the gate spacer alongside the transfer gate as taught by Cole because according to Cole such an order of steps is a suitable alternative order. One of ordinary skill in the art at the time of the invention would have been motivated to look to analogous art teaching alternative suitable or useful methods of performing the disclosed steps, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 30, Jang teaches the heterogeneous structure has a width decreasing from a top surface of the heterogeneous structure to a bottom surface of the heterogeneous structure (Fig. 6).
Regarding claim 31, Jang teaches the heterogeneous structure extends a first depth within the substrate, the pixel region (here the pixel region is interpreted to be 24) extends a second depth within the substrate (Fig. 6), and the second depth is less than the first depth (Fig. 6).
Regarding claim 32, Jang teaches a maximal width of the heterogeneous structure is less than a width of the pixel region (Fig. 5).
Regarding claim 36, Jang teaches the method of claim 1.
Jang does not specify a top surface of the heterogeneous layer is separated from a photodiode in the pixel region.
Hsu teaches in Fig. 2 with associated text a trench structure 308, wherein a top surface of the heterogeneous layer is separated from a photodiode in the pixel region 106 (Fig. 9, paragraph [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the trench structure of Jang to be separated from a pixel region as taught by Hsu for the trench structure of Jang because according to Hsu the epitaxial isolation features 308 may form a P-N junction with the radiation-sensing region 106A to prevent lateral current leakage and therefore the arrangement would be suitable to prevent current leakage in the device of Jang.
Regarding claim 37, Jang teaches the heterogeneous layer is spaced apart from the pixel region without forming a P-N junction with the pixel region (the heterogeneous layer in an embodiment is p-type [0012] and here the pixel region is interpreted to be 24 which is also p-type [0015] so that no p-n junction is formed between them) .
Claims 2, 5, 22-24 and 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Hsu and Cole as applied to claims 1 and further in view of Muramatsu et. Al. (US 20180286899 A1 hereinafter Muramatsu).
Regarding claim 2, Jang in view of Hsu and Cole teaches the method of claim 1.
Jang does not specify forming the trench comprises: depositing a hard mask on the substrate; depositing a patterned photoresist on the hard mask; and etching the substrate to form the trench based on the patterned photoresist and the hard mask However Jang does teach a mask can be used during the photolithography process and used during a subsequent epitaxial growth to prevent nucleation outside of the trench 16 [0010]
Muramatsu discloses in Figs. 3-6 with associated text forming a trench 9 comprises: depositing a hard mask (5 and 6) on a substrate 3 (Fig. 3, [0024]); depositing a patterned photoresist 50 on the hard mask (Fig. 4, [0024]; and etching the substrate to form the trench based on the patterned photoresist and the hard mask [0024].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the trench of Jang in view of Hsu and Cole with the method of Muramatsu because according to Muramatsu a resist layer 50 is formed on the insulating layer 6, and a slit-shaped opening 50a corresponding to the opening of the trench 9 is formed in the resist layer 50 by photo-etching. Subsequently, slit-shaped openings 6a and 5a corresponding to the opening 50a are formed in the insulating layers 6 and 5 by plasma etching, subsequently (after the first step), the trenches 9 are formed in the semiconductor substrate 3 by reactive ion etching (RIE) (second step), thus, the trench 9 is formed in the semiconductor substrate 3 to separate the photoelectric conversion parts 2 from each other [0024] so that such a method is suitable for forming trenches to separate the photoelectric conversion parts from each other as required by Jang in view of Hsu and Cole.
Regarding claim 5, Jang in view of Hsu and Cole teaches the method of claim 4.
Jang does not specify epitaxially growing the heterogeneous layer further comprises: annealing the device so as to drive the dopant into the substrate to form an isolation region around the heterogeneous layer, wherein the dopant has a conductivity type being n-type or p-type.
Muramatsu discloses in Figs. 3-6 with associated text epitaxially growing a heterogeneous layer 11 further comprises: annealing the device so as to drive the dopant into the substrate to form an isolation region 12 around the heterogeneous layer (Fig. 6, [0022] and [0025]), wherein the dopant has a conductivity type being n-type or p-type (boron [0022] is a p-type dopant).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the isolation layer of Jang in view of Hsu and Cole with the method of Muramatsu because according to Muramatsu generation of a dark current due to a defect occurring in the semiconductor substrate 3 along the inner surface 9a of the trench 9 is suppressed [0022] so that such a would be useful for suppressing a dark current due to a defect occurring in the semiconductor substrate of Jang in view of Hsu.
Regarding claim 22, Jang in view of Hsu and Cole teaches the method of claim 21.
Jang does not specify forming the isolation region comprises diffusing a dopant from the heterogeneous layer into the substrate.
Muramatsu discloses in Figs. 3-6 with associated text forming an isolation region 12 comprises diffusing a dopant from a heterogeneous layer 11 into a substrate (Fig. 6, [0022] and [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the isolation layer of Jang in view of Hsu with the method of Muramatsu because according to Muramatsu generation of a dark current due to a defect occurring in the semiconductor substrate 3 along the inner surface 9a of the trench 9 is suppressed [0022] so that such a would be useful for suppressing a dark current due to a defect occurring in the semiconductor substrate of Jang in view of Hsu.
Regarding claim 23, Jang in view of Hsu, Cole and Muramatsu teaches the dopant is diffused by an annealing process (Muramatsu Fig. 6, thermal diffusion [0025]).
Regarding claim 24, Jang in view of Hsu Cole and Muramatsu teaches the dopant has an n-type conductivity or a p-type conductivity (boron [0022] is a p-type dopant).
Regarding claim 33, Jang in view of Hsu and Cole teaches the method of claim 29.
Jang does not specify diffusing a dopant from the heterogeneous structure into the substrate.
Muramatsu discloses in Figs. 3-6 with associated text diffusing a dopant from a heterogeneous structure 11 into the substrate (Fig. 6, [0022] and [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the isolation layer of Jang in view of Hsu and Cole with the method of Muramatsu because according to Muramatsu generation of a dark current due to a defect occurring in the semiconductor substrate 3 along the inner surface 9a of the trench 9 is suppressed [0022] so that such a would be useful for suppressing a dark current due to a defect occurring in the semiconductor substrate of Jang in view of Hsu and Cole.
Regarding claim 34, Jang in view of Hsu Cole and Muramatsu teaches the dopant is diffused from the heterogeneous structure in the substrate by an annealing process (Muramatsu Fig. 6, thermal diffusion [0025]).
Regarding claim 35, Jang in view of Hsu Cole and Muramatsu teaches the dopant has an n-type conductivity or a p-type conductivity (boron [0022] is a p-type dopant).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Hsu and Cole as applied to claim 1 and further in view of Kaneda et. Al. (US 20160284757 A1 hereinafter Kaneda).
Regarding claim 3, Jang in view of Hsu and Cole teaches the method of claim 1, further comprising doping the substrate to form an isolation region 14 inside the substrate and within a proximity of the pixel region (Jang Fig. 1, [0009]), wherein: the trench is formed in the isolation region (Fig. 2, [0010]).
Jang does not specify the heterogeneous layer provides a gettering of at least one of metal ions, dot- defects, or impurities in the substrate; and the isolation region is configured for isolating the heterogeneous layer from charge carriers generated in the substrate.
Kaneda discloses in Fig. 2 with associated text a heterogeneous layer 108 (108 comprises germanium (paragraph [0042]) similar to that of Jang in view of Hsu and Cole wherein the heterogeneous layer provides a gettering of at least one of metal ions, dot-defects, or impurities in the substrate (paragraph [0027]); and an isolation region 109 similar to that of Jang in view of Hsu is configured for isolating a heterogeneous layer 108 from charge carriers generated in a substrate 120 (paragraph [0027]) so that by following the teaching of Kaneda the heterogeneous layer of Jang in view of Hsu would provide a gettering of at least one of metal ions, dot-defects, or impurities in the substrate and the isolation region of Jang in view of Hsu and Cole would be configured for isolating the heterogeneous layer from charge carriers generated in the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to follow the teachings of Kaneda in the device of Jang in view of Hsu and Cole because according to Kaneda such a structure makes it possible to reduce noise such as the white spot (Kaneda paragraph [0027]) and to suppress the inflow of the electrons from the element isolation region 106 into the charge accumulation region 102 which forms the photoelectric conversion element and to suppress occurrence of noise (Kaneda paragraph [0027]), furthermore Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
The following italicized limitations of claim 3 lines 5-8 are understood to be functional (i.e. the heterogeneous layer provides a gettering of at least one of metal ions, dot- defects, or impurities in the substrate; and the isolation region is configured for isolating the heterogeneous layer from charge carriers generated in the substrate): The limitation describes purpose, function, operation, or intent -of-use the heterogeneous layer and isolation layer. However, the claim does not disclose a sufficient structure which supports the function. Since Jang in view of Hsu shows an identical structure as claimed, namely a heterogeneous layer and isolation layer, the Examiner submits that the heterogeneous layer and isolation layer is capable of producing the claimed results.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 21-25 and 28-37 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/AARON J GRAY/Examiner, Art Unit 2897