DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation “the transistors” throughout the claim. It is unclear if the limitations refer to “a plurality of transistors” or different feature. Correction is required.
Claim 23 recites the limitation “the opening”. It is unclear if the limitations refer to “a plurality of openings” or different feature. Correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-24 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Chiang et al. (US PUB. 2020/0173958).
Regarding claim 21, CHIANG teaches a device, comprising:
a substrate 110 having a first side and a second side opposite the first side (Fig. 1-Fig. 2A);
a plurality of dielectric components 136 that extend from the first side of the substrate 110 to the second side of the substrate (Fig. 1 & Fig. 2A);
a plurality of transistors (102 & 104) disposed over the first side of the substrate 110, wherein adjacent transistors of the plurality of transistors are separated by different dielectric components 136 of the plurality of dielectric components 136 (Fig. 1, Fig. 2A & Fig. 14A), and wherein the plurality of transistors include at least one voltage reference transistor 104 (VRFET) and at least one sensing transistor 102 (ISFET); and
a sensing film 124 disposed over the second side of the substrate 110, wherein a surface of the sensing film directly contacts surfaces of the plurality of dielectric components 136 (see Fig. 2A & Fig. 14A); and
a structure disposed over the sensing film 124, wherein the structure includes a plurality of openings (126 & 128) that are each vertically aligned with a respective transistor of the plurality of transistors (Fig. 1-Fig. 2A & Fig. 14A);
wherein:
the plurality of transistors includes a first voltage reference transistor and a second voltage reference transistor (see Fig. 14A below);
the first voltage reference transistor and the second voltage reference transistor have different lateral dimensions in across-sectional side view (note the different lateral dimensions between the first and second voltage transistors below); and
the sensing transistor is disposed between the first voltage reference transistor and the second voltage reference transistor in the cross-sectional side view (note the annotations in Fig. 14 below).
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Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 22, Chiang teaches the device of claim 21, wherein: the transistors (see transistors in Fig. 14A above) include a plurality of gates, respectively; and at least some of the gates of the transistors have different material compositions or different dimensions than other gates of the transistors (see Fig. 1-Fig. 2A & Fig. 14A and associated text).
Regarding claim 23, Chiang teaches the device of claim 21, wherein: the openings are fillable by a fluid 132 that contains one or more miniature components 130; and the sensing film 124 is attachable to the one or more miniature components (see Fig. 1-2F and associated texts (e.g. Para [0030, 0040, 0057 & 0062-0064])).
Regarding claim 24, Chiang teaches the device of claim 23, wherein the one or more miniature components include at least one of: an ion, a nucleic acid, a polarized molecule, an antigen, an antibody, an enzyme, a cell, a protein, a virus, or a bacterium (Fig. 1-2F and associated text (e.g. Para [0030])).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-13 & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. in view of ZHAO et al. (US PUB. 2022/0059576).
Regarding claim 1, Chiang teaches a device, comprising:
a substrate 110 having a first side and a second side opposite the first side (Fig. 1-Fig. 2A & Fig. 14A);
a plurality of isolation structures 136 that extend through the substrate 110 from the first side to the second side (Fig. 1- Fig. 2A & Fig. 14A);
a first transistor (1302vrf) having a first gate, a second transistor (1302isf) having a second gate, and a third transistor (1302isf, see annotations on Fig. 14A below) having a third gate, wherein the first gate, the second gate, and the third gate are each disposed over the first side of the substrate 110, wherein the second gate (gate of 1302isf) is disposed between the first gate and the third gate (see Fig. 14A below), wherein a first isolation structure of the plurality of isolation structures 136 is disposed between the first transistor 1302vrf and the second transistor 1302isf (e.g. Fig. 2A), and wherein a second isolation structure of the plurality of isolation structures 136 is disposed between the second transistor and the third transistor 1302vrf (see 1-2A and note continuation of the plurality of isolation structures 136 in Fig. 14A);
a structure disposed over the second side of the substrate 110, wherein the structure includes a first opening aligned with the first transistor (1302vrf), a second opening aligned with the second transistor (1302isf), and a third opening aligned with the third transistor (1302vrf) (see Fig. 14A below and note the annotations); and
a sensing film 124 disposed over the second side of the substrate 110, wherein the sensing film is configured to attach to one or more predefined miniature targets (Fig. 1-2F & Fig. 14A and associated text (e.g. Para [0030])), and wherein a surface of the sensing film 124 extends to surfaces of the first isolation structure 136 and the second isolation structure (see Fig. 2A, wherein a surface of the sensing film124 extends to surfaces of the first one of the isolation structures 136 and the second one of the isolation structures);
wherein:
the first transistor and the third transistor are voltage reference transistors (see Fig. 14 below: the first transistor and third transistor are capable of performing as voltage reference transistors);
the second transistor is a sensing transistor (Fig. 14A below: second transistor is capable of functioning as a sensing transistor); and
the first gate and the third gate have different lateral dimensions (note the difference in lateral dimensions of the first and third gates in Fig. 14A below).
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However, Chiang is silent on wherein the first gate and the third gate have different gate dielectric layers with different material compositions. ZHAO teaches a semiconductor device, wherein a first gate 123 and a third gate 113 have different gate dielectric layers with different material compositions (Fig. 1 and respective text). This has the advantage of reduced leakage current, lower operating voltages and improved thermal stability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chiang with gate dielectric layers, as taught by ZHAO, so as to obtain an improved semiconductor device. Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 2, the combination of Chiang and Zhao teaches the device of claim 1, wherein: the first opening, the second opening, and the third opening are configured to collect a fluid 132 that contains the one or more predefined miniature targets (see Fig. 14A above); and the device is configured to detect a presence of the one or more predefined miniature targets at least in part via physical contact made between the sensing film and the one or more predefined miniature targets (Fig. 1-2F & Fig. 14A and associated text (e.g. Para [0030])).
Regarding claim 3, the combination of Chiang and Zhao teaches the device of claim 2, wherein the device is configured to detect the presence of the one or more predefined miniature targets at least in part via capacitive coupling as a result of the physical contact made between the sensing film 124 and the one or more predefined miniature targets (Fig. 1-2F & Fig. 14A and associated text e.g. Para [0030, 0040, 0057 & 0062-0064]).
Regarding claim 4, the combination of Chiang and Zhao teaches the device of claim 2, wherein: the one or more predefined miniature targets include: an ion, a nucleic acid, a polarized molecule, an antigen, an antibody, an enzyme, a cell, a protein, a virus, or a bacterium (Fig. 1-2F & Fig. 14A and associated text (e.g. Para [0030])).
Regarding claim 5, the combination of Chiang and Zhao teaches the device of claim 2, wherein when the device is configured to drive the one or more predefined miniature targets to the second opening at least in part through electrical biases applied to the first transistor, the second transistor, and the third transistor (Fig. 1-2F & Fig. 14A and associated text).
Regarding claim 7, the combination of Chiang and Zhao teaches the device of claim 1, wherein the sensing film is 124 disposed between the structure and the substrate (Fig. 1-2A & Fig. 14).
Regarding claim 8, the combination of Chiang and Zhao teaches the device of claim 1, wherein: the first gate, the second gate, and the third gate include a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer, respectively; and the first gate dielectric layer has a greater dielectric constant than the third gate dielectric layer (Chiang’s Fig, 1-2A & 14A and Zhao’s Fig. 1).
Regarding claim 9, the combination of Chiang and Zhao teaches the device of claim 8, wherein: the first gate dielectric layer contains hafnium oxide; and the third gate dielectric layer contains silicon oxide (ZHAO’s Fig. 1 and Para [0031 & 0049-0050]).
Regarding claim 10, while Chiang teaches the device of claim 1, wherein: the first gate, the second gate, and the third gate (note 1302isf on the right, see Fig. 14A above) include a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer, respectively; However, Chiang is silent on the first gate dielectric layer and the third gate dielectric layer having different thicknesses. ZHAO teaches a semiconductor device, wherein one transistor with a gate dielectric layer 122 and a another transistor with a gate dielectric layer 112 (Fig. 1), wherein the gate dielectric layers (122 & 112) have different thicknesses. This has the advantage of allowing for further miniaturization, reduced leakage current, lower operating voltages and improved thermal stability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chiang with gate dielectric layers, as taught by ZHAO, so as to obtain an improved semiconductor device.
Regarding claim 11, the combination of Chiang and Zhao teaches the device of claim 1, wherein: the first gate, the second gate, and the third gate (note 102isf on the right in Fig. 14A above ) include a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer, respectively; and the first gate dielectric layer and the third gate dielectric layer have different lateral dimensions (note the different lateral dimensions between the gate dielectric layers of the first and third transistors in Fig. 14 above).
Regarding claim 12, Chiang teaches a device, comprising:
a substrate 110 having a first side and a second side opposite the first side (Fig. 1-2F & Fig. 14A);
a plurality of dielectric structures 136 that extend through the substrate 110 from the first side to the second side (Fig. 1-2A & Fig. 14);
a first voltage reference transistor (1302vrf, see Fig. 14A below), a second voltage reference transistor (1302isf, see Fig. 14A below), and a sensing transistor (1302isf, see Fig. 14A below) each formed over the first side of the substrate 110, wherein the first voltage reference transistor, the sensing transistor, and the second voltage reference transistor are separated by different dielectric structures 136 of the plurality of dielectric structures 136 (Fig. 1-2A & see Fig. 14A above), wherein the sensing transistor (1302isf) is located between the first voltage reference transistor and the second voltage reference transistor (see Fig. 14 below and note the annotations), and wherein the first voltage reference transistor and the second voltage reference transistor have different lateral dimensions (note the difference in lateral dimensions of the first and second voltage reference transistors in Fig. 14A below);
a patterned structure formed on the second side of the substrate, wherein the patterned structure defines a first opening, a second opening, and a third opening that are aligned with the first voltage reference transistor, the sensing transistor, and the second voltage reference transistor, respectively (note the openings above the three transistors in Fig. 14A), and wherein the first opening, the second opening, and the third opening are configured to receive a fluid 132 that contains one or more predefined miniature targets, the one or more predefined miniature targets including: an ion, a nucleic acid, a polarized molecule, an antigen, an antibody, an enzyme, a cell, a protein, a virus, or a bacterium (Para [0030]); and
a sensing layer 124 formed over the second side of the substrate 110, wherein the sensing transistor is configured to detect, at least in part through a capacitive coupling, a presence of the one or more predefined miniature targets in the fluid that attach to the sensing layer in the second opening (Fig. 1-2F & Fig. 14A and associated text e.g. Para [0030, 0040, 0057 & 0062-0064]), and wherein a surface of the sensing layer 124 extends to surfaces of the plurality of dielectric structures 136 (see Fig. 2a).
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Chiang is silent on wherein a first gate dielectric of the first voltage reference transistor has a different thickness than a second gate dielectric of the second voltage reference transistor. ZHAO teaches a semiconductor device, wherein one transistor with a gate dielectric layer 122 and another transistor with a gate dielectric layer 112 (Fig. 1), wherein the gate dielectric layers (122 & 112) have different thicknesses. This has the advantage of allowing for further miniaturization, reduced leakage current, lower operating voltages and improved thermal stability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chiang with gate dielectric layers, as taught by ZHAO, so as to obtain an improved semiconductor device. Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 13, the combination of Chiang and ZHAO teaches the device of claim 12, wherein the first gate dielectric and the second gate dielectric have different material compositions (ZHAO’s Fig. 1 and respective text).
Regarding claim 15, the combination of Chiang and ZHAO teaches the device of claim 12, wherein the sensing layer 124 is formed between the substrate 110 and the structure (ZHAO’s Fig. 1-2A).
Allowable Subject Matter
Claims 26-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 01/05/2026 have been fully considered but they are not persuasive. The Examiner would like to point out that the prior art teaches all of the claim limitations as addressed in the rejection above.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818