DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13, 15 & 30 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. in view of ZHAO et al. (US PUB. 2022/0059576).
Regarding claim 12, Chiang teaches a device, comprising:
a substrate 110 having a first side and a second side opposite the first side (Fig. 1-2F & Fig. 14A);
a plurality of dielectric structures 136 that extend through the substrate 110 from the first side to the second side (Fig. 1-2A & Fig. 14);
a first voltage reference transistor (1302vrf, see Fig. 14A below), a second voltage reference transistor (1302isf, see Fig. 14A below), and a sensing transistor (1302isf, see Fig. 14A below) each formed over the first side of the substrate 110,
wherein the sensing transistor (1302isf) is disposed between the first voltage reference transistor and the second voltage reference transistor laterally in a cross-sectional side view (see Fig. 14 below and note the annotations), wherein the first voltage reference transistor, the sensing transistor, and the second voltage reference transistor are separated by different dielectric structures 136 of the plurality of dielectric structures 136 (Fig. 1-2A & see Fig. 14A above), and wherein the first voltage reference transistor and the second voltage reference transistor have different lateral dimensions (note the difference in lateral dimensions of the first and second voltage reference transistors in Fig. 14A below);
a patterned structure formed on the second side of the substrate, wherein the patterned structure defines a first opening, a second opening, and a third opening that are aligned with the first voltage reference transistor, the sensing transistor, and the second voltage reference transistor, respectively (note the openings above the three transistors in Fig. 14A), and wherein the first opening, the second opening, and the third opening are configured to receive a fluid 132 that contains one or more predefined miniature targets, the one or more predefined miniature targets including: an ion, a nucleic acid, a polarized molecule, an antigen, an antibody, an enzyme, a cell, a protein, a virus, or a bacterium (Para [0030]); and
a sensing layer 124 formed over the second side of the substrate 110, wherein the sensing transistor is configured to detect, at least in part through a capacitive coupling, a presence of the one or more predefined miniature targets in the fluid that attach to the sensing layer in the second opening (Fig. 1-2F & Fig. 14A and associated text e.g. Para [0030, 0040, 0057 & 0062-0064]), and wherein a surface of the sensing layer 124 extends to surfaces of the plurality of dielectric structures 136 (see Fig. 2a).
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Chiang is silent on wherein a first gate dielectric of the first voltage reference transistor has a different thickness than a second gate dielectric of the second voltage reference transistor. ZHAO teaches a semiconductor device, wherein one transistor with a gate dielectric layer 122 and another transistor with a gate dielectric layer 112 (Fig. 1), wherein the gate dielectric layers (122 & 112) have different thicknesses. This has the advantage of allowing for further miniaturization, reduced leakage current, lower operating voltages and improved thermal stability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chiang with gate dielectric layers, as taught by ZHAO, so as to obtain an improved semiconductor device. Furthermore, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Regarding claim 13, the combination of Chiang and ZHAO teaches the device of claim 12, wherein the first gate dielectric and the second gate dielectric have different material compositions (ZHAO’s Fig. 1 and respective text).
Regarding claim 15, the combination of Chiang and ZHAO teaches the device of claim 12, wherein the sensing layer 124 is formed between the substrate 110 and the structure (ZHAO’s Fig. 1-2A).
Regarding claim 30, the combination of Chiang and ZHAO teaches the device of claim 12, further comprising an encapsulation structure 132, wherein the substrate, the plurality of dielectric structures, the first voltage reference transistor, the second voltage reference transistor, the sensing transistor, the patterned structure, and the sensing layer are located within the encapsulation structure (Fig. 1-2F & Fig. 14A.
Allowable Subject Matter
Claims 1-5, 7-11, 21-24, 26, 28-29 & 31 are allowed.
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
With respect to claim 12, applicant's arguments filed 05/07/2026 have been fully considered but they are not persuasive. The Examiner would like to point out that the prior art teaches all of the claim limitations as addressed in the rejection above.
With respect to claims 1 & 21, the amendment overcomes the prior art and said claims are allowable
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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