DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Claims 1-9 and 18-20, in the reply filed on 05/28/2025 is acknowledged. Claims 1-9 and 18-28 are pending. Claims 10-17 have been canceled.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a first source/drain disposed over the first fin structure” and “a second source/drain disposed over the second fin structure” of Claim 21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Currently Figures 5C-1 and 5C-2 show a first and second source/drain disposed adjacent to the first and second fin structures, respectfully.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 21, the claim limitations “a first source/drain disposed over the first fin structure” and “a second source/drain disposed over the second fin structure” is new matter. These limitations are new matter as neither the Applicant’s Specification or Drawings has a source/drain being “disposed over” a fin structure including a first and second set of nanostructures. In at least Figures 5A-1 to 5C-2 of the Applicant’s Drawings, a first fin structure 104a is shown to include nanostructures 108, and the source/drain region (124a) is formed adjacent to the fin structures. For examination purposes, the Examiner will interpret the claim limitations “a first source/drain disposed over the first fin structure” and “a second source/drain disposed over the second fin structure” as “a first source/drain disposed adjacent to the first fin structure” and “a second source/drain disposed adjacent to the second fin structure” as interpreted from the Applicant’s Drawings. Claims 22-28 are also rejected under 25 U.S.C. 112(a) as they depend from and include all of the limitations of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitations “a pull-down transistor comprising a first gate stack wrapping around the first set of nanostructures and the first source/drain feature” and “a pull-up transistor comprising a second gate stack wrapping around the second set of nanostructures and the second source/drain feature.” These limitations in the claim are unclear as it is unclear if the gate stack is wrapped around only the nanostructures, or if the first gate stack is wrapped around the set of nanostructures and the source/drain feature. For examination purposes, the Examiner will interpret the claim to have the gate stack be only wrapped around the set of nanostructures, and not the source/drain as interpreted from the Applicant’s Drawings.
Claim 18 recites the limitations “a pull-down transistor comprising a first gate stack wrapping around a first set of nanostructures and a first source/drain feature” and “a pull-up transistor comprising a second gate stack wrapping around a second set of nanostructures and a second source/drain feature.” These limitations in the claim are unclear as it is unclear if the gate stack is wrapped around only the nanostructures, or if the first gate stack is wrapped around the set of nanostructures and the source/drain feature. For examination purposes, the Examiner will interpret the claim to have the gate stack be only wrapped around the set of nanostructures, and not the source/drain as interpreted from the Applicant’s Drawings. Claims 19-20 are also rejected under 35 U.S.C. 112(b) as they depend from and include all of the limitations of Claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 18-19, 21-22, and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20230074880 A1) hereinafter “Park” in view of Lim et al. (US 20220383948 A1) hereinafter “Lim.”
Regarding Claim 1, Figure 4 of Park teaches: A semiconductor structure (100a), comprising: a first set of semiconductor layers (B; 140B) stacked over a substrate (101) and spaced apart from one another; a second set of semiconductor layers (C; 140C) stacked over the substrate and spaced apart from one another; a first source/drain feature (150B) adjoining the first set of semiconductor layers; a second source/drain feature (152C) adjoining the second set of semiconductor layers; a first contact plug (170B) landing on and partially embedded in the first source/drain feature; and a second contact plug (170C) landing on and partially embedded in the second source/drain feature, wherein a bottom of the first contact plug is lower than a bottom of the second contact plug (Figure 4)
Park does not explicitly teach: a first set of nanostructures and a second set of nanostructures
Figures 7A-7B of Lim teach: a semiconductor device (Paragraph 0071) comprising gate-all-around transistors (Paragraph 0072) over a substrate (P-SUB) wherein the transistors include a first set of nanostructures (Paragraph 0076; NS1) stacked over the substrate
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor layers of Park be a first set of nanostructures and a second set of nanostructures stacked over a substrate because Lim teaches nanostructures are utilized in active regions of gate-all-around transistors (Lim Paragraph 0071).
Regarding Claim 2, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: the first set of semiconductor layers (150B) includes a first semiconductor layer (topmost 150B vertically) which is an uppermost one of the first set of semiconductor layers and a second semiconductor layer (second from the topmost 150B vertically) which is a second uppermost one of the first set of semiconductor layers and the bottom of the first contact plug (170B) is at a predetermined depth (Paragraph 0065).
The combination of the nanostructures of Lim with the structure of Park will yield a structure such that the semiconductor layers of Park are nanostructures.
Park does not teach: the bottom of the first contact plug is located at a level between a bottom surface of the first nanostructure and a top surface of the second nanostructure.
However, one having ordinary skill in the art would recognize that the predetermined depth of the first contact plug, as stated in Park, could be between a bottom surface of the first semiconductor layer and a top surface of the second semiconductor layer as one would have reasonable success having the contact plug located at this depth as long as the contact plug is electrically connected to the source/drain region.
Regarding Claim 3, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: the second set of semiconductor layers (140C) includes a third semiconductor layer (uppermost 140C vertically) which is an uppermost one of the second set of semiconductor layers, and the bottom of the second contact plug is at a predetermined depth (Paragraph 0066).
The combination of the nanostructures of Lim with the structure of Park will yield a structure such that the semiconductor layers of Park are nanostructures.
Park does not teach: the bottom of the second contact plug is located at a level between a top surface of the third nanostructure and a bottom surface of the third nanostructure.
However, one having ordinary skill in the art would recognize that the predetermined depth of the second contact plug, as stated in Park, could be between a top surface of the third semiconductor layer and a bottom surface of the third semiconductor layer as one would have reasonable success having the contact plug located at this depth as long as the contact plug is electrically connected to the source/drain region.
Regarding Claim 4, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: the first set of semiconductor layers (140B) is located over a P-type well region (105B; Paragraph 0027: Where active region 105B is formed to have a first-type conductivity, P-type), and the second set of semiconductor layers (140C) is located over an N-type well region.
The combination of the nanostructures of Lim with the structure of Park will yield a structure such that the semiconductor layers of Park are nanostructures.
Regarding Claim 9, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: a first gate stack (160B) wrapping around the first set of semiconductor layers (140B) and a second gate stack (160C) wrapping around the second set of semiconductor layers (140C)
The combination of the nanostructures of Lim with the structure of Park will yield a structure such that the semiconductor layers of Park are nanostructures.
Park does not teach: a static random-access memory (SRAM) cell over the substrate, comprising: a pull-down transistor and a pull-up transistor.
Figures 2 and 7A-7B of Lim teach: an SRAM cell (21; Paragraph 0035) over a substrate (P-SUB; Paragraph 0071: Where figures 7A-7B are cross-sections of the cell.) comprising: a pull-down transistor (PD1/PD2) and a pull-up transistor (PU1/PU2)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a static random-access memory (SRAM) cell over the substrate, comprising: a pull-down transistor and a pull-up transistor because Lim teaches N-type and P-type transistors are used as pull-down and pull-up transistors in SRAM cells to output data having opposite phases (Lim Paragraph 0036).
Regarding Claim 18, Figure 4 of Park teaches: A semiconductor structure (100a), comprising: a first transistor (B) comprising a first gate stack (160B) wrapping around a first set of semiconductor layers (140B) and a first source/drain feature (150B); and a second transistor comprising a second gate stack (160C) wrapping around a second set of semiconductor layers (140C) and a second source/drain feature (152C); an interlayer dielectric layer (190) over the first source/drain feature and the second source/drain feature; a first contact plug (170B)in the interlayer dielectric layer and on the first source/drain feature; and a second contact plug (170C) in the interlayer dielectric layer and on the second source/drain feature, wherein a first contact area between first contact plug and the first source/drain feature is greater (Figure 4, where the longer contact plug, 170B, has more surface area in contact with the first source/drain than the shorter contact plug, 170C, and therefore has more contact area.) than a second contact area between second contact plug and the second source/drain feature (Figure 4).
Park does not teach: a pull-down transistor comprising a first set of nanostructures and a pull-up transistor comprising a second set of nanostructures.
Figures 2 and 7A-7B of Lim teach: a semiconductor device (Paragraph 0071) comprising: a pull-down transistor (PD1/PD2) and a pull-up transistor (PU1/PU2) over a substrate (P-SUB), wherein the pull-up and pull-down transistors are gate-all-around transistors (Paragraph 0072) and the transistors include a first set of nanostructures (Paragraph 0076; NS1) and a second set of nanostructures (NS2) stacked over the substrate.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a pull-down transistor and a pull-up transistor because Lim teaches N-type and P-type transistors are used as pull-down and pull-up transistors to output data having opposite phases (Lim Paragraph 0036), and further, to have the semiconductor layers of Park be a first set of nanostructures and a second set of nanostructures stacked over a substrate because Lim teaches nanostructures are utilized in active regions of gate-all-around transistors (Lim Paragraph 0071).
Regarding Claim 19, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: the first set of semiconductor layers (140B) is located over a P-type well region (105B; Paragraph 0027: Where active region 105B is formed to have a first-type conductivity, P-type), and the second set of semiconductor layers (140C) is located over an N-type well region.
The combination of the nanostructures of Lim with the structure of Park will yield a structure such that the semiconductor layers of Park are nanostructures.
Regarding Claim 21, Figure 4 of Park teaches: A semiconductor structure (100a), comprising: a first fin structure (B) and a second fin structure (C) each disposed over a substrate (101), wherein the first fin structure includes a first set of semiconductor layers (140B), and the second fin structure includes a second set of semiconductor layers (140C); a first source/drain (150B) disposed adjacent to the first fin structure; a second source/drain (152C) disposed adjacent to the second fin structure; an interlayer dielectric layer (190) disposed over the first source/drain and the second source/drain; a first conductive contact (170B) that extends at least partially through the interlayer dielectric layer and the first source/drain; and a second conductive contact (170C) that extends at least partially through the interlayer dielectric layer and the second source/drain, wherein the first conductive contact and the second conductive contact have different depths (Figure 4). [See Examiner’s interpretation in the 35 U.S.C. 112(b) rejection of Claim 21 above.]
Park does not explicitly teach: a first set of nanostructures and a second set of nanostructures
Figures 7A-7B of Lim teach: a semiconductor device (Paragraph 0071) comprising gate-all-around transistors (Paragraph 0072) over a substrate (P-SUB) wherein the transistors include a first set of nanostructures (Paragraph 0076; NS1) stacked over the substrate
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor layers of Park be a first set of nanostructures and a second set of nanostructures stacked over a substrate because Lim teaches nanostructures are utilized in active regions of gate-all-around transistors (Lim Paragraph 0071).
Regarding Claim 22, Figure 4 of Park teaches: the first fin structure (B) is formed over a first doped well region (105B); and the second fin structure (C) is formed over a second doped well region (105C) that has a different type of conductivity (Paragraph 0027) than the first doped well region.
Regarding Claim 26, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the first fin structure, the second fin structure, the first source/drain, and the second source/drain are parts of an electronic memory circuit.
Figures 2 and 7A-7B of Lim teach: an SRAM cell (21; Paragraph 0035) over a substrate (P-SUB; Paragraph 0071: Where figures 7A-7B are cross-sections of the cell.) comprising gate-all-around transistors (Paragraph 0072).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first fin structure, the second fin structure, the first source/drain, and the second source/drain are parts of an electronic memory circuit because Lim teaches gate-all-around transistors are utilized in memory structures (Lim Paragraph 0072).
Regarding Claim 27, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the electronic memory circuit comprises a static random-access memory (SRAM) circuit cell.
Figures 2 and 7A-7B of Lim teach: an SRAM cell (21; Paragraph 0035) over a substrate (P-SUB; Paragraph 0071: Where figures 7A-7B are cross-sections of the cell.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the electronic memory circuit comprises a static random-access memory (SRAM) circuit cell because Lim teaches SRAM cells are utilized as a volatile memory cell in memory devices (Lim Paragraph 0026).
Regarding Claim 28, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the first fin structure and the first source/drain are parts of a pull-down transistor of the SRAM circuit cell; and the second fin structure and the second source/drain are parts of a pull-up transistor of the SRAM circuit cell.
Figures 2 and 7A-7B of Lim teach: an SRAM cell (21; Paragraph 0035) over a substrate (P-SUB; Paragraph 0071: Where figures 7A-7B are cross-sections of the cell.) comprising: a pull-down transistor (PD1/PD2) and a pull-up transistor (PU1/PU2)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first fin structure and the first source/drain are parts of a pull-down transistor of the SRAM circuit cell; and the second fin structure and the second source/drain are parts of a pull-up transistor of the SRAM circuit cell because Lim teaches N-type and P-type transistors are used as pull-down and pull-up transistors in SRAM cells to output data having opposite phases (Lim Paragraph 0036).
Claims 6, 23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20230074880 A1) hereinafter “Park” in view of Lim et al. (US 20220383948 A1) hereinafter “Lim” and Park et al. (US 20230116172 A1) hereinafter “Park2”.
Regarding Claim 6, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the first contact plug and the second contact plug are in contact with each other.
Figure 2D of Park2 teaches: a common contact plug (172) in contact with a first source/drain (leftmost 150) and a second source/drain (rightmost 150)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first contact plug and the second contact plug be in contact with each other because Park2 teaches forming a common contact plug can yield a semiconductor device having improved production yield (Park2 Paragraph 0090).
Regarding Claim 23, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: a dielectric structure disposed at least over a boundary between the first doped well and the second doped well.
Figures 1 and 2D of Park2 teach: a dielectric structure (180) disposed between a first active region (105a) and a second active region (105b)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a dielectric structure disposed between a first and second active region because Park2 teaches gate isolation patterns are utilized between active layers to isolate transistor regions (Park2 Paragraph 0046).
Regarding Claim 25, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the first conductive contact physically extends to the second conductive contact
Figure 2D of Park2 teaches: a common contact plug (172) in contact with a first source/drain (leftmost 150) and a second source/drain (rightmost 150)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first conductive contact physically extends to the second conductive contact because Park2 teaches forming a common contact plug can yield a semiconductor device having improved production yield (Park2 Paragraph 0090).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20230074880 A1) hereinafter “Park” in view of Lim et al. (US 20220383948 A1) hereinafter “Lim,” Sung et al. (US 20220310818 A1) hereinafter “Sung” and Chen et al. (US 20190304833 A1) hereinafter “Chen.”
Regarding Claim 7, the combination of Park and Lim teaches all of the limitations of the claimed invention as stated above.
Figure 4 of Park teaches: an interlayer dielectric layer (190)
Park does not teach: a first dielectric fin structure and a second dielectric fin structure over the substrate, wherein the first source/drain feature is located between and in contact with the first dielectric fin structure and the second dielectric fin structure;
Figure 7D of Sung teaches: a first dielectric fin structure (leftmost 712) and a second dielectric fin structure (middle 712), with a first source/drain feature (752) located between and in contact with the first and second dielectric fin structure.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first dielectric fin structure and a second dielectric fin structure over the substrate, wherein the first source/drain feature is located between and in contact with the first dielectric fin structure and the second dielectric fin structure because Sung teaches dielectric fin structures have advantages including the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing (Sung Paragraph 0027).
Park does not teach: a contact etching stop layer along the first source/drain feature, the first dielectric fin structure and the second dielectric fin structure;
Figure 5 of Chen teaches: a contact etch stop layer (CESL) (60) conformally formed over source/drain regions (56)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a contact etching stop layer along the first source/drain feature, the first dielectric fin structure and the second dielectric fin structure because Chen teaches the conformal deposition of a contact etch stop layer provides the mechanism to stop an etch process when forming contacts (Chen Paragraph 0025).
The combination of a contact etch stop layer with the structure of Park, will yield a structure such that the interlayer dielectric layer is over the contact etching stop layer.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20230074880 A1) hereinafter “Park” in view of Lim et al. (US 20220383948 A1) hereinafter “Lim,” Sung et al. (US 20220310818 A1) hereinafter “Sung,” Chen et al. (US 20190304833 A1) hereinafter “Chen” and Park et al. (US 20230116172 A1) hereinafter “Park2.”
Regarding Claim 8, the combination of Park, Lim, Sung, and Chen teaches all of the limitations of the claimed invention as stated above.
Park does not teach: the first contact plug partially covers an upper surface of the first dielectric fin structure.
Figure 2D of Park2 teaches: a common contact plug (172) covers an upper surface of a dielectric fin structure (180)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first contact plug partially covers an upper surface of the first dielectric fin structure because Park2 teaches forming a common contact plug can yield a semiconductor device having improved production yield (Park2 Paragraph 0090).
Allowable Subject Matter
Claims 5, 20, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have a ratio of the second dimension to the first dimension is in a range from about 0.6 to about 0.8 along with the other limitations of Claim 1.
Regarding Claim 20, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have the first bottom surface of the third contact is lower than the second bottom surface of the third contact along with the other limitations of Claim 18.
Regarding Claim 24, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have a ratio of the first depth and the second depth is in a range between about 0.6 and about 0.8 along with the other limitations of Claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891