DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04 February 2026 have been fully considered but they are respectfully not persuasive, the responses have been set forth below.
Applicant submits that the prior art of record does not teach or disclose the third diffusion barrier layer prevents copper diffusion (Remarks; p. 6). However, Applicant's arguments are directed against the references individually, and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As modified by Hung in the previous rejection of record, the equivalence between SiN and carbon-doped SiN was established. As such, the “third diffusion barrier layer” is carbon-doped SiN and implicitly satisfies the limitation of the intended use of “preventing copper diffusion”. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure (as modified by Hung) is capable of performing the intended use, then it meets the claim.
Applicant states “Even if the metal resistance layer 630 in Ding corresponded to the structure of the metal resistance layer in the present application, the insulating layer 210 corresponded to the structure of the selected interlayer film in the present application, the insulating layer 220 corresponded to the structure of the third diffusion barrier layer in the present application, and the insulating layer 230 corresponded to the structure of the next interlayer film of the present application, Applicant respectfully submits that the combination structure of the two is not the same….” (Remarks; p. 6-7). Examiner notes Applicant has interpreted different elements of the prior art to correspond to various elements of the claim, and has not addressed the elements mapped by the Examiner from the prior rejection of record. As such the argument is moot. The claims have not been amended with features to overcome the prior art of record as mapped and presented in the previous Office action, and the rejection is updated according to the amendments and is presented below, along with new 112 issues in the dependent claims introduced by the new amendment.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 15, it recites “forming a next interlayer film” in line 4. It is unclear if this recitation of “a next interlayer film” is meant to refer to the same “a next interlayer film” recited in claim 1, or if it intends to refer to another “a next interlayer film”. For the purpose of applying prior art, this will be interpreted as “wherein forming the next interlayer film” to establish proper antecedence with claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shaofeng Ding (US 20200235087 A1; hereinafter Ding) in view of Ching-Wen Hung et al. (US 20140246730 A1; hereinafter Hung), Imran Khan et al. (US 20130341759 A1; hereinafter Khan), and Jeffrey Amadon et al. (US 20040239478 A1; hereinafter Amadon).
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Regarding Claim 1, Ding teaches a method for manufacturing an integrated metal resistance layer, comprising the following steps:
step 1, selecting a formation position of a metal resistance layer (Ding; Fig. 8; 630; ¶0050; ¶0094), wherein the formation position of the metal resistance layer (630) is located on a surface of a selected interlayer film (Ding; Fig. 8; 630 is located on top of a surface of selected interlayer film which comprises a top portion of 210; wherein ¶0028 states more insulating layers may be included, and only five are shown for convenience of illustration), an interlayer film (210) below the metal resistance layer (630) is the selected interlayer film (therefore the top portion of 210 is the selected interlayer film), which is embedded with a selected copper connection (Fig. 8; 300 {which comprises 310, 320, 330, 340} is inlaid in the top portion of 210, ¶0058 states it is copper), and the selected copper connection (300) is a first copper connection (300);
wherein a zeroth interlayer film (bottom portion of 210) and a contact plug (760; ¶0046) passing through the zeroth interlayer film (760 passes through bottom portion of 210),
wherein a bottom of the first copper connection (bottom of 300) is connected to the contact plug (760 is connected to a bottom of 300),
wherein the first copper connection (300) is formed by means of a single damascene process (as it is described as copper in ¶0058 and/or a metal nitride, this limitation is satisfied because it can be formed via single damascene or dual damascene processes; wherein a single damascene process is interpreted as deposition of a single metal without a liner, as shown in Ding Fig. 11);
step 2, completing formation processes of the selected copper connection (300) and the selected interlayer film (top portion of 210) on a semiconductor substrate (100) (as shown in Fig. 12);
step 3, forming the metal resistance layer (630), comprising the following sub-steps:
step 31, depositing a third diffusion barrier layer (Fig. 12; capping layer 220+232 comprises SiN and is a diffusion barrier layer; ¶0037 and ¶0027 states 220 and 232 are capping layers; ¶0029 states a boundary may not exist between 220 and 232; ¶0036 states they may comprise SiN); a bottom surface of the third diffusion barrier layer (bottom of 220+232) is in contact with a top surface of the selected copper connection (top of 300) and a top surface of the selected interlayer film (top of 210); and a next interlayer film (Fig. 8; 234+240; ¶0026-¶0036);
depositing a material layer (as shown and described in Ding; Fig. 13; ¶0130; “The conductive patterns 600 may be formed via a deposition process and an etching process. For example, a conductive layer may be formed on substantially the entire lower insulating layer 232 via a deposition process.”) of the metal resistance layer (630), wherein a resistivity of the material layer of the metal resistance layer is greater than a resistivity of copper (¶0094 discloses that 600 may be TiN which is the same material as the instant application, therefore this limitation is satisfied), wherein the material layer of the metal resistance layer comprises a first titanium nitride layer or a second cobalt layer (TiN; ¶0094); a bottom surface of the metal resistance layer (bottom of 630) is in contact with a top surface of the third diffusion barrier layer (top of 220+232; as shown in Fig. 13);
step 32, performing patterned etching on the material layer of the metal resistance layer to form the metal resistance layer in a formation region of the metal resistance layer in sequence, the material layer of the metal resistance layer after the patterned etching forms the metal resistance layer (as described in Ding ¶0130 and shown in Fig. 12 and Fig. 13), wherein the formation region of the metal resistance layer (630) is located on the surface of the selected interlayer film (210) (630 is “on” the surface of 210 which is commensurate in scope with what the Applicant has provided in Fig. 3F wherein the term “on” means there may be intermediate layers such as Applicant’s 209b); and
step 4, forming a next copper connection (Fig. 23; 400 which comprises 410-450 and is described as being copper in ¶0058) and vias (Fig. 23; vias comprise 710, 720, 730, 740, 750 are at a bottom of next copper connections 410, 420, 430, 440, 450), wherein the vias have two different heights (vias 740 and 750 have different heights), and a height of a via (740) on the top of the metal resistance layer (630) and the bottom of the next copper connection (400) is less than a height of a via (750) on the top of the selected copper connection (300) and the bottom of the next copper connection (400) (as shown in Ding; Fig. 23),
wherein an etching process of an opening of the via at the bottom of the next copper connection (400) stops at a surface of the selected copper connection (300) or the metal resistance layer (630), so as to form the vias of two different heights at the bottom of the next copper connection (as shown clearly in Ding Fig. 21; where V_TR5 stops at the surface of 300 and V_TR4 stops at the surface of 630, and these vias are at the bottom of next copper connection 400),
wherein the next copper connection (400) and the via (740/750) at the bottom of the next copper connection are both formed in the next interlayer film (234+240), a bottom surface of the next interlayer film (bottom of 234+240) contacts a side surface of the metal resistance layer (sides of 630), and the top surface of the third diffusion barrier layer (top of 220+232) outside the metal resistance layer (630) (as shown in Fig. 8).
Ding describes in ¶0028 that more insulating layers may be included, and only five are shown for convenience of illustration, but does not expressly disclose wherein the interlayer film (210) comprises two films, one in the upper portion surrounding (300) and one in the lower portion surrounding (760), and wherein the zeroth interlayer film and the contact (760) are formed in a middle of line process.
However, Ding shows in Fig. 11 that via 760 is formed between copper connections 300 and the devices (such as transistors; ¶0025) on the substrate 100.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that Ding’s multiple insulating films (¶0028) would include a zeroth insulating layer at the level of the via 760 and formed in a middle end of line process because the via 760 has a tall aspect ratio which would require different etching/formation parameters than the formation of the copper connection 300. This would result in 210 comprising the selected interlayer film in the upper portion around 300 and a zeroth interlayer film in the lower portion around the via 760.
Ding does not expressly disclose the material of the third diffusion barrier layer is a carbon-doped silicon nitride layer, the third diffusion barrier layer is used to block a diffusion of copper between the selected interlayer film (upper portion of 210) and the next interlayer film (234+240).
In the same field of endeavor, Hung teaches a semiconductor method/device including a cap layer (Hung; Fig. 4; 130; ¶0019) over a dielectric layer (Hung; Fig. 4; 120; ¶0019) with an integrated resistive layer (Hung; Fig. 4; 140; ¶0021). Hung teaches in ¶0019 using carbon doped silicon nitride or silicon nitride as the cap layer 130, thereby establishing the equivalence of using SiN or carbon-doped SiN as a cap layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the carbon doped SiN cap layer of Hung for the SiN cap layer in Ding. One of ordinary skill in the art would have motivation to make this substitution because Hung establishes in ¶0019 these are equivalent for their intended use as a cap layer and to protect the devices/structures underneath during subsequent manufacturing processes. The substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). This obvious substitution implicitly satisfies the limitation of “the third diffusion barrier layer is used to block a diffusion of copper between the selected interlayer film (upper portion of 210) and the next interlayer film (234+240)” because it is of the same material as in the instant application.
Ding does not expressly disclose forming a fourth silicon oxide layer on the metal resistance layer, a bottom surface of the fourth silicon oxide layer is in contact with a top surface of the metal resistance layer, and performing the patterned etching (Ding; ¶0130) in sequence, wherein an interlayer film contacts top and side surfaces of the silicon oxide layer.
In the same field of endeavor, Khan teaches depositing a metal resistance layer (Khan; Fig. 1B; 1008; ¶0013), depositing a silicon oxide layer over the metal resistance layer (Khan; Fig. 1B; 1009; ¶0013), a bottom surface of the silicon oxide layer (bottom of 1009) is in contact with a top surface of the metal resistance layer (top of 1008) (as shown in Fig. 1B), and using a photoresist (Khan; Fig. 1B; 1010; ¶0013) to pattern and etch the layers sequentially to form the metal resistor (Khan; Fig. 1C; 1012; ¶0013-¶0014; wherein 1009 is implicitly patterned sequentially first because it is first material to be etched from the direction of the photoresist 1010; wherein the bottom surface of the silicon oxide layer is in contact with the top surface of the metal resistance layer); wherein an interlayer film (Fig. 1C; 1014; ¶0014) contacts top and side surfaces of the silicon oxide layer (top and sides of 1009) and a side surface of the metal resistance layer (sides of 1012) (as shown in Fig. 1C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the silicon oxide layer deposited and etched in sequence with the resistance layer (with the features above of Khan) in the method of Ding to act as a hard mask (Khan; ¶0013) for the metal resistance layer in order to aid with the patterning of the high precision resistor.
Ding does not expressly disclose wherein the next copper connection (400) and the via at the bottom of the next copper connection (750) are formed by means of a dual damascene process.
In the same field of endeavor, Amadon teaches this in ¶0056-0058 and Fig. 2F. Amadon discloses in ¶0022 that a dual damascene process may be used to connect a thin film resistor to metal levels and active devices. Fig. 2F shows conductive lines 72 and vias 74 are above the resistor and formed via dual damascene processes (Amadon; ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual damascene process of Amadon to form the connections and vias above the resistor in the process/device of Ding. One of ordinary skill in the art would have motivation to make this modification in order to provide a good quality interconnect, and because it is a well-known process in the field of semiconductors (Amadon; ¶0056).
Regarding Claim 12, modified Ding teaches the method for manufacturing the integrated metal resistance layer according to claim 1, but is silent regarding wherein a thickness of the first titanium nitride layer (630) is 50-150 nm.
In the same field of endeavor, Amadon teaches a similar device with an integrated thin film resistor in the claimed range (Amadon; ¶0036-0037; where a resistor material 12 of TiN is deposited to be 100nm thick, and states the sheet resistance value depends on the type of material used).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the thickness of the TiN of Amadon as the thickness of the TiN resistor material of Ding in order to obtain a desired resistance value for the material (TiN) used (Amadon; ¶0037).
Regarding Claim 14, modified Ding teaches the method for manufacturing the integrated metal resistance layer according to claim 1, but is silent regarding wherein in step 32, a selected region of the patterned etching is defined by means of a photolithography process. Ding describes in ¶0130 that material is deposited on the entire layer below and etched to form the patterns 610, 620, and 630, but is silent regarding the exact etching process used.
In the same field of endeavor, Amadon teaches in ¶0043 using photolithography to pattern and etch a resistor layer. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the photolithography of Amadon for the etching of Ding. One of ordinary skill in the art would have motivation to use the photolithography of Amadon because it is shown to be applicable to patterning a resistor layer, and photolithography is a well-established patterning technique in the art to provide a precisely defined feature.
Regarding Claim 15, modified Ding teaches the method for manufacturing the integrated metal resistance layer according to claim 13, wherein the dual damascene process comprises the following sub-steps:
forming the next interlayer film (Ding; Fig. 20; 234+240);
forming a trench of the next copper connection and the opening of the via at the bottom of the next copper connection in the next interlayer film (234+240) (as shown in Ding Fig. 21; trenches and via openings L_TR4, V_TR4, L_TR5, and V_TR5 are formed in 234+240), the opening of the via at the bottom of the next copper connection being located at the bottom of the trench of the next copper connection (as shown in Fig. 21); and
forming a metal copper (Ding; Fig. 22; trenches/vias are filled with metal 800 which is copper as described in ¶0160), and performing chemical mechanical polishing to obtain the next copper connection composed of the metal copper filling the trench of the next copper connection and the via composed of the metal copper filling the opening of the via at the bottom of the next copper connection (as shown in the progression of Fig. 22 to Fig. 23; wherein 800 is planarized via CMP as described in ¶0162).
Ding does not expressly disclose forming a barrier layer before the metal copper in a dual damascene process.
In the same field of endeavor, Amadon teaches this in ¶0056-0058 and Fig. 2F. Amadon discloses in ¶0022 that a dual damascene process may be used to connect a thin film resistor to metal levels and active devices. Fig. 2F shows conductive lines 72 and vias 74 are above the resistor and formed via dual damascene processes (Amadon; ¶0056).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual damascene process of Amadon in connections and vias above the resistor in the process/device of Ding. One of ordinary skill in the art would have motivation to make this modification in order to provide a good quality interconnect, and because it is a well-known process in the field of semiconductors (Amadon; ¶0056).
Regarding Claim 16, modified Ding teaches the method for manufacturing the integrated metal resistance layer according to claim 1, and wherein a front end of line process comprises forming a gate structure on the semiconductor substrate (100) and forming a source region and a drain region on two sides of the gate structure (as described in ¶0025 of Ding; who teaches a transistor formed in the substrate 100 which implicitly includes a gate structure and S/D regions on two sides of the gate structure).
Regarding Claim 17, modified Ding teaches the method for manufacturing the integrated metal resistance layer according to claim 1, wherein a thickness of the second cobalt layer is 10-50 nm (this limitation is implicitly satisfied because the second cobalt layer of claim 1 is optional).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898