Attorney’s Docket Number: 44020051US02
Filing Date: 8/2/2022
Claimed Priority Date: 8/3/2021 (US 63/228,765)
Inventors: Kang et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the election and amendment filed on 7/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 7/11/2025 in reply to the Office action in paper no. 7, mailed on 7/11/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Inventions Election
Applicant's election with traverse of invention I, reading on a semiconductor device, in the reply filed on 7/11/2025 is acknowledged. The traversal is on the grounds that there is no search and/or examination burden in examining both method claims 15-20 and device claims 1-14. This is not found persuasive.
Subsequent to the election, the applicant amended claims 15–20 to depend from the device claims such that all pending claims are now directed to the device invention. Accordingly, the arguments presented in the traversal are moot, as the claims that formed the basis of the restriction between the method and device inventions are no longer pending in their original form. Examination, therefore, proceeds on the merits of the pending claims directed to the elected device invention. The restriction requirement between the device invention and the previously identified method invention is maintained for the remainder of prosecution. Should the applicant later present claims directed to the previously nonelected method invention, such claims will be withdrawn from consideration as being directed to a nonelected invention.
Accordingly, the requirement is still deemed proper and is therefore made final.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the common source line comprising the sacrificial, oxide, and polysilicon layers recited in claims 13 and 19 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Claims 13 and 19 recite a common source line comprising a sacrificial layer an oxide layer, and a polysilicon layer. The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter in claims 13 and 19. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 2 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 2 recites “the strapping region comprises a first plurality of memory holes that is less dense than a second plurality of memory holes in a non-strapping region.” However, the specification does not reasonably convey to one of ordinary skill in the art that the inventors had possession of a strapping region comprising memory holes.
The specification consistently describes and illustrates different structures for the memory region and the strapping region. In particular, the openings in the memory region are described as memory holes 120 in which transistor layers (e.g., layers 128) are subsequently formed. See, e.g., figs. 4-5B.
The specification does not describe or illustrate memory holes formed within the strapping regions (see, e.g., figs. 20A and 21A), nor does it describe the formation of transistor layers within such a region.
The only reference to a strapping region comprising a plurality of memory holes appears as a single statement in paragraph 0050, which recites language substantially identical to that of claim 2. This isolated statement, without supporting description of structure, fabrication, or illustration in the drawings, does not reasonably convey possession of the claimed subject matter, particularly in view of the remainder of the specification which only describes the non-strapping region as comprising memory holes.
The disclosure of paragraph 0050 appears to merely restate the claim limitation without providing a description of the corresponding structure or process, and therefore does not demonstrate possession of the claimed subject matter. Ariad Pharmaceuticals, Inc. v. Eli Lilly & Co. (598 F.3d 1336, Fed. Cir. 2010).
Accordingly, the specification fails to provide adequate written description support for the limitation recited in claim 2.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9 and 10 are rejected under 35 U.S.C. 112(b) as being indefinite.
The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 recites the limitation "the poly-silicon word line". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim (US 2013/0171806).
Regarding claim 1, Shim (see, e.g., fig. 1 and 2A) shows all aspects of the instant invention including a semiconductor memory device comprising a memory array comprising at least one select-gate-for-drain (SGD) transistor 135au and at least one memory transistor 135a, the array having at least one strapping region and at least one strapping contact 155a, the contact connecting the SGD transistor to a strapping line 160a.
Regarding claim 6, Shim (see, e.g., par. 0073) shows that the strapping line comprises one or more of W, Al, Cu, Ti, Ta, Mo and Ru.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, 7, 8, 11, 12, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kameoka (US 2015/0255486) in view of Shim.
Regarding claim 1 Kameoka (see, e.g., figs. 1 and 2) shows most aspect of the instant invention including a semiconductor device 10 comprising a memory array comprising at least one SGD transistor SG and at least one memory transistor ML. Kameoka, however, fails to show the array having a strapping region and at least one strapping contact connecting the SGD transistor to a strapping line.
Regarding claim 7, Kameoka (see, e.g., figs. 1 and 2) shows a semiconductor memory device 10 comprising:
A memory stack ML on a substrate 12, the stack comprising alternating layers of word line WL and dielectric materials 62
A plurality of memory transistors 60 extending through the stack
A filled slit ILP1 extending through the stack and adjacent the transistors, and
A plurality of SGD transistors SG in a top portion of the stack
Kameoka, however, fails to show that the at least one SGD transistor is electrically connected to a strapping line.
Regarding claims 1 and 7, Shim (see, e.g., par. 0074) teaches that connecting the SGD transistor to a strapping line would result in the array having good reliability and high operating speed. Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the strapping region of Shim in the device of Kameoka to have an array with good reliability and high operating speed.
Regarding claims 3 and 8, Kameoka (see, e.g., fig. 2) teaches that the SGD transistors comprise a polysilicon word line SG.
Regarding claim 4, Kameoka (see, e.g., fig. 2) shows the memory transistor comprises first 60 and second 72 materials, the first material has a higher resistance than the second material.
Regarding claim 5, Kameoka (see, e.g., fig. 2) shows the second material 72 is adjacent to a slit region ILP1 of the array.
Regarding claim 15, Kameoka (see, e.g., figs. 10 and 14) shows the device further comprising a plurality of memory holes 26 extending through the stack ML, transistor layers 28/SP in the holes forming the memory transistors, a bit line pad 40 on a top surface of the memory transistors, a low resistivity material 72 in each of a plurality of recessed regions formed in the word lines 60. Shim (see, e.g., fig. 2A), an SGD contact 155a, wherein the strapping line 160a contacts the SGC contact.
Regarding claims 11 and 16, Kameoka (see, e.g., fig. 2) shows that each of the memory transistors comprises one or more transistor layers 28/SP selected from AlO, a blocking oxide, a trap material, a tunnel oxide, and a channel material.
Regarding claim 17, Kameoka (see, e.g., par.0072) shows that the low-resistivity material 72 comprises one or more of W, Ru, Al, Ir, Ta, Ti, Pt, Mo, Ni or a silicide thereof.
Regarding claims 12 and 18, Kameoka (see, e.g., par.0076) shows that the filled slit ILP1 comprises an insulator material selected from one or more of SiO, SiN, and SiON.
Regarding claims 14 and 20, see the comment stated above in paragraph 25 with respect to claim 6, which are considered repeated here.
Regarding claims 15-18 and 20, it is noted that Kameoka/Shim show all aspects of the semiconductor device according to the claimed invention (see paragraphs 36-40 above) and that the method steps recited in the claims are intermediate method steps that does not affect the structure of the final device.
Allowable Subject Matter
Claims 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
March 7, 2026