DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/18/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 recites “”an etch stop layer” has antecedent issue which should be “the etch stop layer”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 15 are rejected under 35 U.S.C. 103 as being obvious over Wong et al (US 2021/0036122 A1) in view of Wu et al. (US PGPUB 2020/0411415 A1) further in view of Wang et al. (US Patent 10692987 B2) and Lin et al. (US PGPUB 2021/0083046 A1)
Regarding claims 12: Wong teaches in Fig. 18A-18D about a semiconductor device, comprising:
a substrate 202;
nanostructured [0012] charnel regions 204a disposed on the substrate;
a gate structure 264 surrounding the nanostructured channel regions;
a source/drain (S/D) region 230 disposed on the substrate;
a contact structure (comprising 294) disposed on the S/D region, wherein the contact structure comprises:
a silicide layer [0049] disposed on the S/D region;
a conductive layer 294 disposed on the silicide layer,
a dielectric layer (292) disposed along a sidewall of the conductive layer; and
a first air spacer disposed on the silicide layer and along a sidewall of the dielectric layer and in contact with a top surface of the silicide layer;
a conductive capping layer disposed on a gate metal layer of the gate structure; and
a second air spacer ([0050] spacers having width W1, W2, W3, W4 etc.) disposed on and in contact with a top surface of a gate dielectric layer of the gate structure and disposed along and in contact with sidewalls of the conductive capping layer and the gate metal layer.
Wong does not explicitly show a silicide layer [0049] disposed on the S/D region and the first air spacer in contact with a top surface of the silicide layer.
Wu teaches in Fig. 3 a silicide layer 272 disposed on the S/D region 240A and the first air spacer 284 in contact with a top surface of the silicide layer.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Wu’s teachings to Wong’s semiconductor device to have contact structure with reduced contact resistance.
Wong in view of Wu does not explicitly show a conductive capping layer disposed on a gate metal layer of the gate structure; and
a second air spacer disposed on and in contact with a top surface of a gate dielectric layer of the gate structure and disposed along and in contact with sidewalls of the conductive capping layer and the gate metal layer.
Wang teaches in Fig. 20 about a conductive capping layer 190 disposed on a gate metal layer 166 of the gate structure; and
a second air spacer 184 disposed on and in contact with a top surface of a gate dielectric layer 156 of the gate structure and disposed along and in contact with sidewalls of the conductive capping layer (any surface including the bottom surface of 190 can be interpreted as a sidewall) and the gate metal layer 166 (as shown).
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Wang’s teachings to Wong’s semiconductor device to have the feature as claimed depending on formation method of air gaps and to reduce effective capacitance further by forming air spacers adjacent to the gate to improve device reliability (Wang, col.1, lines 15-50).
Wong in view of Wu and wang still further does not explicitly talk about a conductive capping layer.
Lin teaches in Fig. 2R about a conductive capping layer 125 disposed on the gate structure [0029].
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Lin’s teachings to Wong’s semiconductor device to have a conductive capping layer disposed on the gate structure and which would be adjacent to Wong’s first air spacer and thereby protect the gate electrode from damage or loss during subsequent processing (Lin, [0029]).
It would have been obvious to one of ordinary skill in the art at the time of the application was filed to have the material as claimed, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 15: Wong teaches in Fig. 18A-18D wherein a second dielectric layer 242 or 242+240 disposed on the contact structure, wherein a portion of the second dielectric layer surrounds the first air spacer.
Claim 16 is rejected under 35 U.S.C. 103 as being obvious over Wong et al (US 2021/0036122 A1) in view of Wu et al. (US PGPUB 2020/0411415 A1), Wang et al. (US Patent 10692987 B2) and Lin et al. (US PGPUB 2021/0083046 A1) and further in view of Lee et al (US 2020/0105867 A1) and further in view of Kang et al. (US PGPUB 20210098592 A)
Regarding claim 16: Lee teaches in Fig. 2J wherein the first air spacer 150b has a top surface with a tapered profile and has a bottom surface with a curved profile. Kang also teaches in Fig. 2A the air spacer 169 has a top surface with a tapered profile.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Lee’s and Kang’s teachings to Wong’s semiconductor device to have the
Feature as claimed depending on the gate recess formation to form the capping layer and air -gap spacer is capped by adjusting the recess height (Kang, [0092]).
Claim 17-18, 20 are rejected under 35 U.S.C. 103 as being obvious over Wong et al (US 2021/0036122 A1) in view of Wang et al (US Patent 10692987 B2) and Liu et al. (DE 102020114875 A1)
Regarding claim 17: Wong teaches about a method, comprising:
forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on a substrate 202 (Fig. 3);
forming a polysilicon structure (210,212) on the superlattice structure (Fig. 4);
forming a source/drain (S/D) region 230 on the substrate (Fig. 7);
replacing the polysilicon structure and the second nanostructured layers with a gate structure 264 (Fig. 11),
forming a first air spacer on the gate structure (Fig. 13, 16, 17);
forming an opening on the S/D region (From Fig. 17 -18A where opening is created by removing 242 to fill 294);
forming a semiconductor layer with a first semiconductor portion on a top surface of the S/D region and a second semiconductor portion along sidewalls of the opening;
removing the first semiconductor portion from the top surface of the S/D region;
forming a conductive layer in the opening and on the second semiconductor portion of the
semiconductor layer; and
removing the second semiconductor portion of the semiconductor layer to form a second air
spacer along sidewalls of the conductive layer
Wong does not explicitly show forming a first air spacer on the gate structure.
Wang teaches in Fig. 18 forming a first air spacer 184 on the gate structure (furthermore there is no specific limitations of before or after for specific order of operation)
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to use Wang’s teachings to Wong’s method to have the first air spacer on the gate structure and thereby effectively decreasing the effective capacitance of the device to boosts the device performance (Wang, page 1).
Please refer to MPEP 2144.04 “ Changes in Sequence of Adding Ingredients“ as reproduced below.
Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959) (Prior art reference disclosing a process of making a laminated sheet wherein a base sheet is first coated with a metallic film and thereafter impregnated with a thermosetting material was held to render prima facie obvious claims directed to a process of making a laminated sheet by reversing the order of the prior art process steps.). See also In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930) (Selection of any order of mixing ingredients is prima facie obvious.).
Wong does not teach forming a semiconductor layer with a first semiconductor portion on a top surface of the S/D region and a second semiconductor portion along sidewalls of the opening;
removing the first semiconductor portion from the top surface of the S/D region;
forming a conductive layer in the opening and on the second semiconductor portion of the
semiconductor layer; and
removing the second semiconductor portion of the semiconductor layer to form a second air
spacer along sidewalls of the conductive layer.
Liu teaches in Fig. 18-21 forming a semiconductor layer 112 with a first semiconductor portion on a top surface of the S/D region 82 and a second semiconductor portion along sidewalls of the opening (Fig. 18);
removing the first semiconductor portion from the top surface of the S/D region (Fig. 19);
forming a conductive layer 118 in the opening and on the second semiconductor portion of the
semiconductor layer (Fig. 20); and
removing the second semiconductor portion of the semiconductor layer to form a second air
spacer 120 along sidewalls of the conductive layer (Fig. 21).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to use Liu’s teachings to Wong’s method to have the feature as claimed to form air spacer with known method to a known device resulting in a reduction in capacitance and improve device performance as Liu teaches in associated description of air gap 120.
Regarding claim 18: Wong teaches in forming an oxide layer 212a [0027] on the S/D region prior to forming the semiconductor layer.
Regarding 20: Wong in view of Wang teaches wherein forming the first air spacer (as explained in Claim 17, Wang teaches the first air spacer) comprising etching a high-k gate dielectric layer (Wong, [0037]) of the gate structure.
Allowable Subject Matter
Claims 1-8, 10-11, 21 are allowed. The following is an examiner's statement of reasons for
allowance:
The closet prior arts on records are Wong et al (US 2021/0036122 A1), Wu et al. (US PGPUB 2020/0411415 A1), Lin et al. (US PGPUB 2021/0083046 A1) and Kang et al. (US PGPUB 20210098592 A)
However none of the existing prior arts on record teaches either singularly or in combination about "an etch stop layer with a curved bottom profile disposed on and in contact with a top surface of the S/D region and a top surface of the silicide layer " in combination with other limitations as a whole as recited in claim 1. Moreover none of the prior arts on record would be obvious to modify without breaking the functionality of the devices.
Claims 2-8, 10-11, 21 are also allowed being dependent on allowed claim 1.
Response to Arguments
Applicant’s arguments, see pages 2-3, filed on 06/18/2026, with respect to the rejection(s) of claim(s) 12, 17 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wong et al (US 2021/0036122 A1) in view of Wu et al. (US PGPUB 2020/0411415 A1) further in view of Wang et al. (US Patent 10692987 B2) and Lin et al. (US PGPUB 2021/0083046 A1) for claim 12 and Wong et al (US 2021/0036122 A1) in view of Wang et al (US Patent 10692987 B2) and Liu et al. (DE 102020114875 A1) for claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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