DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/02/2026 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues against the 35 USC § 103 rejection using Lee et al. (US 2022/0189945 A1, hereinafter Lee ‘945) in view of Do et al. (US 2016/0056153 A1, hereinafter Do ‘153). Applicant argues that neither Lee ‘945 nor Do ‘153 teach the dimensions of the gate contact based on its proximity to source/drain contacts. Further, Applicant argues that Lee ‘945 does not provide a description “to guide a person having ordinary skill in the art to make P2 have a first dimension, to make P3 have a second dimension greater than the first dimension, and to make P1 have a third dimension greater than the second dimension (e.g. based upon proximity to source/drain contacts).” Lastly, Applicant argues Do ‘153 “merely provides that different gate contacts might have different dimensions, without any description to guide a person of ordinary skill in the art to select a certain size for a certain gate contact, let alone to select a size based upon the number of sides of a gate contact that are adjacent to source/drain contacts”.
Examiner respectfully disagrees with Applicant’s above arguments.
Examiner submits that Lee ‘945 discloses a contact design flexibility such that contact dimensions are different as shown in Para [0008] where it is disclosed that contact dimensions can vary based on design rules of widths and distances and in Para [0055] where Lee ‘945 further discloses that the widths of the contacts (P1-P3) of a standard cell device can vary as needed. Do ‘153 provides further evidence that one contact can be larger or smaller than another contact and further distinguishes between contact sizes by provides a teaching of a set of available contact size options. Do ‘153 teaches that flexibility in the design of contact dimensions is needed as it teaches in Para [0122] that contact dimensions can be set to improve device integration and to dimensions and spacings between structures so that, “the performance deterioration of the semiconductor device may be minimized”. A person of ordinary skill in the art will readily understand that there will be misalignment of structures during manufacturing and that spacing between structures, such as gates, sources and drains and contacts, can impact device parasitic capacitance, cross talk and electrical shorting. Lee ‘945 as modified by Do ‘153, then teaches that contact dimensions can vary and that these dimensions should vary to prevent device deterioration. And Lee ‘945 as modified by Do ‘153 provide dimension designs for these contacts. Examiner notes that it appears Applicant is also trying to address the device architecture design to minimize device deterioration as in the contact size impacting the reduction of contact resistance (Para [0049] of the Specification of the instant application).
Lee ‘945 teaches contact sizes can vary as needed and Do ‘153 provides further evidence that one contact can be larger or smaller than another contact. Further Do ‘153 teaches a set of options for those contact dimensions.
It is known to a person of ordinary skill in the art that contact dimensions will vary based on device architectural items, such as spacing and allowance for manufacturing process misalignment. It would obvious then for a person of ordinary skill in the art to choose from the set of preset contact options taught by Do ‘153 so that the contact provide spacing between gates and source drain areas so that they do not minimize device deterioration by avoiding choosing contact sizes that are either too large (which a person of ordinary skill in the art would know could result in parasitic capacitance or device shorts) or too small (which a person of ordinary skill in the art would know would impact electrical resistance of the signal). Using the teachings of Lee ‘945 as modified by Do ‘153, a person of ordinary skill in the art would then be inclined to select contact size options (D1, D2 and D3), that met the recited limitations of claim 1.
Regarding Claim 11, Applicant argues against the 35 USC § 103 rejection using Do et al. (US 2023/0143562 A1, hereinafter Do ‘562) in view of Lee et al. (US 2022/0189945 A1, hereinafter Lee ‘945) in view of Do et al. (US 2016/0056153 A1, hereinafter Do ‘153). Applicant argues that neither Lee ‘945 nor Do ‘562 nor Do ‘153 teach the dimensions of the gate contact based on its proximity to source/drain contacts. Further, Applicant argues that prior art does not provide a description “to guide a person having ordinary skill in the art to make P2 have a first dimension, to make P3 have a second dimension greater than the first dimension, and to make P1 have a third dimension greater than the second dimension (e.g. based upon proximity to source/drain contacts).” Lastly, Applicant argues Do ‘153 “merely provides that different gate contacts might have different dimensions, without any description to guide a person of ordinary skill in the art to select a certain size for a certain gate contact, let alone to select a size based upon the number of sides of a gate contact that are adjacent to source/drain contacts”.
Examiner respectfully disagrees with Applicant’s above arguments.
Examiner submits that Do ‘562 in view of Lee ‘945 discloses a contact design flexibility such that contact dimensions are different as shown in Para [0044] of Do ‘562 it is disclosed contact dimensions can vary based on design rules of widths and distances as it states “the gate contact may be spaced apart from each other by a certain distance or more” to improve the performance of the standard cell. Do ‘153 provides further evidence that one contact can be larger or smaller than another contact and further distinguishes between contact sizes by provides a teaching of a set of available contact size options. Do ‘153 teaches that flexibility in the design of contact dimensions is needed as it teaches in Para [0122] that contact dimensions can be set to improve device integration and to dimensions and spacings between structures so that, “the performance deterioration of the semiconductor device may be minimized”. A person of ordinary skill in the art will readily understand that there will be misalignment of structures during manufacturing and that spacing between structures, such as gates, sources and drains and contacts, can impact device parasitic capacitance, cross talk and electrical shorting. Do ‘562 as modified by Lee ‘945, then teaches that dimensions can vary and that these dimensions should vary to prevent device deterioration. And Do ‘153 provides dimension designs for these contacts. Examiner notes that it appears Applicant is also trying to address the device architecture design to minimize device deterioration as in the contact size impacting the reduction of contact resistance (Para [0049] of the Specification of the instant application).
Do ‘563 teaches contact sizes can vary as needed and Do ‘153 provides further evidence that one contact can be larger or smaller than another contact. Further Do ‘153 teaches a set of options for those contact dimensions.
It is known to a person of ordinary skill in the art that contact dimensions will vary based on device architectural items, such as spacing and allowance for manufacturing process misalignment. It would obvious then for a person of ordinary skill in the art to choose from the set of preset contact options taught by Do ‘153 so that the contact provide spacing between gates and source drain areas so that they do not minimize device deterioration by avoiding choosing contact sizes that are either too large (which a person of ordinary skill in the art would know could result in parasitic capacitance or device shorts) or too small (which a person of ordinary skill in the art would know would impact electrical resistance of the signal). Using the teachings of Do ‘562 as modified by Lee ‘945 as further modified by Do ‘153, a person of ordinary skill in the art would then be inclined to select contact size options (D1 and D2), that met the recited limitations of claim 11.
Claim Rejections - 35 USC § 112
Applicant’s Amendment of Claim 23 made in the Applicant’s Arguments of 02/02/2026 overcome the 35 USC § 112 rejections of the Office Action mailed on 11/03/2025. Therefore that 35 USC § 112 rejection of Claim 23 is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0189945 A1, hereinafter Lee ‘945), in view of Do et al. (US 2016/0056153 A1, hereinafter Do ‘153), in view of the following arguments.
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With respect to Claim 1 Lee ‘945 discloses an integrated circuit (Fig 8), comprising:
a first standard cell (C40, Fig 8, Para [0078]) having a first p-type field-effect transistor (pFET) (Para [0079] discloses pFET, Fig 8 discloses P type region) and a first n- type field-effect transistor (nFET) (Para [0079] discloses nFET, Fig 8 discloses N type region)) integrated;
a first gate, a second gate and a third gate (G1, G2 and G3 as shown in annotated Fig 8_1 of Lee ‘945, Para [0035] discloses gates) longitudinally oriented along a first direction (Y, Fig 8 discloses G1/G2/G3 longitudinally oriented in Y direction) and configured in the first standard cell (C40);
a first gate contact landing (P2, Fig 8, Para [0081]) on the first gate (G1) and being adjacent two source/drain (S/D) contacts on two opposite edges of the first gate (Fig 8 discloses P2 adjacent to two S/D contacts on opposite edges of G1);
a second gate contact landing (P3, Fig 8, Para [0081]) on the second gate (G2) and being adjacent a single S/D contact on one edge of the second gate (G2) (Fig 8 discloses P3 adjacent to one S/D contact); and
a third gate contact landing (P1, Fig 8, Para [0081]) on the third gate (G3) and being free from any S/D contact (Fig 8 discloses P3 is not adjacent to S/D contacts), wherein
But Lee ‘945 fails to explicitly disclose the first gate contact spans a first dimension (D1) along a second direction being orthogonal to the first direction, the second gate contact spans a second dimension (D2) along the second direction, the third gate contact spans a third dimension (D3) along the second direction, and D1 is less than D2 and D2 is less than D3.
Nevertheless, in a related endeavor (Fig 1-2 and 4 of Do ‘153), Do ‘153 teaches the first gate contact (CT3, Fig 4 of Do ‘153, Para [0072]) spans a first dimension (D1) (W3, Fig 4 of Do ‘153, Para [0073]) along a second direction (D2, Fig. 4 of Do ‘153, Para [0073]) being orthogonal to the first direction (D1 as shown in Fig. 4 of Do ‘153)(D1 being orthogonal to D2; D1 runs parallel to the gates, therefore is equivalent to dimension Y of Lee ‘945), the second gate contact (CT1, Fig 4 of Do ‘153, Para [0072]) spans a second dimension (D2) (W1, Fig 4 of Do ‘153, Para [0072]) along the second direction (D2, Fig. 4 of Do ‘153, Para [0073]), the third gate contact (CT2, Fig 4 of Do ‘153, Para [0072]) spans a third dimension (D3) (W2, Fig 4 of Do ‘153, Para [0072]) along the second direction (D2, Fig. 4 of Do ‘153, Para [0073]), and D1 (W3) is less than D2 (W1)(Para [0108] of Do ‘153 discloses W3<W1) and D2 (W1) is less than D3 (W2)(Para [0108] of Do ‘153 discloses W2 is greater than W1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘153’s teaching of the first gate contact spans a first dimension (D1) along a second direction being orthogonal to the first direction, the second gate contact spans a second dimension (D2) along the second direction, the third gate contact spans a third dimension (D3) along the second direction, and D1 is less than D2 and D2 is less than D3 into Lee ‘945’s device. Lee ‘945 discloses a standard cell device with three gate contacts, but fails to explicitly disclose the dimensions of those gate contacts in the X direction. Do ‘153 teaches a standard cell device and, in Para [0078] teaches having gate contacts of differing widths of the via contacts provides freedom in locating the contacts. (From Do ’153, “…since the first and second widths W1 and W2 of the first and second contacts CT and CT2 are greater than the third width W3 of the third contact CT3, positions of the via-contacts VC may be relatively free on the first to third contacts CT1, CT2, and CT3”). Therefore the ordinary artisan would have been motivated to modify Lee ‘945 in the manner set forth above, at least, because the dimensional differences taught by Do ‘153 provides design flexibility in placing the gate contacts.
As incorporated, the gate contact dimensions (W1/W2/W3) in the second direction and their sizes relative to each other taught by Do ‘153 would be used, as the gate contact (P1/P2/P3 of Lee ‘945) dimensions in the second direction (X), along with their sizes relative to each other, in the device of Lee ‘945.
With respect to Claim 2 Lee ‘945 as modified by Do ‘153 discloses all limitations of the integrated circuit of claim 1, but Lee ‘945 as modified by Do ‘153 fails to explicitly disclose wherein a first ratio D2/D1 is equal to a second ratio D3/D2.
However, it appears that Claim 1 is broad enough to allow the obvious optimization of the results-effective variable of designing pads of dimensions to achieve the well-known advantage of forming pads to connectors that respect the available space (that is fits the space dimension and does not contact adjacent structures) for the pad layout.
Therefore, it would be obvious for one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘945’s design rules to achieve the results oriented variable of a first ratio D2/D1 is equal to a second ratio D3/D2. MPEP §2144.05 (II)(B).
The ordinary artisan would have been motivated to modify Lee ‘945 as modified by Do ‘153 in the manner set forth above, at least, because as Lee ‘945 states in Para (0004) "In order to stably exchange signals between the plurality of cells, the standard of the connection lines may have to satisfy a predetermined design rule. The design rule may include various rules such as a minimum width rule, a minimum length rule, a minimum area rule, an enclosure rule, and an interval rule." and then Para (0082) states that the pin must satisfy the enclosure rule. Paras (0005, 0007 and 0008) of Lee ‘945 further disclose the motivation of creating connections with the shortest length to achieve stated signal stability.
With respect to Claim 3 Lee ‘945 as modified by Do ‘153 discloses all limitations of the integrated circuit of claim 2, but Lee ‘945 as modified by Do ‘153 fails to explicitly disclose wherein each of the first ratio D2/D1 and the second ratio D3/D2 ranges between 1.2 and 1.5.
However, it appears that Claim 1 is broad enough to allow the obvious optimization of the results-effective variable of designing pads of dimensions to achieve the well-known advantage of forming pads to connectors that respect the available space (that is fits the space dimension and does not contact adjacent structures) for the pad layout.
Therefore, it would be obvious for one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘945’s design rules to achieve the first ratio D2/D1 and the second ratio D3/D2 ranges between 1.2 and 1.5. MPEP §2144.05 (II)(B).
The ordinary artisan would have been motivated to modify Lee ‘945 as modified by Do ‘153 in the manner set forth above, at least, because as Lee ‘945 states in Para (0004) "In order to stably exchange signals between the plurality of cells, the standard of the connection lines may have to satisfy a predetermined design rule. The design rule may include various rules such as a minimum width rule, a minimum length rule, a minimum area rule, an enclosure rule, and an interval rule." and then Para (0082) states that the pin must satisfy the enclosure rule. Paras (0005, 0007 and 0008) of Lee ‘945 further disclose the motivation of creating connections with the shortest length to achieve stated signal stability.
Claims 4-7 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘945 in view of Do ‘153 in further view of Do et al. (US 2023/0143562 A1, hereinafter Do ‘562), in view of the following arguments.
With respect to Claim 4 Lee ‘945 as modified by Do ‘153 discloses all limitations of the integrated circuit of claim 1, but Lee ‘945 as modified by Do ‘153 fails to explicitly disclose further comprising a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated; and a first dielectric gate disposed between the first standard cell and the second standard cell.
Nevertheless, in a related endeavor (Fig 7 of Do ‘562), Do ‘562 teaches further comprising a second standard cell (STCB, Fig 7 of Do ‘562, Para [0079]) being adjacent to the first standard cell (STCA, Fig 7 of Do ‘562, Para [0079])(Para [0083] of Do ‘562 discloses STCA arranged adjacently), having a second pFET (RX1, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as p-type) and a second nFET (RX2, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as n-type) integrated; and a first dielectric gate (DG2, Fig 7 of Do ‘562, Para [0083]) disposed between the first standard cell (STCA) and the second standard cell (STCB).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘562’s teaching of a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated; and a first dielectric gate disposed between the first standard cell and the second standard cell into Lee ‘945 as modified by Do ‘153’s device. The ordinary artisan would have been motivated to modify Lee ‘945 as modified by Do ‘153 in the manner set forth above, at least, because, as Do ‘562 teaches in Para [0028 and 0029] standard cells can form integrated circuits by arranging them adjacent to each other, various arrangements resulting in the circuit functionalities described in Para [0029] of Do ‘562.
As incorporated, the teaching of Do ‘562 of two standard cells arranged adjacent to each other with a first dielectric gate (DG2 of Do ‘562) between them would be used as an arrangement of the standard cell (C40) of Lee ‘945 as modified by Do ‘153.
With respect to Claim 5 Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 discloses all limitations of the integrated circuit of claim 4, and Do ‘562 discloses further comprising a second dielectric gate (SDB, Para [0081] of Do ‘562) disposed between the first standard cell (STCA) and the second standard cell (STCB); and
spanning between the first dielectric gate (DG2) and the second dielectric gate (SDB), wherein the first dielectric gate (DG2) is disposed on a boundary (right side of STCA as shown in Fig 7 of Do ‘562) of the first standard cell (STCA), and the second dielectric gate (SDB) is disposed on a boundary (left side of STCB)(Para [0082] of Do ‘562 discloses SDB between the two standard cells) of the second standard cell (STCB).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘562’s further teaching of a second dielectric gate disposed between the first standard cell and the second standard cell; and spanning between the first dielectric gate and the second dielectric gate, wherein the first dielectric gate is disposed on a boundary of the first standard cell, and the second dielectric gate is disposed on a boundary of the second standard cell into Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562’s device. The ordinary artisan would have been motivated to modify Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 in the manner set forth above, at least, because, adding the additional second dielectric gate (SDB) between the adjacent standard cells would provide an additional dielectric layer to prevent electrical signal cross talk between adjacent cells.
As incorporated, the teaching of Do ‘562 of using a second dielectric gate (SDB) between the first and second standard cell would be incorporated between the first and second standard cell (C40) of Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562.
But in the current embodiment, Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 fails to explicitly disclose a first fill cell configured between the first standard cell and the second standard cell.
Nevertheless, in a related embodiment (Fig 1 and 3 of Do ‘562), Do ‘562 teaches a first fill cell (STC, Fig 3 of Do ‘562 discloses an arrangement of standard cells and Para [0030] of Do ‘562 teaches that standard cell arrangements may include a filler cell) configured between the first standard cell (CA1, Fig 3 of Do ‘562, Para [0049]) and the second standard cell (CA2, Fig 3 of Do 562, Para [0049]).
Therefore it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘562’s fill cell between the adjacent first and second standard cells of Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562, and thereby, modified Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562’s device will have a fill cell (STC of Do ‘562) between standard cells (C40) as discussed above.
The ordinary artisan would have been motivated to modify Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 in the manner set forth above, at least, because this inclusion provides, as taught by Do ‘562 (Para [0030]), “The filler cell may be arranged adjacent to a functional cell to provide routing of signals provided to the functional cell or output from the functional cell. Also, the filler cell may be a cell used to fil a space remaining after functional cells are arranged”.
With respect to Claim 6 Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 discloses all limitations of the integrated circuit of claim 5, and Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 teaches further wherein the first fill cell (STC) further comprises includes a third dielectric gate (DDB, Fig 1 of Do ‘562, Para [0034] discloses a double or single diffusion break may be formed a the STC cell boundary) interposed between the first dielectric gate (DG2) and the second dielectric gate (SDB).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘562’s teaching of first fill cell further comprises includes a third dielectric gate interposed between the first dielectric gate and the second dielectric gate of Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562, and thereby, modified Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562’s device will have a third dielectric gate between standard cells (C40) as discussed above.
The ordinary artisan would have been motivated to further modify Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 in the manner set forth above, at least, because, adding the additional second dielectric gate (SDB) between the adjacent standard cells would provide an additional dielectric layer to prevent electrical signal cross talk between adjacent cells.
As incorporated, the fill cell of Do ‘562 (STC) with two diffusion breaks (SDB and DDB) would be inserted between standard cells (C40 of Lee ‘945).
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With respect to Claim 7 Lee ‘945 as modified by Do ‘153 and further modified by Do ‘562 discloses all limitations of the integrated circuit of claim 5, and Lee ‘945 discloses further wherein
the first pFET and the second pFET (Para [0079] of Lee ‘945 discloses a plurality of pFET and nFET) are formed on a first continuous active region (RX1, as shown in annotated Fig 8_1 of Lee ‘945, Para [0049]);
the first nFET and the second nFET (Para [0079] of Lee ‘945 discloses a plurality of pFET and nFET) are formed on a second continuous active region (RX2, as shown in annotated Fig 8_1 of Lee ‘945, Para [0049]);
the first continuous active region (RX1) and the second continuous active regions (RX2) are longitudinally oriented along the second direction (X)( as shown in annotated Fig 8_1 of Lee ‘945 discloses RX1 and RX2 longitudinally oriented in X direction); and
the first dielectric gate (right most Diffusion Break) and the second dielectric gate (left most Diffusion Break) are longitudinally oriented along the first direction (Y) and extend from the first continuous active region (RX1) to the second continuous active region (RX2)(annotated Fig 8_1 of Lee ‘945 discloses first and second dielectric gate extend in the Y direction).
With respect to Claim 11 Do ‘562 discloses an integrated circuit (Fig 7), comprising:
a first standard cell (STCA, Fig 7 of Do ‘562, Para [0079]) having a first p-type field-effect transistor (pFET) (RX1, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as p-type) and a first n- type field-effect transistor (nFET) integrated (RX2, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as n-type), and having a first dielectric gate (DG2, Fig 7 of Do ‘562, Para [0083]) on a first standard cell boundary (right boundary of STCA as shown in Fig 7 of Do ‘562);
a second standard cell (STCB, Fig 7 of Do ‘562, Para [0079]) being adjacent to the first standard cell (STCA)(Para [0083] of Do ‘562 discloses STCA arranged adjacently), having a second pFET (RX1 of STCB, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as p-type) and a second nFET integrated (RX2 pf STCB, Fig 7 of Do ‘562, Para [0079 and 0036] disclose RX1 as n-type), and having a second dielectric gate (DG2 of STCB, Fig 7 of Do ‘562, Para [0083]) on a second standard cell boundary (right boundary of STCB as shown in Fig 7 of Do ‘562); and
But in the current embodiment Do ‘562 fails to explicitly disclose a first fill cell configured between the first standard cell and the second standard cell, and spanning between the first dielectric gate and the second dielectric gate.
Nevertheless, in another embodiment (Fig 1 and 3 of Do ‘562), Do ‘562 teaches a first fill cell (STC, Fig 3 of Do ‘952 discloses an arrangement of standard cells and Para [0030] of Do ‘562 teaches that standard cell arrangements may include a filler cell) configured between the first standard cell (CA1, Fig 3 of Do ‘562, Para [0049]) and the second standard cell (CA2, Fig 3 of Do 562, Para [0049]) and spanning between the first dielectric gate (first cell DDB) and the second dielectric gate (second cell DDB) (DDB, Fig 1 of Do ‘562, Para [0034] discloses a double or single diffusion break may be formed a the STC cell boundary).
Therefore it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘562’s additional teaching of a fill cell between the dielectric gates of adjacent first and second standard cells of the first embodiment of Do ‘562, and thereby, modified Do 562’s device will have a fill cell (STC of Do ‘562) between standard cells (STCA) and (STCB) as discussed above.
The ordinary artisan would have been motivated to modify Do ‘562 in the manner set forth above, at least, because this inclusion provides, as taught by Do ‘562 (Para [0030]), “The filler cell may be arranged adjacent to a functional cell to provide routing of signals provided to the functional cell or output from the functional cell. Also, the filler cell may be a cell used to fill a space remaining after functional cells are arranged”. Incorporating a fill cell between the two dielectric gates would provide protection against parasitic capacitance between standard cells.
But Do ‘562 fails to explicitly disclose wherein the first standard cell further comprises: a first gate and a second gate longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two source/drain (S/D) contacts on two opposite edges of the first gate; and a second gate contact landing on the second gate and being adjacent a single S/D contact on one edge of the second gate, wherein the first gate contact spans a first dimension (D1) along a second direction being orthogonal to the first direction, the second gate contact spans a second dimension (D2) along the second direction, and D1 is less than D2.
Nevertheless, in a related endeavor (Fig 8 of Lee ‘945) Lee ‘945 discloses wherein the first standard cell (C40, Fig 8 of Lee ‘945, Para [0078]) further comprises: a first gate and a second gate (G1 and G2 as shown in annotated Fig 8_1 of Lee ‘945, Para [0035] discloses gates) longitudinally oriented along a first direction (Y, Fig 8 of Lee ‘945 discloses G1/G2/G3 longitudinally oriented in Y direction) and configured in the first standard cell (C40); a first gate contact landing (P2, Fig 8, Para [0081]) on the first gate (G1) and being adjacent two source/drain (S/D) contacts on two opposite edges of the first gate (Fig 8 discloses P2 adjacent to two S/D contacts on opposite edges of G1);
a second gate contact landing (P3, Fig 8, Para [0081]) on the second gate (G2) and being adjacent a single S/D contact on one edge of the second gate (G2) (Fig 8 discloses P3 adjacent to one S/D contact); and
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘945’s teaching of the first standard cell further comprises: a first gate and a second gate longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two source/drain (S/D) contacts on two opposite edges of the first gate; and a second gate contact landing on the second gate and being adjacent a single S/D contact on one edge of the second gate into Do ‘562’s device. The ordinary artisan would have been motivated to modify Do ‘562 in the manner set forth above, at least, the first and second gates in the standard cell provide additional functionality to the device and the spacing of the gate contacts from the source/drain provides a gap between contacts that helps to prevent parasitic capacitance between the source/drain contacts and the gate contacts.
As incorporated, the first and second gate with gate contact spacing orientation taught by Lee ‘945 would be used in the standard cell (SCTA) of Do ‘562.
But Do ‘562 as modified by Lee ‘945 fails to explicitly disclose the first gate contact spans a first dimension (D1) along a second direction being orthogonal to the first direction, the second gate contact spans a second dimension (D2) along the second direction, and D1 is less than D2.
Nevertheless, in a related endeavor (Fig 1-2 and 4 of Do ‘153), Do ‘153 teaches the first gate contact (CT3, Fig 4 of Do ‘153, Para [0072]) spans a first dimension (D1) (W3, Fig 4 of Do ‘153, Para [0073]) along a second direction (D2, Fig. 4 of Do ‘153, Para [0073]) being orthogonal to the first direction (D1 as shown in Fig. 4 of Do ‘153)(D1 being orthogonal to D2; D1 runs parallel to the gates, therefore is equivalent to dimension Y of Lee ‘945), the second gate contact (CT1, Fig 4 of Do ‘153, Para [0072]) spans a second dimension (D2) (W1, Fig 4 of Do ‘153, Para [0072]) along the second direction (D2, Fig. 4 of Do ‘153, Para [0073]), and D1 (W3) is less than D2 (W1)(Para [0108] of Do ‘153 discloses W3<W1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘153’s teaching of the first gate contact spans a first dimension (D1) along a second direction being orthogonal to the first direction, the second gate contact spans a second dimension (D2) along the second direction, and D1 is less than D2 into Do ‘562 as modified by Lee ‘945’s device. Lee ‘945 discloses a standard cell device with two gate contacts, but fails to explicitly disclose the dimensions of those gate contacts in the X direction. Do ‘153 teaches a standard cell device and, in Para [0078] teaches having gate contacts of differing widths of the via contacts provides freedom in locating the contacts. (From Do ’153, “…since the first and second widths W1 and W2 of the first and second contacts CT and CT2 are greater than the third width W3 of the third contact CT3, positions of the via-contacts VC may be relatively free on the first to third contacts CT1, CT2, and CT3”). Therefore the ordinary artisan would have been motivated to modify Do ‘562 as modified by Lee ‘945 in the manner set forth above, at least, because the dimensional differences taught by Do ‘153 provides design flexibility in placing the gate contacts.
As incorporated, the gate contact dimensions (W1/W3) in the second direction and their sizes relative to each other taught by Do ‘153 would be used, as the first and second gate contact (P3/P2) of Do ‘562 as modified by Lee ‘945, dimensions in the second direction (X), along with their sizes relative to each other, in the device of Do ‘562 as modified by Lee ‘945.
With respect to Claim 12 Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 discloses all limitations of the integrated circuit of claim 11, and Lee ‘945 further discloses wherein
the first pFET and the second pFET (Para [0079] of Lee ‘945 discloses a plurality of pFET and nFET in active regions) are formed on a first continuous active region, (RX1, Fig 8 of Lee ‘945, Para [0049]) and
the first nFET and the second nFET (Para [0079] of Lee ‘945 discloses a plurality of pFET and nFET in active regions) are formed on a second continuous active region (RX2, Fig 8 of Lee ‘945, Para [0049]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘945’s the first pFET and the second pFET are formed on a first continuous active region, and the first nFET and the second nFET are formed on a second continuous active region into Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153’s device. The ordinary artisan would have been motivated to modify Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 in the manner set forth above, at least, because having a plurality of pFET and nFET in the first and second active regions respectively provide additional functionality to the standard cell.
As incorporated, the first pFET and the second pFET are formed on a first continuous active region, and the first nFET and the second nFET are formed on a second continuous active region as further taught by Lee ‘945 would be used in standard cells (STCA/STCB) of Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153.
With respect to Claim 13 Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 discloses all limitations of the integrated circuit of claim 12, and in a further embodiment Lee ‘945 (Fig 6A-6C of Lee ‘945) further discloses wherein
each of the first continuous active region (RX1) and the second continuous active region (RX2) comprises multiple channels vertically stacked (Fig 6A of Lee ‘945 discloses channels CB1 and VA0 and Para [0065] discloses additional gate channels not shown in the cross section Fig 6A); and
each of the first gate (G1, Fig 6A of Lee ‘945, Para [0065]) and the second gate (G2, Fig 6A, although not shown in cross section Fig 6A, Para [0065] discloses gate channels G1-G6) wraps around the multiple channels (Fig 6A of Lee ‘945 discloses channels CB1 and VA0 and Para [0065] discloses additional gate channels not shown in the cross section Fig 6A).
Therefore it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the further teachings of Lee ‘945 of each of the first continuous active region and the second continuous active region comprising multiple channels vertically stacked and each of the first gate and the second gate wrapping around the multiple channels into the device of Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 and thereby, modified Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153’s device will have multiple channels, vertically stacked in the active regions (RX1 and RX2) where the first (G1) and second gate (G2) wrap around the multiple channels.
The ordinary artisan would have been motivated to modify Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 in the manner set forth above, at least, because this inclusion provides multiple functional gates increasing the functionality (NAND gate or AND gate or NOR gate or OR gate, etc.) of the cell such as those taught by Lee ‘953 in Para (0028).
With respect to Claim 14 Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 discloses all limitations of the integrated circuit of claim 12, and Lee ‘945 discloses further comprising:
a third gate (G3, as shown in annotated Fig 8_1 of Lee ‘945, Para [0035] of Lee ‘945 discloses gates) longitudinally oriented along the first direction (X) and configured in the first standard cell (C40); and
a third gate contact (P1, Fig 8 of Lee ‘945, Para [0081]) landing on the third gate and being free from any S/D contact (Fig 8 discloses P1 not surrounded by any S/D contact),
But Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 fails to explicitly disclose wherein the third gate contact spans a third dimension (D3) along the second direction, and wherein D3 is greater than D2.
Nevertheless, in a related endeavor (Fig 1-2 and 4 of Do ‘153), Do ‘153 teaches wherein the third gate contact (CT2, Fig 4 of Do ‘153, Para [0072]) spans a third dimension (D3) (W2, Fig 4 of Do ‘153, Para [0072]) along the second direction (D2, Fig. 4 of Do ‘153, Para [0073]), and wherein D3 (W2) is greater than D2 (W1)(Para [0108] of Do ‘153 discloses W2 is greater than W1).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Do ‘153’s teaching of the third gate contact spans a third dimension (D3) along the second direction, and wherein D3 is greater than D2 into Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153’s device. Do ‘153 teaches a standard cell device and, in Para [0078] teaches having gate contacts of differing widths of the via contacts provides freedom in locating the contacts. (From Do ’153, “…since the first and second widths W1 and W2 of the first and second contacts CT and CT2 are greater than the third width W3 of the third contact CT3, positions of the via-contacts VC may be relatively free on the first to third contacts CT1, CT2, and CT3”). Therefore the ordinary artisan would have been motivated to modify Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153 in the manner set forth above, at least, because the dimensional differences taught by Do ‘153 provides design flexibility in placing the gate contacts.
As incorporated, the gate contact dimension (W2) in the second direction and its size relative to W1 taught by Do ‘153 would be used, as the gate contact (P1 of Lee ‘945) dimensions in the second direction (X), along with their sizes relative to each other, in the device of Do ‘562 as modified by Lee ‘945 and further modified by Do ‘153.
Allowable Subject Matter
Claims 21-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 21-23: Allowable subject matter has been indicated because the closest prior art of record, Lee et al. (US 2022/0189945 A1), Do et al. (US 2016/0056153 A1), and Do et al. (US 2023/0143562 A1) either alone or in combination, fails to teach or fairly suggest the feature: “a third S/D contact overlying the first S/D contact and the first fin, wherein the third S/D contact does not overlie the second fin; and a fourth S/D contact overlying the second S/D contact and the second fin, wherein the fourth S/D contact does not overlie the first fin”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 24, Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “and the first length is greater than the second length”.
Closest prior art of record Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) teaches the limitations of claim 1, and teaches, “wherein the adjacent two S/D contacts are a first S/D contact having a first length in the first direction and a second S/D contact having a second length in the first direction”, however Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) fail to disclose “and the first length is greater than the second length”.
Regarding Claim 25, Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “a fourth gate spaced apart from the first gate in the first direction, longitudinally oriented along the first direction, and configured in the first standard cell; and a fourth gate contact landing on the fourth gate”.
Closest prior art of record Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) teaches the limitations of claim 1, however Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) fail to disclose “a fourth gate spaced apart from the first gate in the first direction, longitudinally oriented along the first direction, and configured in the first standard cell; and a fourth gate contact landing on the fourth gate”.
Regarding Claim 26, Allowable subject matter has been indicated because the closest prior art of record, either alone or in combination, fails to teach or fairly suggest the feature: “a second metal line adjacent the first metal line and spaced apart from the first metal line by a first spacing; and a third metal line adjacent the second metal line and spaced apart from the second metal line by a second spacing different than the first spacing”.
Closest prior art of record Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) teaches the limitations of claim 1 and teaches “further comprising a first metal line overlying the second gate contact and the third gate contact”, however Lee et al. (US 2022/0189945 A1) and Do et al. (US 2023/0143562 A1) fail to disclose “a second metal line adjacent the first metal line and spaced apart from the first metal line by a first spacing; and a third metal line adjacent the second metal line and spaced apart from the second metal line by a second spacing different than the first spacing”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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